xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/rk3288-evb-rk628-rgb2dsi-avb.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
3
4/dts-v1/;
5#include "rk3288-evb-rk628.dtsi"
6
7&rk628_dsi0 {
8	status = "okay";
9
10	ports {
11		#address-cells = <1>;
12		#size-cells = <0>;
13
14		port@0 {
15			reg = <0>;
16
17			dsi0_in_post_process: endpoint {
18				remote-endpoint = <&post_process_out_dsi0>;
19			};
20		};
21	};
22
23	panel@0 {
24		compatible = "simple-panel-dsi";
25		reg = <0>;
26		backlight = <&backlight>;
27		enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
28		prepare-delay-ms = <120>;
29		enable-delay-ms = <120>;
30		disable-delay-ms = <120>;
31		unprepare-delay-ms = <120>;
32		init-delay-ms = <120>;
33
34		dsi,flags = <(MIPI_DSI_MODE_VIDEO |
35			      MIPI_DSI_MODE_VIDEO_BURST |
36			      MIPI_DSI_MODE_LPM |
37			      MIPI_DSI_MODE_EOT_PACKET)>;
38		dsi,format = <MIPI_DSI_FMT_RGB888>;
39		dsi,lanes = <4>;
40
41		panel-init-sequence = [
42			39 00 04 ff 98 81 03
43			39 00 02 01 00
44			39 00 02 02 00
45			39 00 02 03 53
46			39 00 02 04 53
47			39 00 02 05 13
48			39 00 02 06 04
49			39 00 02 07 02
50			39 00 02 08 02
51			39 00 02 09 00
52			39 00 02 0a 00
53			39 00 02 0b 00
54			39 00 02 0c 00
55			39 00 02 0d 00
56			39 00 02 0e 00
57			39 00 02 0f 00
58			39 00 02 10 00
59			39 00 02 11 00
60			39 00 02 12 00
61			39 00 02 13 00
62			39 00 02 14 00
63			39 00 02 15 08
64			39 00 02 16 10
65			39 00 02 17 00
66			39 00 02 18 08
67			39 00 02 19 00
68			39 00 02 1a 00
69			39 00 02 1b 00
70			39 00 02 1c 00
71			39 00 02 1d 00
72			39 00 02 1e c0
73			39 00 02 1f 80
74			39 00 02 20 02
75			39 00 02 21 09
76			39 00 02 22 00
77			39 00 02 23 00
78			39 00 02 24 00
79			39 00 02 25 00
80			39 00 02 26 00
81			39 00 02 27 00
82			39 00 02 28 55
83			39 00 02 29 03
84			39 00 02 2a 00
85			39 00 02 2b 00
86			39 00 02 2c 00
87			39 00 02 2d 00
88			39 00 02 2e 00
89			39 00 02 2f 00
90			39 00 02 30 00
91			39 00 02 31 00
92			39 00 02 32 00
93			39 00 02 33 00
94			39 00 02 34 04
95			39 00 02 35 05
96			39 00 02 36 05
97			39 00 02 37 00
98			39 00 02 38 3c
99			39 00 02 39 35
100			39 00 02 3a 00
101			39 00 02 3b 40
102			39 00 02 3c 00
103			39 00 02 3d 00
104			39 00 02 3e 00
105			39 00 02 3f 00
106			39 00 02 40 00
107			39 00 02 41 88
108			39 00 02 42 00
109			39 00 02 43 00
110			39 00 02 44 1f
111			39 00 02 50 01
112			39 00 02 51 23
113			39 00 02 52 45
114			39 00 02 53 67
115			39 00 02 54 89
116			39 00 02 55 ab
117			39 00 02 56 01
118			39 00 02 57 23
119			39 00 02 58 45
120			39 00 02 59 67
121			39 00 02 5a 89
122			39 00 02 5b ab
123			39 00 02 5c cd
124			39 00 02 5d ef
125			39 00 02 5e 03
126			39 00 02 5f 14
127			39 00 02 60 15
128			39 00 02 61 0c
129			39 00 02 62 0d
130			39 00 02 63 0e
131			39 00 02 64 0f
132			39 00 02 65 10
133			39 00 02 66 11
134			39 00 02 67 08
135			39 00 02 68 02
136			39 00 02 69 0a
137			39 00 02 6a 02
138			39 00 02 6b 02
139			39 00 02 6c 02
140			39 00 02 6d 02
141			39 00 02 6e 02
142			39 00 02 6f 02
143			39 00 02 70 02
144			39 00 02 71 02
145			39 00 02 72 06
146			39 00 02 73 02
147			39 00 02 74 02
148			39 00 02 75 14
149			39 00 02 76 15
150			39 00 02 77 0f
151			39 00 02 78 0e
152			39 00 02 79 0d
153			39 00 02 7a 0c
154			39 00 02 7b 11
155			39 00 02 7c 10
156			39 00 02 7d 06
157			39 00 02 7e 02
158			39 00 02 7f 0a
159			39 00 02 80 02
160			39 00 02 81 02
161			39 00 02 82 02
162			39 00 02 83 02
163			39 00 02 84 02
164			39 00 02 85 02
165			39 00 02 86 02
166			39 00 02 87 02
167			39 00 02 88 08
168			39 00 02 89 02
169			39 00 02 8a 02
170			39 00 04 ff 98 81 04
171			39 00 02 00 80
172			39 00 02 70 00
173			39 00 02 71 00
174			39 00 02 66 fe
175			39 00 02 82 15
176			39 00 02 84 15
177			39 00 02 85 15
178			39 00 02 3a 24
179			39 00 02 32 ac
180			39 00 02 8c 80
181			39 00 02 3c f5
182			39 00 02 88 33
183			39 00 04 ff 98 81 01
184			39 00 02 22 0a
185			39 00 02 31 00
186			39 00 02 53 78
187			39 00 02 55 7b
188			39 00 02 60 20
189			39 00 02 61 00
190			39 00 02 62 0d
191			39 00 02 63 00
192			39 00 02 a0 00
193			39 00 02 a1 10
194			39 00 02 a2 1c
195			39 00 02 a3 13
196			39 00 02 a4 15
197			39 00 02 a5 26
198			39 00 02 a6 1a
199			39 00 02 a7 1d
200			39 00 02 a8 67
201			39 00 02 a9 1c
202			39 00 02 aa 29
203			39 00 02 ab 58
204			39 00 02 ac 26
205			39 00 02 ad 28
206			39 00 02 ae 5c
207			39 00 02 af 30
208			39 00 02 b0 31
209			39 00 02 b1 32
210			39 00 02 b2 00
211			39 00 02 c0 00
212			39 00 02 c1 10
213			39 00 02 c2 1c
214			39 00 02 c3 13
215			39 00 02 c4 15
216			39 00 02 c5 26
217			39 00 02 c6 1a
218			39 00 02 c7 1d
219			39 00 02 c8 67
220			39 00 02 c9 1c
221			39 00 02 ca 29
222			39 00 02 cb 5b
223			39 00 02 cc 26
224			39 00 02 cd 28
225			39 00 02 ce 5c
226			39 00 02 cf 30
227			39 00 02 d0 31
228			39 00 02 d1 2e
229			39 00 02 d2 32
230			39 00 02 d3 00
231			39 00 04 ff 98 81 00
232			05 fa 01 11
233			05 14 01 29
234		];
235
236		panel-exit-sequence = [
237			05 00 01 28
238			05 00 01 10
239		];
240
241		display-timings {
242			native-mode = <&timing0>;
243
244			timing0: timing0 {
245				clock-frequency = <64000000>;
246				hactive = <720>;
247				vactive = <1280>;
248				hfront-porch = <40>;
249				hsync-len = <10>;
250				hback-porch = <40>;
251				vfront-porch = <22>;
252				vsync-len = <4>;
253				vback-porch = <11>;
254				hsync-active = <0>;
255				vsync-active = <0>;
256				de-active = <0>;
257				pixelclk-active = <0>;
258			};
259		};
260	};
261};
262
263&rk628_combtxphy {
264	status = "okay";
265};
266
267&rk628_post_process {
268	pinctrl-names = "default";
269	pinctrl-0 = <&rk628_vop_pins>;
270	status = "okay";
271
272	ports {
273		#address-cells = <1>;
274		#size-cells = <0>;
275
276		port@0 {
277			reg = <0>;
278
279			post_process_in_rgb: endpoint {
280				remote-endpoint = <&rgb_out_post_process>;
281			};
282		};
283
284		port@1 {
285			reg = <1>;
286
287			post_process_out_dsi0: endpoint {
288				remote-endpoint = <&dsi0_in_post_process>;
289			};
290		};
291	};
292};
293
294&rgb {
295	status = "okay";
296
297	ports {
298		port@1 {
299			reg = <1>;
300
301			rgb_out_post_process: endpoint {
302				remote-endpoint = <&post_process_in_rgb>;
303			};
304		};
305	};
306};
307
308&video_phy {
309	status = "okay";
310};
311
312&rgb_in_vopb {
313	status = "disabled";
314};
315
316&rgb_in_vopl {
317	status = "okay";
318};
319
320&route_rgb {
321	connect = <&vopl_out_rgb>;
322	status = "disabled";
323};
324
325&vopb {
326	assigned-clocks = <&cru DCLK_VOP0>;
327	assigned-clock-parents = <&cru PLL_GPLL>;
328};
329
330&vopl {
331	assigned-clocks = <&cru DCLK_VOP1>;
332	assigned-clock-parents = <&cru PLL_CPLL>;
333};
334