1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 3 4/dts-v1/; 5#include "rk3288-evb-rk628.dtsi" 6 7/ { 8 vcc33_lcd: vcc33-lcd { 9 compatible = "regulator-fixed"; 10 regulator-name = "vcc33_lcd"; 11 regulator-boot-on; 12 gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; 13 enable-active-high; 14 }; 15 16 panel { 17 compatible = "simple-panel"; 18 backlight = <&backlight>; 19 power-supply = <&vcc33_lcd>; 20 enable-gpios = <&gpio5 RK_PC1 GPIO_ACTIVE_HIGH>; 21 prepare-delay-ms = <20>; 22 enable-delay-ms = <20>; 23 disable-delay-ms = <20>; 24 unprepare-delay-ms = <20>; 25 bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>; 26 27 display-timings { 28 native-mode = <&timing0>; 29 30 timing0: timing0 { 31 clock-frequency = <149000000>; 32 hactive = <1920>; 33 vactive = <1080>; 34 hback-porch = <96>; 35 hfront-porch = <120>; 36 vback-porch = <8>; 37 vfront-porch = <33>; 38 hsync-len = <64>; 39 vsync-len = <4>; 40 hsync-active = <0>; 41 vsync-active = <0>; 42 de-active = <0>; 43 pixelclk-active = <0>; 44 }; 45 }; 46 47 port { 48 panel_in_lvds: endpoint { 49 remote-endpoint = <&lvds_out_panel>; 50 }; 51 }; 52 }; 53}; 54 55&rk628_lvds { 56 rockchip,link-type = "dual-link-even-odd-pixels"; 57 status = "okay"; 58 59 ports { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 port@0 { 64 reg = <0>; 65 66 lvds_in_post_process: endpoint { 67 remote-endpoint = <&post_process_out_lvds>; 68 }; 69 }; 70 71 port@1 { 72 reg = <1>; 73 74 lvds_out_panel: endpoint { 75 remote-endpoint = <&panel_in_lvds>; 76 }; 77 }; 78 }; 79}; 80 81&rk628_combtxphy { 82 status = "okay"; 83}; 84 85&rk628_post_process { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&rk628_vop_pins>; 88 status = "okay"; 89 90 ports { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 94 port@0 { 95 reg = <0>; 96 97 post_process_in_rgb: endpoint { 98 remote-endpoint = <&rgb_out_post_process>; 99 }; 100 }; 101 102 port@1 { 103 reg = <1>; 104 105 post_process_out_lvds: endpoint { 106 remote-endpoint = <&lvds_in_post_process>; 107 }; 108 }; 109 }; 110}; 111 112&rgb { 113 status = "okay"; 114 115 ports { 116 port@1 { 117 reg = <1>; 118 119 rgb_out_post_process: endpoint { 120 remote-endpoint = <&post_process_in_rgb>; 121 }; 122 }; 123 }; 124}; 125 126&video_phy { 127 status = "okay"; 128}; 129 130&rgb_in_vopb { 131 status = "disabled"; 132}; 133 134&rgb_in_vopl { 135 status = "okay"; 136}; 137 138&route_rgb { 139 connect = <&vopl_out_rgb>; 140 status = "disabled"; 141}; 142 143&vopb { 144 assigned-clocks = <&cru DCLK_VOP0>; 145 assigned-clock-parents = <&cru PLL_GPLL>; 146}; 147 148&vopl { 149 assigned-clocks = <&cru DCLK_VOP1>; 150 assigned-clock-parents = <&cru PLL_CPLL>; 151}; 152