1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include "rk3288-evb-android-rk808-edp.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Rockchip rk3288 evb avb board"; 12*4882a593Smuzhiyun compatible = "rockchip,rk3288-evb-android-rk808-edp", "rockchip,rk3288"; 13*4882a593Smuzhiyun chosen: chosen { 14*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0"; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&hevc { 19*4882a593Smuzhiyun status = "okay"; 20*4882a593Smuzhiyun clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac"; 21*4882a593Smuzhiyun rockchip,normal-rates = <300000000>, <0>, <200000000>, <200000000>; 22*4882a593Smuzhiyun rockchip,advanced-rates = <600000000>, <0>, <500000000>, <500000000>; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&io_domains { 26*4882a593Smuzhiyun status = "okay"; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun dvp-supply = <&vcc_18>; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun&isp_mmu { 32*4882a593Smuzhiyun status = "okay"; 33*4882a593Smuzhiyun}; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun&i2c3 { 36*4882a593Smuzhiyun status = "okay"; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun sgm3784: sgm3784@30 { 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <0>; 41*4882a593Smuzhiyun compatible = "sgmicro,gsm3784"; 42*4882a593Smuzhiyun reg = <0x30>; 43*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 44*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 45*4882a593Smuzhiyun enable-gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; 46*4882a593Smuzhiyun strobe-gpio = <&gpio7 RK_PB5 GPIO_ACTIVE_HIGH>; 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun sgm3784_led0: led@0 { 49*4882a593Smuzhiyun reg = <0x0>; 50*4882a593Smuzhiyun led-max-microamp = <299200>; 51*4882a593Smuzhiyun flash-max-microamp = <1122000>; 52*4882a593Smuzhiyun flash-max-timeout-us = <1600000>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun sgm3784_led1: led@1 { 56*4882a593Smuzhiyun reg = <0x1>; 57*4882a593Smuzhiyun led-max-microamp = <299200>; 58*4882a593Smuzhiyun flash-max-microamp = <1122000>; 59*4882a593Smuzhiyun flash-max-timeout-us = <1600000>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun vm149c: vm149c@0c { 64*4882a593Smuzhiyun compatible = "silicon touch,vm149c"; 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun reg = <0x0c>; 67*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 68*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun ov13850: ov13850@10 { 72*4882a593Smuzhiyun compatible = "ovti,ov13850"; 73*4882a593Smuzhiyun reg = <0x10>; 74*4882a593Smuzhiyun clocks = <&cru SCLK_VIP_OUT>; 75*4882a593Smuzhiyun clock-names = "xvclk"; 76*4882a593Smuzhiyun /* avdd-supply = <>; */ 77*4882a593Smuzhiyun /* dvdd-supply = <>; */ 78*4882a593Smuzhiyun /* dovdd-supply = <>; */ 79*4882a593Smuzhiyun /* reset-gpios = <>; */ 80*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 81*4882a593Smuzhiyun pinctrl-0 = <&isp_mipi>; 82*4882a593Smuzhiyun power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 83*4882a593Smuzhiyun pwdn-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 84*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 85*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 86*4882a593Smuzhiyun rockchip,camera-module-name = "CMK-CT0116"; 87*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan-50013A1"; 88*4882a593Smuzhiyun lens-focus = <&vm149c>; 89*4882a593Smuzhiyun flash-leds = <&sgm3784_led0 &sgm3784_led1>; 90*4882a593Smuzhiyun port { 91*4882a593Smuzhiyun ov13850_out: endpoint { 92*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 93*4882a593Smuzhiyun data-lanes = <1 2>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&mipi_phy_rx0 { 100*4882a593Smuzhiyun status = "okay"; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun ports { 103*4882a593Smuzhiyun #address-cells = <1>; 104*4882a593Smuzhiyun #size-cells = <0>; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun port@0 { 107*4882a593Smuzhiyun reg = <0>; 108*4882a593Smuzhiyun #address-cells = <1>; 109*4882a593Smuzhiyun #size-cells = <0>; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 112*4882a593Smuzhiyun reg = <1>; 113*4882a593Smuzhiyun remote-endpoint = <&ov13850_out>; 114*4882a593Smuzhiyun data-lanes = <1 2>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun port@1 { 119*4882a593Smuzhiyun reg = <1>; 120*4882a593Smuzhiyun #address-cells = <1>; 121*4882a593Smuzhiyun #size-cells = <0>; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun dphy_rx_out: endpoint@0 { 124*4882a593Smuzhiyun reg = <0>; 125*4882a593Smuzhiyun remote-endpoint = <&isp_mipi_in>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&rkisp1 { 132*4882a593Smuzhiyun status = "okay"; 133*4882a593Smuzhiyun port { 134*4882a593Smuzhiyun #address-cells = <1>; 135*4882a593Smuzhiyun #size-cells = <0>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun isp_mipi_in: endpoint@0 { 138*4882a593Smuzhiyun reg = <0>; 139*4882a593Smuzhiyun remote-endpoint = <&dphy_rx_out>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&route_hdmi { 146*4882a593Smuzhiyun status = "okay"; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&vopb { 150*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP0>; 151*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_GPLL>; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&vopl { 155*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP1>; 156*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_CPLL>; 157*4882a593Smuzhiyun}; 158