1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 3 4/dts-v1/; 5#include "rk3288-evb-rk628.dtsi" 6 7/ { 8 model = "Rockchip RK3288 EVB RK628 Board"; 9 compatible = "rockchip,rk3288-evb-rk628", "rockchip,rk3288"; 10 11 panel { 12 compatible = "simple-panel"; 13 backlight = <&backlight>; 14 enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; 15 prepare-delay-ms = <20>; 16 enable-delay-ms = <20>; 17 disable-delay-ms = <20>; 18 unprepare-delay-ms = <20>; 19 bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>; 20 21 display-timings { 22 native-mode = <&timing0>; 23 24 timing0: timing0 { 25 clock-frequency = <48000000>; 26 hactive = <1024>; 27 vactive = <600>; 28 hback-porch = <90>; 29 hfront-porch = <90>; 30 vback-porch = <10>; 31 vfront-porch = <10>; 32 hsync-len = <90>; 33 vsync-len = <10>; 34 hsync-active = <0>; 35 vsync-active = <0>; 36 de-active = <0>; 37 pixelclk-active = <0>; 38 }; 39 }; 40 41 port { 42 panel_in_lvds: endpoint { 43 remote-endpoint = <&lvds_out_panel>; 44 }; 45 }; 46 }; 47}; 48 49&rk628_lvds { 50 status = "okay"; 51 52 ports { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 port@0 { 57 reg = <0>; 58 59 lvds_in_post_process: endpoint { 60 remote-endpoint = <&post_process_out_lvds>; 61 }; 62 }; 63 64 port@1 { 65 reg = <1>; 66 67 lvds_out_panel: endpoint { 68 remote-endpoint = <&panel_in_lvds>; 69 }; 70 }; 71 }; 72}; 73 74&rk628_combtxphy { 75 status = "okay"; 76}; 77 78&rk628_post_process { 79 pinctrl-names = "default"; 80 pinctrl-0 = <&rk628_vop_pins>; 81 status = "okay"; 82 83 ports { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 port@0 { 88 reg = <0>; 89 90 post_process_in_rgb: endpoint { 91 remote-endpoint = <&rgb_out_post_process>; 92 }; 93 }; 94 95 port@1 { 96 reg = <1>; 97 98 post_process_out_lvds: endpoint { 99 remote-endpoint = <&lvds_in_post_process>; 100 }; 101 }; 102 }; 103}; 104 105&rgb { 106 status = "okay"; 107 108 ports { 109 port@1 { 110 reg = <1>; 111 112 rgb_out_post_process: endpoint { 113 remote-endpoint = <&post_process_in_rgb>; 114 }; 115 }; 116 }; 117}; 118 119&video_phy { 120 status = "okay"; 121}; 122 123&rgb_in_vopb { 124 status = "disabled"; 125}; 126 127&rgb_in_vopl { 128 status = "okay"; 129}; 130 131&route_rgb { 132 connect = <&vopl_out_rgb>; 133 status = "disabled"; 134}; 135 136&vopb { 137 assigned-clocks = <&cru DCLK_VOP0>; 138 assigned-clock-parents = <&cru PLL_GPLL>; 139}; 140 141&vopl { 142 assigned-clocks = <&cru DCLK_VOP1>; 143 assigned-clock-parents = <&cru PLL_CPLL>; 144}; 145