Searched refs:MMC_TIMING_MMC_DDR52 (Results 1 – 25 of 51) sorted by relevance
123
38 if (ios->timing == MMC_TIMING_MMC_DDR52 || in dw_mci_hi3798cv200_set_ios()46 if (ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_hi3798cv200_set_ios()
644 case MMC_TIMING_MMC_DDR52: in sdhci_zynqmp_sdcardclk_set_phase()712 case MMC_TIMING_MMC_DDR52: in sdhci_zynqmp_sampleclk_set_phase()771 case MMC_TIMING_MMC_DDR52: in sdhci_versal_sdcardclk_set_phase()837 case MMC_TIMING_MMC_DDR52: in sdhci_versal_sampleclk_set_phase()1100 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52, in arasan_dt_parse_clk_phases()
56 ios->timing == MMC_TIMING_MMC_DDR52) in dw_mci_rk3288_set_ios()114 case MMC_TIMING_MMC_DDR52: in dw_mci_rk3288_set_ios()
214 (timing == MMC_TIMING_MMC_DDR52)) in xenon_set_uhs_signaling()349 host->timing == MMC_TIMING_MMC_DDR52) in xenon_execute_tuning()
621 case MMC_TIMING_MMC_DDR52: in xenon_emmc_phy_set()749 case MMC_TIMING_MMC_DDR52: in xenon_hs_delay_adj()
96 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },332 case MMC_TIMING_MMC_DDR52: in sdhci_sprd_set_uhs_signaling()
130 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",616 if (i <= MMC_TIMING_MMC_DDR52) in sdhci_am654_get_otap_delay()
783 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()1047 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; in sdhci_omap_config_iodelay_pinctrl_state()1053 pinctrl_state[MMC_TIMING_MMC_DDR52] = state; in sdhci_omap_config_iodelay_pinctrl_state()
117 (timing == MMC_TIMING_MMC_DDR52)) in sdhci_brcmstb_set_uhs_signaling()
283 case MMC_TIMING_MMC_DDR52: in arasan_select_phy_clock()
737 ios->timing != MMC_TIMING_MMC_DDR52) { in sunxi_mmc_clk_set_phase()782 if (ios->timing == MMC_TIMING_MMC_DDR52 && in sunxi_mmc_clk_set_rate()887 ios->timing == MMC_TIMING_MMC_DDR52) in sunxi_mmc_set_clk()
288 case MMC_TIMING_MMC_DDR52: in sdhci_cdns_set_uhs_signaling()
105 if (timing == MMC_TIMING_MMC_DDR52) { in sdhci_at91_set_uhs_signaling()
292 case MMC_TIMING_MMC_DDR52: in sdhci_st_set_uhs_signaling()
199 if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 || in mmci_sdmmc_set_clkreg()
267 case MMC_TIMING_MMC_DDR52: in pxav3_set_uhs_signaling()
309 case MMC_TIMING_MMC_DDR52: in dw_mci_exynos_set_ios()
553 case MMC_TIMING_MMC_DDR52: in meson_mmc_prepare_ios_clock()573 case MMC_TIMING_MMC_DDR52: in meson_mmc_check_resampling()
1005 case MMC_TIMING_MMC_DDR52: in sd_set_timing()1086 case MMC_TIMING_MMC_DDR52: in sdmmc_set_ios()
200 (timing == MMC_TIMING_MMC_DDR52)) in dwcmshc_set_uhs_signaling()
67 return card->host->ios.timing == MMC_TIMING_MMC_DDR52; in mmc_card_ddr52()
143 case MMC_TIMING_MMC_DDR52: in mmc_ios_show()
560 #define MMC_TIMING_MMC_DDR52 8 macro641 (mmc->timing == MMC_TIMING_MMC_DDR52) || in mmc_card_ddr()653 return mmc->timing == MMC_TIMING_MMC_DDR52; in mmc_card_ddr52()
225 (priv->timing == MMC_TIMING_MMC_DDR52)) { in xenon_mmc_phy_set()347 priv->timing = MMC_TIMING_MMC_DDR52; in xenon_sdhci_set_ios_post()
64 #define MMC_TIMING_MMC_DDR52 8 macro