1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
4 *
5 * Copyright (C) 2018 Synaptics Incorporated
6 *
7 * Author: Jisheng Zhang <jszhang@kernel.org>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/sizes.h>
21
22 #include "sdhci-pltfm.h"
23 #include "mmc_hsq.h"
24
25 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
26
27 /* DWCMSHC specific Mode Select value */
28 #define DWCMSHC_CTRL_HS400 0x7
29
30 /* DWC IP vendor area 1 pointer */
31 #define DWCMSHC_P_VENDOR_AREA1 0xe8
32 #define DWCMSHC_AREA1_MASK GENMASK(11, 0)
33 /* Offset inside the vendor area 1 */
34 #define DWCMSHC_HOST_CTRL3 0x8
35 #define DWCMSHC_EMMC_CONTROL 0x2c
36 #define DWCMSHC_CARD_IS_EMMC BIT(0)
37 #define DWCMSHC_ENHANCED_STROBE BIT(8)
38 #define DWCMSHC_EMMC_ATCTRL 0x40
39
40 /* Rockchip specific Registers */
41 #define DWCMSHC_EMMC_DLL_CTRL 0x800
42 #define DWCMSHC_EMMC_DLL_RXCLK 0x804
43 #define DWCMSHC_EMMC_DLL_TXCLK 0x808
44 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c
45 #define DECMSHC_EMMC_DLL_CMDOUT 0x810
46 #define DWCMSHC_EMMC_DLL_STATUS0 0x840
47 #define DWCMSHC_EMMC_DLL_STATUS1 0x844
48 #define DWCMSHC_EMMC_DLL_START BIT(0)
49 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
50 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
51 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
52 #define DWCMSHC_EMMC_DLL_START_POINT 16
53 #define DWCMSHC_EMMC_DLL_INC 8
54 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
55 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
56 #define DLL_TAP_VALUE_SEL BIT(25)
57 #define DLL_TAP_VALUE_OFFSET 8
58 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
59 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
60 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
61 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8
62 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
63 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
64 #define DLL_STRBIN_DELAY_NUM_OFFSET 16
65 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
66 #define DLL_RXCLK_NO_INVERTER 1
67 #define DLL_RXCLK_INVERTER 0
68 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
69 #define DLL_RXCLK_TAPNUM_FROM_SW BIT(24)
70 #define DLL_RXCLK_ORI_GATE BIT(31)
71 #define DLL_RXCLK_MAX_TAP 32
72 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
73 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
74 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
75 #define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30)
76
77 #define DLL_LOCK_WO_TMOUT(x) \
78 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
79 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
80 #define RK35xx_MAX_CLKS 3
81
82 #define BOUNDARY_OK(addr, len) \
83 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
84
85 enum dwcmshc_rk_type {
86 DWCMSHC_RK3568,
87 DWCMSHC_RK3588,
88 };
89
90 struct dwcmshc_driver_data {
91 const struct sdhci_pltfm_data *pdata;
92 u32 flags;
93 #define RK_PLATFROM BIT(0)
94 #define RK_DLL_CMD_OUT BIT(1)
95 #define RK_RXCLK_NO_INVERTER BIT(2)
96 #define RK_TAP_VALUE_SEL BIT(3)
97
98 u8 hs200_tx_tap;
99 u8 hs400_tx_tap;
100 u8 hs400_cmd_tap;
101 u8 ddr50_strbin_delay_num;
102 u8 hs400_strbin_tap;
103 };
104
105 struct rk35xx_priv {
106 /* Rockchip specified optional clocks */
107 struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS];
108 struct reset_control *reset;
109 enum dwcmshc_rk_type devtype;
110 u8 txclk_tapnum;
111 u32 cclk_rate;
112 unsigned int actual_clk;
113 const struct dwcmshc_driver_data *drv_data;
114 u32 acpi_en;
115 };
116
117 struct dwcmshc_priv {
118 struct clk *bus_clk;
119 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
120 void *priv; /* pointer to SoC private stuff */
121 };
122
123 /*
124 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
125 * so that each DMA transfer doesn't exceed the boundary.
126 */
dwcmshc_adma_write_desc(struct sdhci_host * host,void ** desc,dma_addr_t addr,int len,unsigned int cmd)127 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
128 dma_addr_t addr, int len, unsigned int cmd)
129 {
130 int tmplen, offset;
131
132 if (likely(!len || BOUNDARY_OK(addr, len))) {
133 sdhci_adma_write_desc(host, desc, addr, len, cmd);
134 return;
135 }
136
137 offset = addr & (SZ_128M - 1);
138 tmplen = SZ_128M - offset;
139 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
140
141 addr += tmplen;
142 len -= tmplen;
143 sdhci_adma_write_desc(host, desc, addr, len, cmd);
144 }
145
dwcmshc_get_max_clock(struct sdhci_host * host)146 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
147 {
148 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
149
150 if (pltfm_host->clk)
151 return sdhci_pltfm_clk_get_max_clock(host);
152 else
153 return pltfm_host->clock;
154 }
155
dwcmshc_check_auto_cmd23(struct mmc_host * mmc,struct mmc_request * mrq)156 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
157 struct mmc_request *mrq)
158 {
159 struct sdhci_host *host = mmc_priv(mmc);
160
161 /*
162 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
163 * block count register which doesn't support stuff bits of
164 * CMD23 argument on dwcmsch host controller.
165 */
166 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
167 host->flags &= ~SDHCI_AUTO_CMD23;
168 else
169 host->flags |= SDHCI_AUTO_CMD23;
170 }
171
dwcmshc_request(struct mmc_host * mmc,struct mmc_request * mrq)172 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
173 {
174 dwcmshc_check_auto_cmd23(mmc, mrq);
175
176 sdhci_request(mmc, mrq);
177 }
178
dwcmshc_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)179 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
180 unsigned int timing)
181 {
182 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
183 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
184 u16 ctrl, ctrl_2;
185
186 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
187 /* Select Bus Speed Mode for host */
188 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
189 if ((timing == MMC_TIMING_MMC_HS200) ||
190 (timing == MMC_TIMING_UHS_SDR104))
191 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
192 else if (timing == MMC_TIMING_UHS_SDR12)
193 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
194 else if ((timing == MMC_TIMING_UHS_SDR25) ||
195 (timing == MMC_TIMING_MMC_HS))
196 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
197 else if (timing == MMC_TIMING_UHS_SDR50)
198 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
199 else if ((timing == MMC_TIMING_UHS_DDR50) ||
200 (timing == MMC_TIMING_MMC_DDR52))
201 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
202 else if (timing == MMC_TIMING_MMC_HS400) {
203 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
204 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
205 ctrl |= DWCMSHC_CARD_IS_EMMC;
206 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
207
208 ctrl_2 |= DWCMSHC_CTRL_HS400;
209 }
210
211 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
212 }
213
dwcmshc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)214 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
215 struct mmc_ios *ios)
216 {
217 u32 vendor;
218 struct sdhci_host *host = mmc_priv(mmc);
219 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
220 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
221 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
222
223 vendor = sdhci_readl(host, reg);
224 if (ios->enhanced_strobe)
225 vendor |= DWCMSHC_ENHANCED_STROBE;
226 else
227 vendor &= ~DWCMSHC_ENHANCED_STROBE;
228
229 sdhci_writel(host, vendor, reg);
230 }
231
dwcmshc_rk3568_set_clock(struct sdhci_host * host,unsigned int clock)232 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
233 {
234 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
235 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
236 struct rk35xx_priv *priv = dwc_priv->priv;
237 const struct dwcmshc_driver_data *drv_data = priv->drv_data;
238 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
239 u32 extra, reg, dll_lock_value;
240 int err;
241
242 host->mmc->actual_clock = 0;
243
244 if (clock == 0) {
245 /* Disable interface clock at initial state. */
246 sdhci_set_clock(host, clock);
247 return;
248 }
249
250 /* Rockchip platform only support 375KHz for identify mode */
251 if (clock <= 400000)
252 clock = 375000;
253
254 if (priv->acpi_en) {
255 union acpi_object params[1];
256 struct acpi_object_list param_objects;
257
258 params[0].type = ACPI_TYPE_INTEGER;
259 params[0].integer.value = clock;
260 param_objects.count = 1;
261 param_objects.pointer = params;
262 acpi_evaluate_object(ACPI_HANDLE(mmc_dev(host->mmc)), "SCLK", ¶m_objects, NULL);
263 } else {
264 err = clk_set_rate(pltfm_host->clk, clock);
265 if (err)
266 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
267 }
268
269 sdhci_set_clock(host, clock);
270
271 /* Disable cmd conflict check */
272 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
273 extra = sdhci_readl(host, reg);
274 extra &= ~BIT(0);
275 sdhci_writel(host, extra, reg);
276
277 /* Disable output clock while config DLL */
278 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
279
280 if (clock <= 52000000) {
281 /* Disable DLL */
282 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
283 /*
284 * Config DLL BYPASS and Reset both of sample and drive clock.
285 * The bypass bit and start bit need to set if DLL is not locked.
286 */
287 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
288 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
289 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
290 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
291 /*
292 * Before switching to hs400es mode, the driver will enable
293 * enhanced strobe first. PHY needs to configure the parameters
294 * of enhanced strobe first.
295 */
296 extra = DWCMSHC_EMMC_DLL_DLYENA |
297 DLL_STRBIN_DELAY_NUM_SEL |
298 drv_data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET;
299 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
300 goto exit;
301 }
302
303 /* Reset DLL */
304 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
305 udelay(1);
306 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
307
308 /* Init DLL settings, clean start bit before resetting */
309 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
310 /* Init DLL settings */
311 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
312 0x2 << DWCMSHC_EMMC_DLL_INC |
313 DWCMSHC_EMMC_DLL_START;
314 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
315 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
316 extra, DLL_LOCK_WO_TMOUT(extra), 1,
317 500 * USEC_PER_MSEC);
318 if (err) {
319 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
320 goto exit;
321 }
322
323 dll_lock_value = ((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0) & 0xFF) * 2) & 0xFF;
324
325 extra = 0x1 << 16 | /* tune clock stop en */
326 0x3 << 17 | /* pre-change delay */
327 0x3 << 19; /* post-change delay */
328 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
329
330 extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
331 if (drv_data->flags & RK_RXCLK_NO_INVERTER)
332 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
333 if (drv_data->flags & RK_TAP_VALUE_SEL)
334 extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET;
335 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
336
337 txclk_tapnum = drv_data->hs200_tx_tap;
338 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
339 txclk_tapnum = drv_data->hs400_tx_tap;
340
341 if (drv_data->flags & RK_DLL_CMD_OUT) {
342 extra = DLL_CMDOUT_SRC_CLK_NEG |
343 DLL_CMDOUT_BOTH_CLK_EDGE |
344 DWCMSHC_EMMC_DLL_DLYENA |
345 drv_data->hs400_cmd_tap |
346 DLL_CMDOUT_TAPNUM_FROM_SW;
347 if (drv_data->flags & RK_TAP_VALUE_SEL)
348 extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET;
349 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
350 }
351 }
352 extra = DWCMSHC_EMMC_DLL_DLYENA |
353 DLL_TXCLK_TAPNUM_FROM_SW |
354 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
355 txclk_tapnum;
356 if (drv_data->flags & RK_TAP_VALUE_SEL)
357 extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET;
358 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
359
360 extra = DWCMSHC_EMMC_DLL_DLYENA |
361 drv_data->hs400_strbin_tap |
362 DLL_STRBIN_TAPNUM_FROM_SW;
363 if (drv_data->flags & RK_TAP_VALUE_SEL)
364 extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET;
365 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
366
367 exit:
368 /* enable output clock */
369 sdhci_enable_clk(host, 0);
370 }
371
rk35xx_sdhci_reset(struct sdhci_host * host,u8 mask)372 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
373 {
374 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
375 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
376 struct rk35xx_priv *priv = dwc_priv->priv;
377
378 if (mask & SDHCI_RESET_ALL && priv->reset) {
379 reset_control_assert(priv->reset);
380 udelay(1);
381 reset_control_deassert(priv->reset);
382 }
383
384 sdhci_reset(host, mask);
385 }
386
sdhci_dwcmshc_request_done(struct sdhci_host * host,struct mmc_request * mrq)387 static void sdhci_dwcmshc_request_done(struct sdhci_host *host, struct mmc_request *mrq)
388 {
389 if (mmc_hsq_finalize_request(host->mmc, mrq))
390 return;
391
392 mmc_request_done(host->mmc, mrq);
393 }
394
395 static const struct sdhci_ops sdhci_dwcmshc_ops = {
396 .set_clock = sdhci_set_clock,
397 .set_bus_width = sdhci_set_bus_width,
398 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
399 .get_max_clock = dwcmshc_get_max_clock,
400 .reset = sdhci_reset,
401 .adma_write_desc = dwcmshc_adma_write_desc,
402 };
403
404 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
405 .set_clock = dwcmshc_rk3568_set_clock,
406 .set_bus_width = sdhci_set_bus_width,
407 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
408 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
409 .reset = rk35xx_sdhci_reset,
410 .adma_write_desc = dwcmshc_adma_write_desc,
411 .request_done = sdhci_dwcmshc_request_done,
412 };
413
414 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
415 .ops = &sdhci_dwcmshc_ops,
416 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
417 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
418 };
419
420 #ifdef CONFIG_ACPI
421 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
422 .ops = &sdhci_dwcmshc_ops,
423 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
424 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
425 SDHCI_QUIRK2_ACMD23_BROKEN,
426 };
427 #endif
428
429 static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
430 .ops = &sdhci_dwcmshc_rk35xx_ops,
431 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
432 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
433 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
434 };
435
dwcmshc_rk35xx_init(struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)436 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
437 {
438 int err;
439 struct rk35xx_priv *priv = dwc_priv->priv;
440
441 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
442 if (IS_ERR(priv->reset)) {
443 err = PTR_ERR(priv->reset);
444 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
445 return err;
446 }
447
448 priv->rockchip_clks[0].id = "axi";
449 priv->rockchip_clks[1].id = "block";
450 priv->rockchip_clks[2].id = "timer";
451 err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
452 priv->rockchip_clks);
453 if (err) {
454 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
455 return err;
456 }
457
458 err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks);
459 if (err) {
460 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
461 return err;
462 }
463
464 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
465 &priv->txclk_tapnum))
466 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
467
468 /* Disable cmd conflict check */
469 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
470 /* Reset previous settings */
471 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
472 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
473
474 return 0;
475 }
476
dwcmshc_rk35xx_postinit(struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)477 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
478 {
479 /*
480 * Don't support highspeed bus mode with low clk speed as we
481 * cannot use DLL for this condition.
482 */
483 if (host->mmc->f_max <= 52000000) {
484 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
485 host->mmc->f_max);
486 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
487 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
488 }
489 }
490
491 static const struct dwcmshc_driver_data dwcmshc_drvdata = {
492 .pdata = &sdhci_dwcmshc_pdata,
493 .flags = 0,
494 };
495
496 static const struct dwcmshc_driver_data rk3568_drvdata = {
497 .pdata = &sdhci_dwcmshc_rk35xx_pdata,
498 .flags = RK_PLATFROM | RK_RXCLK_NO_INVERTER,
499 .hs200_tx_tap = 16,
500 .hs400_tx_tap = 8,
501 .hs400_cmd_tap = 8,
502 .hs400_strbin_tap = 4,
503 .ddr50_strbin_delay_num = 16,
504 };
505
506 static const struct dwcmshc_driver_data rk3588_drvdata = {
507 .pdata = &sdhci_dwcmshc_rk35xx_pdata,
508 .flags = RK_PLATFROM | RK_DLL_CMD_OUT,
509 .hs200_tx_tap = 16,
510 .hs400_tx_tap = 9,
511 .hs400_cmd_tap = 8,
512 .hs400_strbin_tap = 4,
513 .ddr50_strbin_delay_num = 16,
514 };
515
516 static const struct dwcmshc_driver_data rk3528_drvdata = {
517 .pdata = &sdhci_dwcmshc_rk35xx_pdata,
518 .flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL,
519 .hs200_tx_tap = 12,
520 .hs400_tx_tap = 6,
521 .hs400_cmd_tap = 6,
522 .hs400_strbin_tap = 3,
523 .ddr50_strbin_delay_num = 10,
524 };
525
526 static const struct dwcmshc_driver_data rk3562_drvdata = {
527 .pdata = &sdhci_dwcmshc_rk35xx_pdata,
528 .flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL,
529 .hs200_tx_tap = 12,
530 .hs400_tx_tap = 6,
531 .hs400_cmd_tap = 6,
532 .hs400_strbin_tap = 3,
533 .ddr50_strbin_delay_num = 10,
534 };
535
536 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
537 {
538 .compatible = "rockchip,rk3588-dwcmshc",
539 .data = &rk3588_drvdata,
540 },
541 {
542 .compatible = "rockchip,rk3568-dwcmshc",
543 .data = &rk3568_drvdata,
544 },
545 {
546 .compatible = "rockchip,rk3528-dwcmshc",
547 .data = &rk3528_drvdata,
548 },
549 {
550 .compatible = "rockchip,rk3562-dwcmshc",
551 .data = &rk3562_drvdata,
552 },
553 {
554 .compatible = "snps,dwcmshc-sdhci",
555 .data = &dwcmshc_drvdata,
556 },
557 {},
558 };
559 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
560
561 #ifdef CONFIG_ACPI
562 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
563 {
564 .id = "MLNXBF30",
565 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
566 },
567 {}
568 };
569 #endif
570
dwcmshc_probe(struct platform_device * pdev)571 static int dwcmshc_probe(struct platform_device *pdev)
572 {
573 struct device *dev = &pdev->dev;
574 struct sdhci_pltfm_host *pltfm_host;
575 struct sdhci_host *host;
576 struct dwcmshc_priv *priv;
577 struct rk35xx_priv *rk_priv = NULL;
578 const struct sdhci_pltfm_data *pltfm_data;
579 const struct dwcmshc_driver_data *drv_data;
580 struct mmc_hsq *hsq;
581 int err;
582 u32 extra;
583
584 drv_data = device_get_match_data(&pdev->dev);
585 if (!drv_data) {
586 dev_err(&pdev->dev, "Error: No device match data found\n");
587 return -ENODEV;
588 }
589 pltfm_data = drv_data->pdata;
590
591 host = sdhci_pltfm_init(pdev, pltfm_data,
592 sizeof(struct dwcmshc_priv));
593 if (IS_ERR(host))
594 return PTR_ERR(host);
595
596 /*
597 * extra adma table cnt for cross 128M boundary handling.
598 */
599 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
600 if (extra > SDHCI_MAX_SEGS)
601 extra = SDHCI_MAX_SEGS;
602 host->adma_table_cnt += extra;
603
604 pltfm_host = sdhci_priv(host);
605 priv = sdhci_pltfm_priv(pltfm_host);
606
607 if (dev->of_node) {
608 pltfm_host->clk = devm_clk_get(dev, "core");
609 if (IS_ERR(pltfm_host->clk)) {
610 err = PTR_ERR(pltfm_host->clk);
611 dev_err(dev, "failed to get core clk: %d\n", err);
612 goto free_pltfm;
613 }
614 err = clk_prepare_enable(pltfm_host->clk);
615 if (err)
616 goto free_pltfm;
617
618 priv->bus_clk = devm_clk_get(dev, "bus");
619 if (!IS_ERR(priv->bus_clk))
620 clk_prepare_enable(priv->bus_clk);
621 }
622
623 err = mmc_of_parse(host->mmc);
624 if (err)
625 goto err_clk;
626
627 sdhci_get_of_property(pdev);
628
629 priv->vendor_specific_area1 =
630 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
631
632 host->mmc_host_ops.request = dwcmshc_request;
633 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
634
635 hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
636 if (!hsq) {
637 err = -ENOMEM;
638 goto err_clk;
639 }
640
641 err = mmc_hsq_init(hsq, host->mmc);
642 if (err)
643 goto err_clk;
644
645 if (drv_data->flags & RK_PLATFROM) {
646 rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
647 if (!rk_priv) {
648 err = -ENOMEM;
649 goto err_clk;
650 }
651
652 rk_priv->drv_data = drv_data;
653 rk_priv->acpi_en = has_acpi_companion(&pdev->dev);
654
655 if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
656 rk_priv->devtype = DWCMSHC_RK3588;
657 else
658 rk_priv->devtype = DWCMSHC_RK3568;
659
660 priv->priv = rk_priv;
661
662 err = dwcmshc_rk35xx_init(host, priv);
663 if (err)
664 goto err_clk;
665 }
666
667 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
668
669 err = sdhci_setup_host(host);
670 if (err)
671 goto err_clk;
672
673 if (rk_priv)
674 dwcmshc_rk35xx_postinit(host, priv);
675
676 err = __sdhci_add_host(host);
677 if (err)
678 goto err_setup_host;
679
680 if (rk_priv && !rk_priv->acpi_en) {
681 pm_runtime_get_noresume(&pdev->dev);
682 pm_runtime_set_active(&pdev->dev);
683 pm_runtime_enable(&pdev->dev);
684 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
685 pm_runtime_use_autosuspend(&pdev->dev);
686 pm_runtime_put_autosuspend(&pdev->dev);
687 }
688
689 return 0;
690
691 err_setup_host:
692 sdhci_cleanup_host(host);
693 err_clk:
694 clk_disable_unprepare(pltfm_host->clk);
695 clk_disable_unprepare(priv->bus_clk);
696 if (rk_priv)
697 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
698 rk_priv->rockchip_clks);
699 free_pltfm:
700 sdhci_pltfm_free(pdev);
701 return err;
702 }
703
dwcmshc_remove(struct platform_device * pdev)704 static int dwcmshc_remove(struct platform_device *pdev)
705 {
706 struct sdhci_host *host = platform_get_drvdata(pdev);
707 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
708 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
709 struct rk35xx_priv *rk_priv = priv->priv;
710
711 sdhci_remove_host(host, 0);
712
713 clk_disable_unprepare(pltfm_host->clk);
714 clk_disable_unprepare(priv->bus_clk);
715 if (rk_priv)
716 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
717 rk_priv->rockchip_clks);
718 sdhci_pltfm_free(pdev);
719
720 return 0;
721 }
722
723 #ifdef CONFIG_PM_SLEEP
dwcmshc_suspend(struct device * dev)724 static int dwcmshc_suspend(struct device *dev)
725 {
726 struct sdhci_host *host = dev_get_drvdata(dev);
727 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
728 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
729 struct rk35xx_priv *rk_priv = priv->priv;
730 int ret;
731
732 mmc_hsq_suspend(host->mmc);
733
734 ret = sdhci_suspend_host(host);
735 if (ret)
736 return ret;
737
738 clk_disable_unprepare(pltfm_host->clk);
739 if (!IS_ERR(priv->bus_clk))
740 clk_disable_unprepare(priv->bus_clk);
741
742 if (rk_priv)
743 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
744 rk_priv->rockchip_clks);
745
746 return ret;
747 }
748
dwcmshc_resume(struct device * dev)749 static int dwcmshc_resume(struct device *dev)
750 {
751 struct sdhci_host *host = dev_get_drvdata(dev);
752 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
753 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
754 struct rk35xx_priv *rk_priv = priv->priv;
755 int ret;
756
757 ret = clk_prepare_enable(pltfm_host->clk);
758 if (ret)
759 return ret;
760
761 if (!IS_ERR(priv->bus_clk)) {
762 ret = clk_prepare_enable(priv->bus_clk);
763 if (ret)
764 return ret;
765 }
766
767 if (rk_priv) {
768 ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS,
769 rk_priv->rockchip_clks);
770 if (ret)
771 return ret;
772 }
773
774 ret = sdhci_resume_host(host);
775 if (ret)
776 return ret;
777
778 return mmc_hsq_resume(host->mmc);
779 }
780
dwcmshc_runtime_suspend(struct device * dev)781 static int dwcmshc_runtime_suspend(struct device *dev)
782 {
783 struct sdhci_host *host = dev_get_drvdata(dev);
784 u16 data;
785
786 data = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
787 data &= ~SDHCI_CLOCK_CARD_EN;
788 sdhci_writew(host, data, SDHCI_CLOCK_CONTROL);
789
790 return 0;
791 }
792
dwcmshc_runtime_resume(struct device * dev)793 static int dwcmshc_runtime_resume(struct device *dev)
794 {
795 struct sdhci_host *host = dev_get_drvdata(dev);
796 u16 data;
797
798 data = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
799 data |= SDHCI_CLOCK_CARD_EN;
800 sdhci_writew(host, data, SDHCI_CLOCK_CONTROL);
801
802 return 0;
803 }
804 #endif
805
806 static const struct dev_pm_ops dwcmshc_pmops = {
807 SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume)
808 SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend, dwcmshc_runtime_resume, NULL)
809 };
810
811 static struct platform_driver sdhci_dwcmshc_driver = {
812 .driver = {
813 .name = "sdhci-dwcmshc",
814 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
815 .of_match_table = sdhci_dwcmshc_dt_ids,
816 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
817 .pm = &dwcmshc_pmops,
818 },
819 .probe = dwcmshc_probe,
820 .remove = dwcmshc_remove,
821 };
822 module_platform_driver(sdhci_dwcmshc_driver);
823
824 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
825 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
826 MODULE_LICENSE("GPL v2");
827