1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
8 #include <linux/clk.h>
9 #include <linux/mmc/host.h>
10 #include <linux/of_address.h>
11 #include <linux/mmc/slot-gpio.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/rockchip/cpu.h>
14 #include <linux/slab.h>
15
16 #include "dw_mmc.h"
17 #include "dw_mmc-pltfm.h"
18
19 #define RK3288_CLKGEN_DIV 2
20
21 struct dw_mci_rockchip_priv_data {
22 struct clk *drv_clk;
23 struct clk *sample_clk;
24 int default_sample_phase;
25 int num_phases;
26 bool use_v2_tuning;
27 int last_degree;
28 u32 f_min;
29 };
30
dw_mci_rk3288_set_ios(struct dw_mci * host,struct mmc_ios * ios)31 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
32 {
33 struct dw_mci_rockchip_priv_data *priv = host->priv;
34 int ret;
35 unsigned int cclkin;
36 u32 bus_hz;
37
38 if (ios->clock == 0)
39 return;
40
41 /*
42 * cclkin: source clock of mmc controller
43 * bus_hz: card interface clock generated by CLKGEN
44 * bus_hz = cclkin / RK3288_CLKGEN_DIV
45 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
46 *
47 * Note: div can only be 0 or 1, but div must be set to 1 for eMMC
48 * DDR52 8-bit mode.
49 */
50 if (ios->clock < priv->f_min) {
51 ios->clock = priv->f_min;
52 host->slot->clock = ios->clock;
53 }
54
55 if (ios->bus_width == MMC_BUS_WIDTH_8 &&
56 ios->timing == MMC_TIMING_MMC_DDR52)
57 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
58 else
59 cclkin = ios->clock * RK3288_CLKGEN_DIV;
60
61 ret = clk_set_rate(host->ciu_clk, cclkin);
62 if (ret)
63 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
64
65 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
66 if (bus_hz != host->bus_hz) {
67 host->bus_hz = bus_hz;
68 /* force dw_mci_setup_bus() */
69 host->current_speed = 0;
70 }
71
72 /* Make sure we use phases which we can enumerate with */
73 if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS)
74 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
75
76 /*
77 * Set the drive phase offset based on speed mode to achieve hold times.
78 *
79 * NOTE: this is _not_ a value that is dynamically tuned and is also
80 * _not_ a value that will vary from board to board. It is a value
81 * that could vary between different SoC models if they had massively
82 * different output clock delays inside their dw_mmc IP block (delay_o),
83 * but since it's OK to overshoot a little we don't need to do complex
84 * calculations and can pick values that will just work for everyone.
85 *
86 * When picking values we'll stick with picking 0/90/180/270 since
87 * those can be made very accurately on all known Rockchip SoCs.
88 *
89 * Note that these values match values from the DesignWare Databook
90 * tables for the most part except for SDR12 and "ID mode". For those
91 * two modes the databook calculations assume a clock in of 50MHz. As
92 * seen above, we always use a clock in rate that is exactly the
93 * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
94 * back out before the controller sees it).
95 *
96 * From measurement of a single device, it appears that delay_o is
97 * about .5 ns. Since we try to leave a bit of margin, it's expected
98 * that numbers here will be fine even with much larger delay_o
99 * (the 1.4 ns assumed by the DesignWare Databook would result in the
100 * same results, for instance).
101 */
102 if (!IS_ERR(priv->drv_clk)) {
103 int phase;
104
105 /*
106 * In almost all cases a 90 degree phase offset will provide
107 * sufficient hold times across all valid input clock rates
108 * assuming delay_o is not absurd for a given SoC. We'll use
109 * that as a default.
110 */
111 phase = 90;
112
113 switch (ios->timing) {
114 case MMC_TIMING_MMC_DDR52:
115 /*
116 * Since clock in rate with MMC_DDR52 is doubled when
117 * bus width is 8 we need to double the phase offset
118 * to get the same timings.
119 */
120 if (ios->bus_width == MMC_BUS_WIDTH_8)
121 phase = 180;
122 break;
123 case MMC_TIMING_UHS_SDR104:
124 case MMC_TIMING_MMC_HS200:
125 /*
126 * In the case of 150 MHz clock (typical max for
127 * Rockchip SoCs), 90 degree offset will add a delay
128 * of 1.67 ns. That will meet min hold time of .8 ns
129 * as long as clock output delay is < .87 ns. On
130 * SoCs measured this seems to be OK, but it doesn't
131 * hurt to give margin here, so we use 180.
132 */
133 phase = 180;
134 break;
135 }
136
137 clk_set_phase(priv->drv_clk, phase);
138 }
139 }
140
141 #define TUNING_ITERATION_TO_PHASE(i, num_phases) \
142 (DIV_ROUND_UP((i) * 360, num_phases))
143
dw_mci_v2_execute_tuning(struct dw_mci_slot * slot,u32 opcode)144 static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
145 {
146 struct dw_mci *host = slot->host;
147 struct dw_mci_rockchip_priv_data *priv = host->priv;
148 struct mmc_host *mmc = slot->mmc;
149 u32 degrees[4] = {0, 90, 180, 270}, degree;
150 int i;
151 static bool inherit = true;
152
153 if (inherit) {
154 inherit = false;
155 i = clk_get_phase(priv->sample_clk) / 90;
156 degree = degrees[i];
157 goto done;
158 }
159
160 /*
161 * v2 only support 4 degrees in theory.
162 * First we inherit sample phases from firmware, which should
163 * be able work fine, at least in the first place.
164 * If retune is needed, we search forward to pick the last
165 * one phase from degree list and loop around until we get one.
166 * It's impossible all 4 fixed phase won't be able to work.
167 */
168 for (i = 0; i < ARRAY_SIZE(degrees); i++) {
169 degree = degrees[i] + priv->last_degree + 90;
170 degree = degree % 360;
171 clk_set_phase(priv->sample_clk, degree);
172
173 if (mmc_send_tuning(mmc, opcode, NULL)) {
174 /*
175 * Tuning error, the phase is a bad phase,
176 * then try using the calculated best phase.
177 */
178 dev_info(host->dev, "V2 tuned phase to %d error, try the best phase\n", degree);
179 degree = (degree + 180) % 360;
180 clk_set_phase(priv->sample_clk, degree);
181 if (!mmc_send_tuning(mmc, opcode, NULL))
182 break;
183 }
184
185 }
186
187 if (i == ARRAY_SIZE(degrees)) {
188 dev_warn(host->dev, "All phases bad!");
189 return -EIO;
190 }
191
192 done:
193 dev_info(host->dev, "Successfully tuned phase to %d\n", degree);
194 priv->last_degree = degree;
195 return 0;
196 }
197
dw_mci_rk3288_execute_tuning(struct dw_mci_slot * slot,u32 opcode)198 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
199 {
200 struct dw_mci *host = slot->host;
201 struct dw_mci_rockchip_priv_data *priv = host->priv;
202 struct mmc_host *mmc = slot->mmc;
203 int ret = 0;
204 int i;
205 bool v, prev_v = 0, first_v;
206 struct range_t {
207 int start;
208 int end; /* inclusive */
209 };
210 struct range_t *ranges;
211 unsigned int range_count = 0;
212 int longest_range_len = -1;
213 int longest_range = -1;
214 int middle_phase, real_middle_phase;
215
216 if (IS_ERR(priv->sample_clk)) {
217 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
218 return -EIO;
219 }
220
221 if (priv->use_v2_tuning) {
222 ret = dw_mci_v2_execute_tuning(slot, opcode);
223 if (!ret)
224 return 0;
225 /* Otherwise we continue using fine tuning */
226 }
227
228 ranges = kmalloc_array(priv->num_phases / 2 + 1,
229 sizeof(*ranges), GFP_KERNEL);
230 if (!ranges)
231 return -ENOMEM;
232
233 /* Try each phase and extract good ranges */
234 for (i = 0; i < priv->num_phases; ) {
235 /* Cannot guarantee any phases larger than 270 would work well */
236 if (TUNING_ITERATION_TO_PHASE(i, priv->num_phases) > 270)
237 break;
238 clk_set_phase(priv->sample_clk,
239 TUNING_ITERATION_TO_PHASE(i, priv->num_phases));
240
241 v = !mmc_send_tuning(mmc, opcode, NULL);
242
243 if (i == 0)
244 first_v = v;
245
246 if ((!prev_v) && v) {
247 range_count++;
248 ranges[range_count-1].start = i;
249 }
250 if (v) {
251 ranges[range_count-1].end = i;
252 i++;
253 } else if (i == priv->num_phases - 1) {
254 /* No extra skipping rules if we're at the end */
255 i++;
256 } else {
257 /*
258 * No need to check too close to an invalid
259 * one since testing bad phases is slow. Skip
260 * 20 degrees.
261 */
262 i += DIV_ROUND_UP(20 * priv->num_phases, 360);
263
264 /* Always test the last one */
265 if (i >= priv->num_phases)
266 i = priv->num_phases - 1;
267 }
268
269 prev_v = v;
270 }
271
272 if (range_count == 0) {
273 dev_warn(host->dev, "All phases bad!");
274 ret = -EIO;
275 goto free;
276 }
277
278 /* wrap around case, merge the end points */
279 if ((range_count > 1) && first_v && v) {
280 ranges[0].start = ranges[range_count-1].start;
281 range_count--;
282 }
283
284 if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
285 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
286 dev_info(host->dev, "All phases work, using default phase %d.",
287 priv->default_sample_phase);
288 goto free;
289 }
290
291 /* Find the longest range */
292 for (i = 0; i < range_count; i++) {
293 int len = (ranges[i].end - ranges[i].start + 1);
294
295 if (len < 0)
296 len += priv->num_phases;
297
298 if (longest_range_len < len) {
299 longest_range_len = len;
300 longest_range = i;
301 }
302
303 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
304 TUNING_ITERATION_TO_PHASE(ranges[i].start,
305 priv->num_phases),
306 TUNING_ITERATION_TO_PHASE(ranges[i].end,
307 priv->num_phases),
308 len
309 );
310 }
311
312 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
313 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start,
314 priv->num_phases),
315 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end,
316 priv->num_phases),
317 longest_range_len
318 );
319
320 middle_phase = ranges[longest_range].start + longest_range_len / 2;
321 middle_phase %= priv->num_phases;
322 real_middle_phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases);
323
324 /*
325 * Since we cut out 270 ~ 360, the original algorithm
326 * still rolling ranges before and after 270 together
327 * in some corner cases, we should adjust it to avoid
328 * using any middle phase located between 270 and 360.
329 * By calculatiion, it happends due to the bad phases
330 * lay between 90 ~ 180. So others are all fine to chose.
331 * Pick 270 is a better choice in those cases. In case of
332 * bad phases exceed 180, the middle phase of rollback
333 * would be bigger than 315, so we chose 360.
334 */
335 if (real_middle_phase > 270) {
336 if (real_middle_phase < 315)
337 real_middle_phase = 270;
338 else
339 real_middle_phase = 360;
340 }
341
342 dev_info(host->dev, "Successfully tuned phase to %d\n",
343 real_middle_phase);
344
345 clk_set_phase(priv->sample_clk, real_middle_phase);
346
347 free:
348 kfree(ranges);
349 return ret;
350 }
351
dw_mci_rk3288_parse_dt(struct dw_mci * host)352 static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
353 {
354 struct device_node *np = host->dev->of_node;
355 struct dw_mci_rockchip_priv_data *priv;
356
357 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
358 if (!priv)
359 return -ENOMEM;
360
361 /*
362 * RK356X SoCs only support 375KHz for ID mode, so any clk request
363 * that less than 1.6MHz(2 * 400KHz * RK3288_CLKGEN_DIV) should be
364 * wrapped into 375KHz
365 */
366 if (of_device_is_compatible(host->dev->of_node,
367 "rockchip,rk3568-dw-mshc"))
368 priv->f_min = 375000;
369 else
370 priv->f_min = 100000;
371
372 if (of_property_read_u32(np, "rockchip,desired-num-phases",
373 &priv->num_phases))
374 priv->num_phases = 360;
375
376 if (of_property_read_u32(np, "rockchip,default-sample-phase",
377 &priv->default_sample_phase))
378 priv->default_sample_phase = 0;
379
380 if (of_property_read_bool(np, "rockchip,use-v2-tuning"))
381 priv->use_v2_tuning = true;
382
383 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
384 if (IS_ERR(priv->drv_clk))
385 dev_dbg(host->dev, "ciu-drive not available\n");
386
387 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
388 if (IS_ERR(priv->sample_clk))
389 dev_dbg(host->dev, "ciu-sample not available\n");
390
391 host->priv = priv;
392
393 return 0;
394 }
395
dw_mci_rockchip_init(struct dw_mci * host)396 static int dw_mci_rockchip_init(struct dw_mci *host)
397 {
398 /* It is slot 8 on Rockchip SoCs */
399 host->sdio_id0 = 8;
400
401 if (of_device_is_compatible(host->dev->of_node,
402 "rockchip,rk3288-dw-mshc"))
403 host->bus_hz /= RK3288_CLKGEN_DIV;
404
405 if (of_device_is_compatible(host->dev->of_node,
406 "rockchip,rv1106-dw-mshc") &&
407 rockchip_get_cpu_version() == 0 &&
408 !strcmp(dev_name(host->dev), "ffaa0000.mmc")) {
409 if (device_property_read_bool(host->dev, "no-sd")) {
410 dev_err(host->dev, "Invalid usage, should be SD card only\n");
411 return -EINVAL;
412 }
413
414 host->is_rv1106_sd = true;
415 dev_info(host->dev, "is rv1106 sd\n");
416 }
417
418 host->need_xfer_timer = true;
419 return 0;
420 }
421
422 /* Common capabilities of RK3288 SoC */
423 static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
424 MMC_CAP_CMD23,
425 MMC_CAP_CMD23,
426 MMC_CAP_CMD23,
427 MMC_CAP_CMD23,
428 };
429
430 static const struct dw_mci_drv_data rk2928_drv_data = {
431 .init = dw_mci_rockchip_init,
432 };
433
434 static const struct dw_mci_drv_data rk3288_drv_data = {
435 .caps = dw_mci_rk3288_dwmmc_caps,
436 .num_caps = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
437 .set_ios = dw_mci_rk3288_set_ios,
438 .execute_tuning = dw_mci_rk3288_execute_tuning,
439 .parse_dt = dw_mci_rk3288_parse_dt,
440 .init = dw_mci_rockchip_init,
441 };
442
443 static const struct of_device_id dw_mci_rockchip_match[] = {
444 { .compatible = "rockchip,rk2928-dw-mshc",
445 .data = &rk2928_drv_data },
446 { .compatible = "rockchip,rk3288-dw-mshc",
447 .data = &rk3288_drv_data },
448 {},
449 };
450 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
451
dw_mci_rockchip_probe(struct platform_device * pdev)452 static int dw_mci_rockchip_probe(struct platform_device *pdev)
453 {
454 const struct dw_mci_drv_data *drv_data;
455 const struct of_device_id *match;
456 int ret;
457 bool use_rpm = true;
458
459 if (!pdev->dev.of_node)
460 return -ENODEV;
461
462 if ((!device_property_read_bool(&pdev->dev, "non-removable") &&
463 !device_property_read_bool(&pdev->dev, "cd-gpios")) ||
464 (device_property_read_bool(&pdev->dev, "no-sd") &&
465 device_property_read_bool(&pdev->dev, "no-mmc")))
466 use_rpm = false;
467
468 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
469 drv_data = match->data;
470
471 /*
472 * increase rpm usage count in order to make
473 * pm_runtime_force_resume calls rpm resume callback
474 */
475 pm_runtime_get_noresume(&pdev->dev);
476 pm_runtime_set_active(&pdev->dev);
477
478 if (use_rpm) {
479 pm_runtime_enable(&pdev->dev);
480 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
481 pm_runtime_use_autosuspend(&pdev->dev);
482 }
483
484 ret = dw_mci_pltfm_register(pdev, drv_data);
485 if (ret) {
486 if (use_rpm) {
487 pm_runtime_disable(&pdev->dev);
488 pm_runtime_set_suspended(&pdev->dev);
489 }
490 pm_runtime_put_noidle(&pdev->dev);
491 return ret;
492 }
493
494 if (use_rpm)
495 pm_runtime_put_autosuspend(&pdev->dev);
496
497 return 0;
498 }
499
dw_mci_rockchip_remove(struct platform_device * pdev)500 static int dw_mci_rockchip_remove(struct platform_device *pdev)
501 {
502 pm_runtime_get_sync(&pdev->dev);
503 pm_runtime_disable(&pdev->dev);
504 pm_runtime_put_noidle(&pdev->dev);
505
506 return dw_mci_pltfm_remove(pdev);
507 }
508
509 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
510 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
511 pm_runtime_force_resume)
512 SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
513 dw_mci_runtime_resume,
514 NULL)
515 };
516
517 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
518 .probe = dw_mci_rockchip_probe,
519 .remove = dw_mci_rockchip_remove,
520 .driver = {
521 .name = "dwmmc_rockchip",
522 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
523 .of_match_table = dw_mci_rockchip_match,
524 .pm = &dw_mci_rockchip_dev_pm_ops,
525 },
526 };
527
528 module_platform_driver(dw_mci_rockchip_pltfm_driver);
529
530 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
531 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
532 MODULE_ALIAS("platform:dwmmc_rockchip");
533 MODULE_LICENSE("GPL v2");
534