1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Secure Digital Host Controller
4 //
5 // Copyright (C) 2018 Spreadtrum, Inc.
6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/highmem.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_gpio.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/slab.h>
20
21 #include "sdhci-pltfm.h"
22 #include "mmc_hsq.h"
23
24 /* SDHCI_ARGUMENT2 register high 16bit */
25 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
26
27 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200
28 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
29 #define SDHCI_SPRD_DLL_EN BIT(21)
30 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
31 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
32 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
33
34 #define SDHCI_SPRD_REG_32_DLL_DLY 0x204
35
36 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
37 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
38 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
39 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
40 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
41
42 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
43 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
44 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
45
46 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C
47 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
48 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
49
50 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
51
52 /* SDHCI_HOST_CONTROL2 */
53 #define SDHCI_SPRD_CTRL_HS200 0x0005
54 #define SDHCI_SPRD_CTRL_HS400 0x0006
55 #define SDHCI_SPRD_CTRL_HS400ES 0x0007
56
57 /*
58 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
59 * reserved, and only used on Spreadtrum's design, the hardware cannot work
60 * if this bit is cleared.
61 * 1 : normal work
62 * 0 : hardware reset
63 */
64 #define SDHCI_HW_RESET_CARD BIT(3)
65
66 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF
67 #define SDHCI_SPRD_CLK_MAX_DIV 1023
68
69 #define SDHCI_SPRD_CLK_DEF_RATE 26000000
70 #define SDHCI_SPRD_PHY_DLL_CLK 52000000
71
72 struct sdhci_sprd_host {
73 u32 version;
74 struct clk *clk_sdio;
75 struct clk *clk_enable;
76 struct clk *clk_2x_enable;
77 struct pinctrl *pinctrl;
78 struct pinctrl_state *pins_uhs;
79 struct pinctrl_state *pins_default;
80 u32 base_rate;
81 int flags; /* backup of host attribute */
82 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
83 };
84
85 struct sdhci_sprd_phy_cfg {
86 const char *property;
87 u8 timing;
88 };
89
90 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
91 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
92 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
93 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
94 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
95 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
96 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
97 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
98 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
99 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
100 };
101
102 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
103
sdhci_sprd_init_config(struct sdhci_host * host)104 static void sdhci_sprd_init_config(struct sdhci_host *host)
105 {
106 u16 val;
107
108 /* set dll backup mode */
109 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
110 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
111 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
112 }
113
sdhci_sprd_readl(struct sdhci_host * host,int reg)114 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
115 {
116 if (unlikely(reg == SDHCI_MAX_CURRENT))
117 return SDHCI_SPRD_MAX_CUR;
118
119 return readl_relaxed(host->ioaddr + reg);
120 }
121
sdhci_sprd_writel(struct sdhci_host * host,u32 val,int reg)122 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
123 {
124 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
125 if (unlikely(reg == SDHCI_MAX_CURRENT))
126 return;
127
128 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
129 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
130
131 writel_relaxed(val, host->ioaddr + reg);
132 }
133
sdhci_sprd_writew(struct sdhci_host * host,u16 val,int reg)134 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
135 {
136 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
137 if (unlikely(reg == SDHCI_BLOCK_COUNT))
138 return;
139
140 writew_relaxed(val, host->ioaddr + reg);
141 }
142
sdhci_sprd_writeb(struct sdhci_host * host,u8 val,int reg)143 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
144 {
145 /*
146 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
147 * standard specification, sdhci_reset() write this register directly
148 * without checking other reserved bits, that will clear BIT(3) which
149 * is defined as hardware reset on Spreadtrum's platform and clearing
150 * it by mistake will lead the card not work. So here we need to work
151 * around it.
152 */
153 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
154 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
155 val |= SDHCI_HW_RESET_CARD;
156 }
157
158 writeb_relaxed(val, host->ioaddr + reg);
159 }
160
sdhci_sprd_sd_clk_off(struct sdhci_host * host)161 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
162 {
163 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
164
165 ctrl &= ~SDHCI_CLOCK_CARD_EN;
166 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
167 }
168
sdhci_sprd_sd_clk_on(struct sdhci_host * host)169 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
170 {
171 u16 ctrl;
172
173 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
174 ctrl |= SDHCI_CLOCK_CARD_EN;
175 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
176 }
177
178 static inline void
sdhci_sprd_set_dll_invert(struct sdhci_host * host,u32 mask,bool en)179 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
180 {
181 u32 dll_dly_offset;
182
183 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
184 if (en)
185 dll_dly_offset |= mask;
186 else
187 dll_dly_offset &= ~mask;
188 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
189 }
190
sdhci_sprd_calc_div(u32 base_clk,u32 clk)191 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
192 {
193 u32 div;
194
195 /* select 2x clock source */
196 if (base_clk <= clk * 2)
197 return 0;
198
199 div = (u32) (base_clk / (clk * 2));
200
201 if ((base_clk / div) > (clk * 2))
202 div++;
203
204 if (div > SDHCI_SPRD_CLK_MAX_DIV)
205 div = SDHCI_SPRD_CLK_MAX_DIV;
206
207 if (div % 2)
208 div = (div + 1) / 2;
209 else
210 div = div / 2;
211
212 return div;
213 }
214
_sdhci_sprd_set_clock(struct sdhci_host * host,unsigned int clk)215 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
216 unsigned int clk)
217 {
218 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
219 u32 div, val, mask;
220
221 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
222
223 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
224 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
225 sdhci_enable_clk(host, div);
226
227 /* enable auto gate sdhc_enable_auto_gate */
228 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
229 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
230 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
231 if (mask != (val & mask)) {
232 val |= mask;
233 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
234 }
235 }
236
sdhci_sprd_enable_phy_dll(struct sdhci_host * host)237 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
238 {
239 u32 tmp;
240
241 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
242 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
243 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
244 /* wait 1ms */
245 usleep_range(1000, 1250);
246
247 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
248 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
249 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
250 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
251 /* wait 1ms */
252 usleep_range(1000, 1250);
253
254 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
255 tmp |= SDHCI_SPRD_DLL_EN;
256 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
257 /* wait 1ms */
258 usleep_range(1000, 1250);
259 }
260
sdhci_sprd_set_clock(struct sdhci_host * host,unsigned int clock)261 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
262 {
263 bool en = false, clk_changed = false;
264
265 if (clock == 0) {
266 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
267 } else if (clock != host->clock) {
268 sdhci_sprd_sd_clk_off(host);
269 _sdhci_sprd_set_clock(host, clock);
270
271 if (clock <= 400000)
272 en = true;
273 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
274 SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
275 clk_changed = true;
276 } else {
277 _sdhci_sprd_set_clock(host, clock);
278 }
279
280 /*
281 * According to the Spreadtrum SD host specification, when we changed
282 * the clock to be more than 52M, we should enable the PHY DLL which
283 * is used to track the clock frequency to make the clock work more
284 * stable. Otherwise deviation may occur of the higher clock.
285 */
286 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
287 sdhci_sprd_enable_phy_dll(host);
288 }
289
sdhci_sprd_get_max_clock(struct sdhci_host * host)290 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
291 {
292 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
293
294 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
295 }
296
sdhci_sprd_get_min_clock(struct sdhci_host * host)297 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
298 {
299 return 100000;
300 }
301
sdhci_sprd_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)302 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
303 unsigned int timing)
304 {
305 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
306 struct mmc_host *mmc = host->mmc;
307 u32 *p = sprd_host->phy_delay;
308 u16 ctrl_2;
309
310 if (timing == host->timing)
311 return;
312
313 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
314 /* Select Bus Speed Mode for host */
315 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
316 switch (timing) {
317 case MMC_TIMING_UHS_SDR12:
318 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
319 break;
320 case MMC_TIMING_MMC_HS:
321 case MMC_TIMING_SD_HS:
322 case MMC_TIMING_UHS_SDR25:
323 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
324 break;
325 case MMC_TIMING_UHS_SDR50:
326 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
327 break;
328 case MMC_TIMING_UHS_SDR104:
329 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
330 break;
331 case MMC_TIMING_UHS_DDR50:
332 case MMC_TIMING_MMC_DDR52:
333 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
334 break;
335 case MMC_TIMING_MMC_HS200:
336 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
337 break;
338 case MMC_TIMING_MMC_HS400:
339 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
340 break;
341 default:
342 break;
343 }
344
345 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
346
347 if (!mmc->ios.enhanced_strobe)
348 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
349 }
350
sdhci_sprd_hw_reset(struct sdhci_host * host)351 static void sdhci_sprd_hw_reset(struct sdhci_host *host)
352 {
353 int val;
354
355 /*
356 * Note: don't use sdhci_writeb() API here since it is redirected to
357 * sdhci_sprd_writeb() in which we have a workaround for
358 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
359 * not be cleared.
360 */
361 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
362 val &= ~SDHCI_HW_RESET_CARD;
363 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
364 /* wait for 10 us */
365 usleep_range(10, 20);
366
367 val |= SDHCI_HW_RESET_CARD;
368 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
369 usleep_range(300, 500);
370 }
371
sdhci_sprd_get_max_timeout_count(struct sdhci_host * host)372 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
373 {
374 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
375 return 1 << 31;
376 }
377
sdhci_sprd_get_ro(struct sdhci_host * host)378 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
379 {
380 return 0;
381 }
382
sdhci_sprd_request_done(struct sdhci_host * host,struct mmc_request * mrq)383 static void sdhci_sprd_request_done(struct sdhci_host *host,
384 struct mmc_request *mrq)
385 {
386 /* Validate if the request was from software queue firstly. */
387 if (mmc_hsq_finalize_request(host->mmc, mrq))
388 return;
389
390 mmc_request_done(host->mmc, mrq);
391 }
392
393 static struct sdhci_ops sdhci_sprd_ops = {
394 .read_l = sdhci_sprd_readl,
395 .write_l = sdhci_sprd_writel,
396 .write_w = sdhci_sprd_writew,
397 .write_b = sdhci_sprd_writeb,
398 .set_clock = sdhci_sprd_set_clock,
399 .get_max_clock = sdhci_sprd_get_max_clock,
400 .get_min_clock = sdhci_sprd_get_min_clock,
401 .set_bus_width = sdhci_set_bus_width,
402 .reset = sdhci_reset,
403 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
404 .hw_reset = sdhci_sprd_hw_reset,
405 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
406 .get_ro = sdhci_sprd_get_ro,
407 .request_done = sdhci_sprd_request_done,
408 };
409
sdhci_sprd_check_auto_cmd23(struct mmc_host * mmc,struct mmc_request * mrq)410 static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
411 struct mmc_request *mrq)
412 {
413 struct sdhci_host *host = mmc_priv(mmc);
414 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
415
416 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
417
418 /*
419 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
420 * block count register which doesn't support stuff bits of
421 * CMD23 argument on Spreadtrum's sd host controller.
422 */
423 if (host->version >= SDHCI_SPEC_410 &&
424 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
425 (host->flags & SDHCI_AUTO_CMD23))
426 host->flags &= ~SDHCI_AUTO_CMD23;
427 }
428
sdhci_sprd_request(struct mmc_host * mmc,struct mmc_request * mrq)429 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
430 {
431 sdhci_sprd_check_auto_cmd23(mmc, mrq);
432
433 sdhci_request(mmc, mrq);
434 }
435
sdhci_sprd_request_atomic(struct mmc_host * mmc,struct mmc_request * mrq)436 static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
437 struct mmc_request *mrq)
438 {
439 sdhci_sprd_check_auto_cmd23(mmc, mrq);
440
441 return sdhci_request_atomic(mmc, mrq);
442 }
443
sdhci_sprd_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)444 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
445 {
446 struct sdhci_host *host = mmc_priv(mmc);
447 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
448 int ret;
449
450 if (!IS_ERR(mmc->supply.vqmmc)) {
451 ret = mmc_regulator_set_vqmmc(mmc, ios);
452 if (ret < 0) {
453 pr_err("%s: Switching signalling voltage failed\n",
454 mmc_hostname(mmc));
455 return ret;
456 }
457 }
458
459 if (IS_ERR(sprd_host->pinctrl))
460 goto reset;
461
462 switch (ios->signal_voltage) {
463 case MMC_SIGNAL_VOLTAGE_180:
464 ret = pinctrl_select_state(sprd_host->pinctrl,
465 sprd_host->pins_uhs);
466 if (ret) {
467 pr_err("%s: failed to select uhs pin state\n",
468 mmc_hostname(mmc));
469 return ret;
470 }
471 break;
472
473 default:
474 fallthrough;
475 case MMC_SIGNAL_VOLTAGE_330:
476 ret = pinctrl_select_state(sprd_host->pinctrl,
477 sprd_host->pins_default);
478 if (ret) {
479 pr_err("%s: failed to select default pin state\n",
480 mmc_hostname(mmc));
481 return ret;
482 }
483 break;
484 }
485
486 /* Wait for 300 ~ 500 us for pin state stable */
487 usleep_range(300, 500);
488
489 reset:
490 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
491
492 return 0;
493 }
494
sdhci_sprd_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)495 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
496 struct mmc_ios *ios)
497 {
498 struct sdhci_host *host = mmc_priv(mmc);
499 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
500 u32 *p = sprd_host->phy_delay;
501 u16 ctrl_2;
502
503 if (!ios->enhanced_strobe)
504 return;
505
506 sdhci_sprd_sd_clk_off(host);
507
508 /* Set HS400 enhanced strobe mode */
509 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
510 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
511 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
512 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
513
514 sdhci_sprd_sd_clk_on(host);
515
516 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
517 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
518 SDHCI_SPRD_REG_32_DLL_DLY);
519 }
520
sdhci_sprd_phy_param_parse(struct sdhci_sprd_host * sprd_host,struct device_node * np)521 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
522 struct device_node *np)
523 {
524 u32 *p = sprd_host->phy_delay;
525 int ret, i, index;
526 u32 val[4];
527
528 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
529 ret = of_property_read_u32_array(np,
530 sdhci_sprd_phy_cfgs[i].property, val, 4);
531 if (ret)
532 continue;
533
534 index = sdhci_sprd_phy_cfgs[i].timing;
535 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
536 }
537 }
538
539 static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
540 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
541 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
542 SDHCI_QUIRK_MISSING_CAPS,
543 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
544 SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
545 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
546 .ops = &sdhci_sprd_ops,
547 };
548
sdhci_sprd_probe(struct platform_device * pdev)549 static int sdhci_sprd_probe(struct platform_device *pdev)
550 {
551 struct sdhci_host *host;
552 struct sdhci_sprd_host *sprd_host;
553 struct mmc_hsq *hsq;
554 struct clk *clk;
555 int ret = 0;
556
557 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
558 if (IS_ERR(host))
559 return PTR_ERR(host);
560
561 host->dma_mask = DMA_BIT_MASK(64);
562 pdev->dev.dma_mask = &host->dma_mask;
563 host->mmc_host_ops.request = sdhci_sprd_request;
564 host->mmc_host_ops.hs400_enhanced_strobe =
565 sdhci_sprd_hs400_enhanced_strobe;
566 /*
567 * We can not use the standard ops to change and detect the voltage
568 * signal for Spreadtrum SD host controller, since our voltage regulator
569 * for I/O is fixed in hardware, that means we do not need control
570 * the standard SD host controller to change the I/O voltage.
571 */
572 host->mmc_host_ops.start_signal_voltage_switch =
573 sdhci_sprd_voltage_switch;
574
575 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
576 MMC_CAP_WAIT_WHILE_BUSY;
577
578 ret = mmc_of_parse(host->mmc);
579 if (ret)
580 goto pltfm_free;
581
582 if (!mmc_card_is_removable(host->mmc))
583 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
584 else
585 host->always_defer_done = true;
586
587 sprd_host = TO_SPRD_HOST(host);
588 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
589
590 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
591 if (!IS_ERR(sprd_host->pinctrl)) {
592 sprd_host->pins_uhs =
593 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
594 if (IS_ERR(sprd_host->pins_uhs)) {
595 ret = PTR_ERR(sprd_host->pins_uhs);
596 goto pltfm_free;
597 }
598
599 sprd_host->pins_default =
600 pinctrl_lookup_state(sprd_host->pinctrl, "default");
601 if (IS_ERR(sprd_host->pins_default)) {
602 ret = PTR_ERR(sprd_host->pins_default);
603 goto pltfm_free;
604 }
605 }
606
607 clk = devm_clk_get(&pdev->dev, "sdio");
608 if (IS_ERR(clk)) {
609 ret = PTR_ERR(clk);
610 goto pltfm_free;
611 }
612 sprd_host->clk_sdio = clk;
613 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
614 if (!sprd_host->base_rate)
615 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
616
617 clk = devm_clk_get(&pdev->dev, "enable");
618 if (IS_ERR(clk)) {
619 ret = PTR_ERR(clk);
620 goto pltfm_free;
621 }
622 sprd_host->clk_enable = clk;
623
624 clk = devm_clk_get(&pdev->dev, "2x_enable");
625 if (!IS_ERR(clk))
626 sprd_host->clk_2x_enable = clk;
627
628 ret = clk_prepare_enable(sprd_host->clk_sdio);
629 if (ret)
630 goto pltfm_free;
631
632 ret = clk_prepare_enable(sprd_host->clk_enable);
633 if (ret)
634 goto clk_disable;
635
636 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
637 if (ret)
638 goto clk_disable2;
639
640 sdhci_sprd_init_config(host);
641 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
642 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
643 SDHCI_VENDOR_VER_SHIFT);
644
645 pm_runtime_get_noresume(&pdev->dev);
646 pm_runtime_set_active(&pdev->dev);
647 pm_runtime_enable(&pdev->dev);
648 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
649 pm_runtime_use_autosuspend(&pdev->dev);
650 pm_suspend_ignore_children(&pdev->dev, 1);
651
652 sdhci_enable_v4_mode(host);
653
654 /*
655 * Supply the existing CAPS, but clear the UHS-I modes. This
656 * will allow these modes to be specified only by device
657 * tree properties through mmc_of_parse().
658 */
659 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
660 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
661 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
662 SDHCI_SUPPORT_DDR50);
663
664 ret = sdhci_setup_host(host);
665 if (ret)
666 goto pm_runtime_disable;
667
668 sprd_host->flags = host->flags;
669
670 hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
671 if (!hsq) {
672 ret = -ENOMEM;
673 goto err_cleanup_host;
674 }
675
676 ret = mmc_hsq_init(hsq, host->mmc);
677 if (ret)
678 goto err_cleanup_host;
679
680 ret = __sdhci_add_host(host);
681 if (ret)
682 goto err_cleanup_host;
683
684 pm_runtime_mark_last_busy(&pdev->dev);
685 pm_runtime_put_autosuspend(&pdev->dev);
686
687 return 0;
688
689 err_cleanup_host:
690 sdhci_cleanup_host(host);
691
692 pm_runtime_disable:
693 pm_runtime_put_noidle(&pdev->dev);
694 pm_runtime_disable(&pdev->dev);
695 pm_runtime_set_suspended(&pdev->dev);
696
697 clk_disable_unprepare(sprd_host->clk_2x_enable);
698
699 clk_disable2:
700 clk_disable_unprepare(sprd_host->clk_enable);
701
702 clk_disable:
703 clk_disable_unprepare(sprd_host->clk_sdio);
704
705 pltfm_free:
706 sdhci_pltfm_free(pdev);
707 return ret;
708 }
709
sdhci_sprd_remove(struct platform_device * pdev)710 static int sdhci_sprd_remove(struct platform_device *pdev)
711 {
712 struct sdhci_host *host = platform_get_drvdata(pdev);
713 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
714
715 sdhci_remove_host(host, 0);
716
717 clk_disable_unprepare(sprd_host->clk_sdio);
718 clk_disable_unprepare(sprd_host->clk_enable);
719 clk_disable_unprepare(sprd_host->clk_2x_enable);
720
721 sdhci_pltfm_free(pdev);
722
723 return 0;
724 }
725
726 static const struct of_device_id sdhci_sprd_of_match[] = {
727 { .compatible = "sprd,sdhci-r11", },
728 { }
729 };
730 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
731
732 #ifdef CONFIG_PM
sdhci_sprd_runtime_suspend(struct device * dev)733 static int sdhci_sprd_runtime_suspend(struct device *dev)
734 {
735 struct sdhci_host *host = dev_get_drvdata(dev);
736 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
737
738 mmc_hsq_suspend(host->mmc);
739 sdhci_runtime_suspend_host(host);
740
741 clk_disable_unprepare(sprd_host->clk_sdio);
742 clk_disable_unprepare(sprd_host->clk_enable);
743 clk_disable_unprepare(sprd_host->clk_2x_enable);
744
745 return 0;
746 }
747
sdhci_sprd_runtime_resume(struct device * dev)748 static int sdhci_sprd_runtime_resume(struct device *dev)
749 {
750 struct sdhci_host *host = dev_get_drvdata(dev);
751 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
752 int ret;
753
754 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
755 if (ret)
756 return ret;
757
758 ret = clk_prepare_enable(sprd_host->clk_enable);
759 if (ret)
760 goto clk_2x_disable;
761
762 ret = clk_prepare_enable(sprd_host->clk_sdio);
763 if (ret)
764 goto clk_disable;
765
766 sdhci_runtime_resume_host(host, 1);
767 mmc_hsq_resume(host->mmc);
768
769 return 0;
770
771 clk_disable:
772 clk_disable_unprepare(sprd_host->clk_enable);
773
774 clk_2x_disable:
775 clk_disable_unprepare(sprd_host->clk_2x_enable);
776
777 return ret;
778 }
779 #endif
780
781 static const struct dev_pm_ops sdhci_sprd_pm_ops = {
782 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
783 pm_runtime_force_resume)
784 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
785 sdhci_sprd_runtime_resume, NULL)
786 };
787
788 static struct platform_driver sdhci_sprd_driver = {
789 .probe = sdhci_sprd_probe,
790 .remove = sdhci_sprd_remove,
791 .driver = {
792 .name = "sdhci_sprd_r11",
793 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
794 .of_match_table = of_match_ptr(sdhci_sprd_of_match),
795 .pm = &sdhci_sprd_pm_ops,
796 },
797 };
798 module_platform_driver(sdhci_sprd_driver);
799
800 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
801 MODULE_LICENSE("GPL v2");
802 MODULE_ALIAS("platform:sdhci-sprd-r11");
803