Home
last modified time | relevance | path

Searched +full:dphy +full:- +full:cfg (Results 1 – 25 of 52) sorted by relevance

123

/OK3568_Linux_fs/kernel/drivers/phy/cadence/
H A Dcdns-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright: 2017-2018 Cadence Design Systems, Inc.
16 #include <linux/phy/phy-mipi-dphy.h>
21 /* DPHY registers */
76 int (*probe)(struct cdns_dphy *dphy);
77 void (*remove)(struct cdns_dphy *dphy);
78 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
79 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
80 enum cdns_dphy_clk_lane_cfg cfg);
81 void (*set_pll_cfg)(struct cdns_dphy *dphy,
[all …]
/OK3568_Linux_fs/kernel/drivers/media/spi/
H A Drk1608_dphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Rockchip Electronics Co., Ltd.
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-fwnode.h>
20 #include <media/v4l2-subdev.h>
26 #include <linux/rk-preisp.h>
27 #include <linux/rk-isp1-config.h>
28 #include <linux/rk-camera-module.h>
32 #define RK1608_DPHY_NAME "RK1608-dphy"
35 * Rk1608 is used as the Pre-ISP to link on Soc, which mainly has two
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
19 /* DPHY registers */
47 ((x) < 32) ? 0xe0 | ((x) - 16) : \
48 ((x) < 64) ? 0xc0 | ((x) - 32) : \
49 ((x) < 128) ? 0x80 | ((x) - 64) : \
50 ((x) - 128))
51 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
52 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
81 /* DPHY PLL parameters */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Drockchip-mipi-dphy-rx0.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
10 - Helen Koike <helen.koike@collabora.com>
11 - Ezequiel Garcia <ezequiel@collabora.com>
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/rkisp1/
H A Drkisp1-isp.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip ISP1 Driver - ISP Subdevice
13 #include <linux/phy/phy-mipi-dphy.h>
17 #include <media/v4l2-event.h>
19 #include "rkisp1-common.h"
40 * +---------------------------------------------------------+
42 * | +---------------------------------------------------+ |
45 * | | +--------------------------------------------+ | |
48 * | | | +---------------------------------+ | | |
51 * | | | +---------------------------------+ | | |
[all …]
H A Drkisp1-common.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
3 * Rockchip ISP1 Driver - Common definitions
16 #include <media/media-device.h>
17 #include <media/media-entity.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/videobuf2-v4l2.h>
22 #include "rkisp1-regs.h"
23 #include "uapi/rkisp1-config.h"
92 * struct rkisp1_sensor_async - A container for the v4l2_async_subdev to add to the notifier
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Drockchip-mipi-dphy.txt1 Rockchip SoC MIPI RX D-PHY
2 -------------------------------------------------------------
5 - compatible: value should be one of the following
6 "rockchip,rk1808-mipi-dphy-rx"
7 "rockchip,rk3288-mipi-dphy"
8 "rockchip,rk3326-mipi-dphy"
9 "rockchip,rk3368-mipi-dphy"
10 "rockchip,rk3399-mipi-dphy"
11 "rockchip,rv1126-csi-dphy"
12 - clocks : list of clock specifiers, corresponding to entries in
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
11 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
312 orig = readl(inno->phy_base + reg); in phy_update_bits()
315 writel(tmp, inno->phy_base + reg); in phy_update_bits()
323 orig = readl(inno->host_base + reg); in host_update_bits()
326 writel(tmp, inno->host_base + reg); in host_update_bits()
332 unsigned long prate = clk_get_rate(inno->ref_clk); in inno_dsidphy_pll_calc_rate()
343 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 in inno_dsidphy_pll_calc_rate()
[all …]
H A Dphy-rockchip-csi2-dphy.c1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip MIPI CSI2 DPHY driver
19 #include <media/media-entity.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-fwnode.h>
22 #include <media/v4l2-subdev.h>
23 #include <media/v4l2-device.h>
25 #include "phy-rockchip-csi2-dphy-common.h"
26 #include "phy-rockchip-samsung-dcphy.h"
56 struct csi2_dphy *dphy = to_csi2_dphy(sd); in get_remote_sensor() local
[all …]
H A Dphy-rockchip-dphy-rx0.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Rockchip MIPI Synopsys DPHY RX0 driver
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
163 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
[all …]
H A Dphy-rockchip-mipi-rx.c2 * Rockchip MIPI RX Synopsys/Innosilicon DPHY driver
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
46 #include <media/media-entity.h>
47 #include <media/v4l2-ctrls.h>
48 #include <media/v4l2-fwnode.h>
49 #include <media/v4l2-subdev.h>
50 #include <media/v4l2-device.h>
129 /* Configure the count time of the THS-SETTLE by protocol. */
341 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
[all …]
/OK3568_Linux_fs/kernel/drivers/video/rockchip/vehicle/
H A Dvehicle_cif.c1 // SPDX-License-Identifier: GPL-2.0
9 * Jianwei Fan <jianwei.fan@rock-chips.com>
30 #include "vehicle-csi2-dphy-common.h"
37 #include <media/v4l2-mediabus.h>
40 #include <dt-bindings/soc/rockchip-system-status.h>
41 #include <soc/rockchip/rockchip-system-status.h>
108 //define dphy and csi clks/rst
614 //define dphy and csi regs
1241 void __iomem *base = cif->base; in rkcif_write_reg()
1242 const struct vehicle_cif_reg *reg = &cif->cif_regs[index]; in rkcif_write_reg()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
85 * 2. Configure DSI Host and DPHY and enable DPHY
136 int ret = dsi->error; in nwl_dsi_clear_error()
138 dsi->error = 0; in nwl_dsi_clear_error()
146 if (dsi->error) in nwl_dsi_write()
149 ret = regmap_write(dsi->regmap, reg, val); in nwl_dsi_write()
151 DRM_DEV_ERROR(dsi->dev, in nwl_dsi_write()
154 dsi->error = ret; in nwl_dsi_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/
H A Dphy-core-mipi-dphy.c1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/phy/phy-mipi-dphy.h>
18 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
20 * of the D-PHY specification (v2.1).
25 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_get_default_config() argument
30 if (!cfg) in phy_mipi_dphy_get_default_config()
31 return -EINVAL; in phy_mipi_dphy_get_default_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_get_default_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_get_default_config()
41 cfg->clk_pre = 8000; in phy_mipi_dphy_get_default_config()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dlt6911uxe.c1 // SPDX-License-Identifier: GPL-2.0
5 * lt6911uxe HDMI to MIPI CSI-2 bridge driver.
7 * Author: Jianwei Fan <jianwei.fan@rock-chips.com>
10 * V0.0X01.0X01 support DPHY 4K60.
15 * 2.add dphy timing reg.
28 #include <linux/rk-camera-module.h>
31 #include <linux/v4l2-dv-timings.h>
36 #include <media/v4l2-controls_rockchip.h>
37 #include <media/v4l2-ctrls.h>
38 #include <media/v4l2-device.h>
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp1/
H A Drkisp1.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 #include <linux/rk-preisp.h>
45 #include <media/v4l2-event.h>
46 #include <media/media-entity.h>
63 * +---------------------------------------------------------+
65 * | +---------------------------------------------------+ |
68 * | | +--------------------------------------------+ | |
71 * | | | +---------------------------------+ | | |
74 * | | | +---------------------------------+ | | |
[all …]
H A Ddev.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
47 #include <media/videobuf2-dma-contig.h>
48 #include <dt-bindings/soc/rockchip-system-status.h>
49 #include <soc/rockchip/rockchip-system-status.h>
74 MODULE_PARM_DESC(debug, "Debug level (0-1)");
89 v4l2_async_notifier_clr_unready_dev(&isp_dev->notifier); in __rkisp1_clr_unready_dev()
116 p->num_subdevs = 0; in __isp_pipeline_prepare()
117 memset(p->subdevs, 0, sizeof(p->subdevs)); in __isp_pipeline_prepare()
119 if (dev->isp_inp == INP_DMARX_ISP) in __isp_pipeline_prepare()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
321 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), in sun6i_dsi_inst_setup()
332 u8 lanes_mask = GENMASK(device->lanes - 1, 0); in sun6i_dsi_inst_init()
359 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0), in sun6i_dsi_inst_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Ddw_mipi_dsi2.c2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
6 * Author: Guochun Huang <hero.huang@rock-chips.com>
23 #include <asm/arch-rockchip/clock.h>
75 #define PHY_LANES(x) UPDATE(x - 1, 5, 4)
200 DPHY, enumerator
224 /* Non-SNPS PHY */
232 * struct mipi_dphy_configure - MIPI D-PHY configuration set
235 * MIPI D-PHY phy.
301 writel(val, dsi2->base + reg); in dsi_write()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rv1126-cru.h>
7 #include <dt-bindings/power/rv1126-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rv1126.h>
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/imx/
H A Dimx6-mipi-csi2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * MIPI CSI-2 Receiver Subdev for Freescale i.MX6 SOC.
5 * Copyright (c) 2012-2017 Mentor Graphics Inc.
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-fwnode.h>
17 #include <media/v4l2-mc.h>
18 #include <media/v4l2-subdev.h>
19 #include "imx-media.h"
31 * The default maximum bit-rate per lane in Mbps, if the
57 #define DEVICE_NAME "imx6-mipi-csi2"
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/tegra-video/
H A Dcsi.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <media/v4l2-fwnode.h>
67 struct v4l2_subdev_pad_config *cfg, in csi_enum_bus_code() argument
71 return -ENOIOCTLCMD; in csi_enum_bus_code()
73 if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) in csi_enum_bus_code()
74 return -EINVAL; in csi_enum_bus_code()
76 code->code = tegra_csi_tpg_fmts[code->index].code; in csi_enum_bus_code()
82 struct v4l2_subdev_pad_config *cfg, in csi_get_format() argument
88 return -ENOIOCTLCMD; in csi_get_format()
90 fmt->format = csi_chan->format; in csi_get_format()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rv1126-cru.h>
7 #include <dt-bindings/power/rv1126-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rv1126.h>
[all …]
/OK3568_Linux_fs/external/camera_engine_rkaiq/rkaiq/uAPI2/
H A Drk_aiq_user_api2_camgroup.cpp10 * http://www.apache.org/licenses/LICENSE-2.0
37 ret = camgroup_ctx->cam_group_manager->bind(aiq_ctx->_rkAiqManager.ptr()); in _cam_group_bind()
39 LOGE("bind sensor %s aiq ctx %p failed !", aiq_ctx->_sensor_entity_name, aiq_ctx); in _cam_group_bind()
43 camgroup_ctx->cam_group_manager->setContainerCtx(camgroup_ctx); in _cam_group_bind()
46 aiq_ctx->_camGroupManager = camgroup_ctx->cam_group_manager.ptr(); in _cam_group_bind()
47 aiq_ctx->_analyzer->setCamGroupManager(aiq_ctx->_camGroupManager); in _cam_group_bind()
51 aiq_ctx->_rkAiqManager->setCamGroupManager(aiq_ctx->_camGroupManager, in _cam_group_bind()
52 camgroup_ctx->cam_ctxs_num == 0 ? true : false); in _cam_group_bind()
54 if (aiq_ctx->_is_1608_sensor) { in _cam_group_bind()
56 aiq_ctx->_rkAiqManager->setCamGroupManager(aiq_ctx->_camGroupManager, false); in _cam_group_bind()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp/
H A Drkisp.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
40 #include <linux/rk-camera-module.h>
45 #include <linux/rk-preisp.h>
46 #include <linux/rk-isp21-config.h>
48 #include <media/v4l2-event.h>
49 #include <media/media-entity.h>
58 #define ISP_SUBDEV_NAME DRIVER_NAME "-isp-subdev"
71 * +---------------------------------------------------------+
73 * | +---------------------------------------------------+ |
[all …]

123