1 /*
2 * Rockchip isp1 driver
3 *
4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/clk.h>
36 #include <linux/compat.h>
37 #include <linux/iopoll.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/regmap.h>
40 #include <linux/rk-camera-module.h>
41 #include <linux/videodev2.h>
42 #include <linux/vmalloc.h>
43 #include <linux/kfifo.h>
44 #include <linux/interrupt.h>
45 #include <linux/rk-preisp.h>
46 #include <linux/rk-isp21-config.h>
47 #include <linux/iommu.h>
48 #include <media/v4l2-event.h>
49 #include <media/media-entity.h>
50
51 #include "common.h"
52 #include "isp_external.h"
53 #include "regs.h"
54 #include "rkisp_tb_helper.h"
55
56 #define ISP_V4L2_EVENT_ELEMS 4
57
58 #define ISP_SUBDEV_NAME DRIVER_NAME "-isp-subdev"
59 /*
60 * NOTE: MIPI controller and input MUX are also configured in this file,
61 * because ISP Subdev is not only describe ISP submodule(input size,format, output size, format),
62 * but also a virtual route device.
63 */
64
65 /*
66 * There are many variables named with format/frame in below code,
67 * please see here for their meaning.
68 *
69 * Cropping regions of ISP
70 *
71 * +---------------------------------------------------------+
72 * | Sensor image/ISP in_frm |
73 * | +---------------------------------------------------+ |
74 * | | ISP_ACQ (for black level) | |
75 * | | in_crop | |
76 * | | +--------------------------------------------+ | |
77 * | | | ISP_IS | | |
78 * | | | rkisp_isp_subdev: out_crop | | |
79 * | | | | | |
80 * | | | | | |
81 * | | | | | |
82 * | | | | | |
83 * | | +--------------------------------------------+ | |
84 * | +---------------------------------------------------+ |
85 * +---------------------------------------------------------+
86 */
87
88 static void rkisp_config_cmsk(struct rkisp_device *dev);
89
90 struct backup_reg {
91 const u32 base;
92 const u32 shd;
93 u32 val;
94 };
95
sd_to_isp_dev(struct v4l2_subdev * sd)96 static inline struct rkisp_device *sd_to_isp_dev(struct v4l2_subdev *sd)
97 {
98 return container_of(sd->v4l2_dev, struct rkisp_device, v4l2_dev);
99 }
100
mbus_pixelcode_to_mipi_dt(u32 pixelcode)101 static int mbus_pixelcode_to_mipi_dt(u32 pixelcode)
102 {
103 int mipi_dt;
104
105 switch (pixelcode) {
106 case MEDIA_BUS_FMT_Y8_1X8:
107 case MEDIA_BUS_FMT_SRGGB8_1X8:
108 case MEDIA_BUS_FMT_SBGGR8_1X8:
109 case MEDIA_BUS_FMT_SGBRG8_1X8:
110 case MEDIA_BUS_FMT_SGRBG8_1X8:
111 mipi_dt = CIF_CSI2_DT_RAW8;
112 break;
113 case MEDIA_BUS_FMT_Y10_1X10:
114 case MEDIA_BUS_FMT_SBGGR10_1X10:
115 case MEDIA_BUS_FMT_SRGGB10_1X10:
116 case MEDIA_BUS_FMT_SGBRG10_1X10:
117 case MEDIA_BUS_FMT_SGRBG10_1X10:
118 mipi_dt = CIF_CSI2_DT_RAW10;
119 break;
120 case MEDIA_BUS_FMT_Y12_1X12:
121 case MEDIA_BUS_FMT_SRGGB12_1X12:
122 case MEDIA_BUS_FMT_SBGGR12_1X12:
123 case MEDIA_BUS_FMT_SGBRG12_1X12:
124 case MEDIA_BUS_FMT_SGRBG12_1X12:
125 mipi_dt = CIF_CSI2_DT_RAW12;
126 break;
127 case MEDIA_BUS_FMT_YUYV8_2X8:
128 case MEDIA_BUS_FMT_YVYU8_2X8:
129 case MEDIA_BUS_FMT_UYVY8_2X8:
130 case MEDIA_BUS_FMT_VYUY8_2X8:
131 mipi_dt = CIF_CSI2_DT_YUV422_8b;
132 break;
133 case MEDIA_BUS_FMT_EBD_1X8:
134 mipi_dt = CIF_CSI2_DT_EBD;
135 break;
136 case MEDIA_BUS_FMT_SPD_2X8:
137 mipi_dt = CIF_CSI2_DT_SPD;
138 break;
139 default:
140 mipi_dt = -EINVAL;
141 }
142 return mipi_dt;
143 }
144
145 /* Get sensor by enabled media link */
get_remote_sensor(struct v4l2_subdev * sd)146 static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
147 {
148 struct media_pad *local, *remote;
149 struct media_entity *sensor_me;
150 struct v4l2_subdev *remote_sd = NULL;
151
152 local = &sd->entity.pads[0];
153 if (!local)
154 goto end;
155 remote = rkisp_media_entity_remote_pad(local);
156 if (!remote)
157 goto end;
158
159 //skip csi subdev
160 if (!strcmp(remote->entity->name, CSI_DEV_NAME)) {
161 local = &remote->entity->pads[CSI_SINK];
162 if (!local)
163 goto end;
164 remote = media_entity_remote_pad(local);
165 if (!remote)
166 goto end;
167 }
168
169 sensor_me = remote->entity;
170 remote_sd = media_entity_to_v4l2_subdev(sensor_me);
171 end:
172 return remote_sd;
173 }
174
sd_to_sensor(struct rkisp_device * dev,struct v4l2_subdev * sd)175 static struct rkisp_sensor_info *sd_to_sensor(struct rkisp_device *dev,
176 struct v4l2_subdev *sd)
177 {
178 int i;
179
180 for (i = 0; i < dev->num_sensors; ++i)
181 if (dev->sensors[i].sd == sd)
182 return &dev->sensors[i];
183
184 return NULL;
185 }
186
rkisp_align_sensor_resolution(struct rkisp_device * dev,struct v4l2_rect * crop,bool user)187 int rkisp_align_sensor_resolution(struct rkisp_device *dev,
188 struct v4l2_rect *crop, bool user)
189 {
190 struct v4l2_subdev *sensor = NULL;
191 struct v4l2_subdev_selection sel;
192 u32 code = dev->isp_sdev.in_frm.code;
193 u32 src_w = dev->isp_sdev.in_frm.width;
194 u32 src_h = dev->isp_sdev.in_frm.height;
195 u32 dest_w, dest_h, w, h, max_size, max_h, max_w;
196 int ret = 0;
197
198 if (!crop)
199 return -EINVAL;
200
201 memset(&sel, 0, sizeof(sel));
202 switch (dev->isp_ver) {
203 case ISP_V12:
204 max_w = CIF_ISP_INPUT_W_MAX_V12;
205 max_h = CIF_ISP_INPUT_H_MAX_V12;
206 break;
207 case ISP_V13:
208 max_w = CIF_ISP_INPUT_W_MAX_V13;
209 max_h = CIF_ISP_INPUT_H_MAX_V13;
210 break;
211 case ISP_V21:
212 max_w = CIF_ISP_INPUT_W_MAX_V21;
213 max_h = CIF_ISP_INPUT_H_MAX_V21;
214 break;
215 case ISP_V30:
216 if (dev->hw_dev->is_unite) {
217 max_w = CIF_ISP_INPUT_W_MAX_V30_UNITE;
218 max_h = CIF_ISP_INPUT_H_MAX_V30_UNITE;
219 } else {
220 max_w = CIF_ISP_INPUT_W_MAX_V30;
221 max_h = CIF_ISP_INPUT_H_MAX_V30;
222 }
223 break;
224 case ISP_V32:
225 max_w = CIF_ISP_INPUT_W_MAX_V32;
226 max_h = CIF_ISP_INPUT_H_MAX_V32;
227 break;
228 case ISP_V32_L:
229 max_w = CIF_ISP_INPUT_W_MAX_V32_L;
230 max_h = CIF_ISP_INPUT_H_MAX_V32_L;
231 break;
232 default:
233 max_w = CIF_ISP_INPUT_W_MAX;
234 max_h = CIF_ISP_INPUT_H_MAX;
235 }
236 max_size = max_w * max_h;
237 w = clamp_t(u32, src_w, CIF_ISP_INPUT_W_MIN, max_w);
238 max_h = max_size / w;
239 h = clamp_t(u32, src_h, CIF_ISP_INPUT_H_MIN, max_h);
240
241 if (dev->active_sensor)
242 sensor = dev->active_sensor->sd;
243 if (sensor) {
244 /* crop info from sensor */
245 sel.pad = 0;
246 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
247 sel.target = V4L2_SEL_TGT_CROP;
248 /* crop by sensor, isp don't input crop */
249 ret = v4l2_subdev_call(sensor, pad, get_selection, NULL, &sel);
250 if (!ret && !user) {
251 crop->left = 0;
252 crop->top = 0;
253 crop->width = clamp_t(u32, sel.r.width,
254 CIF_ISP_INPUT_W_MIN, w);
255 crop->height = clamp_t(u32, sel.r.height,
256 CIF_ISP_INPUT_H_MIN, h);
257 return 0;
258 }
259
260 if (ret) {
261 sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
262 /* only crop bounds, want to isp to do input crop */
263 ret = v4l2_subdev_call(sensor, pad, get_selection, NULL, &sel);
264 if (!ret) {
265 crop->left = ALIGN(sel.r.left, 2);
266 crop->width = ALIGN(sel.r.width, 2);
267
268 crop->left = clamp_t(u32, crop->left, 0, w);
269 crop->top = clamp_t(u32, sel.r.top, 0, h);
270 crop->width = clamp_t(u32, crop->width,
271 CIF_ISP_INPUT_W_MIN, w - crop->left);
272 crop->height = clamp_t(u32, sel.r.height,
273 CIF_ISP_INPUT_H_MIN, h - crop->top);
274 return 0;
275 }
276 }
277 }
278
279 /* crop from user */
280 if (user) {
281 crop->left = clamp_t(u32, crop->left, 0, w);
282 crop->top = clamp_t(u32, crop->top, 0, h);
283 crop->width = clamp_t(u32, crop->width,
284 CIF_ISP_INPUT_W_MIN, w - crop->left);
285 crop->height = clamp_t(u32, crop->height,
286 CIF_ISP_INPUT_H_MIN, h - crop->top);
287 if ((code & RKISP_MEDIA_BUS_FMT_MASK) == RKISP_MEDIA_BUS_FMT_BAYER &&
288 (ALIGN_DOWN(crop->width, 16) != crop->width ||
289 ALIGN_DOWN(crop->height, 8) != crop->height))
290 v4l2_warn(&dev->v4l2_dev,
291 "Note: bayer raw need width 16 align, height 8 align!\n"
292 "suggest (%d,%d)/%dx%d, specical requirements, Ignore!\n",
293 ALIGN_DOWN(crop->left, 4), crop->top,
294 ALIGN_DOWN(crop->width, 16), ALIGN_DOWN(crop->height, 8));
295 return 0;
296 }
297
298 /* yuv format */
299 if ((code & RKISP_MEDIA_BUS_FMT_MASK) != RKISP_MEDIA_BUS_FMT_BAYER) {
300 crop->left = 0;
301 crop->top = 0;
302 crop->width = min_t(u32, src_w, CIF_ISP_INPUT_W_MAX);
303 crop->height = min_t(u32, src_h, CIF_ISP_INPUT_H_MAX);
304 return 0;
305 }
306
307 /* bayer raw processed by isp need:
308 * width 16 align
309 * height 8 align
310 * width and height no exceeding the max limit
311 */
312 dest_w = ALIGN_DOWN(w, 16);
313 dest_h = ALIGN_DOWN(h, 8);
314
315 /* try to center of crop
316 *4 align to no change bayer raw format
317 */
318 crop->left = ALIGN_DOWN((src_w - dest_w) >> 1, 4);
319 crop->top = (src_h - dest_h) >> 1;
320 crop->width = dest_w;
321 crop->height = dest_h;
322 return 0;
323 }
324
rkisp_media_entity_remote_pad(struct media_pad * pad)325 struct media_pad *rkisp_media_entity_remote_pad(struct media_pad *pad)
326 {
327 struct media_link *link;
328
329 list_for_each_entry(link, &pad->entity->links, list) {
330 if (!(link->flags & MEDIA_LNK_FL_ENABLED) ||
331 !strcmp(link->source->entity->name,
332 DMARX0_VDEV_NAME) ||
333 !strcmp(link->source->entity->name,
334 DMARX1_VDEV_NAME) ||
335 !strcmp(link->source->entity->name,
336 DMARX2_VDEV_NAME))
337 continue;
338 if (link->source == pad)
339 return link->sink;
340 if (link->sink == pad)
341 return link->source;
342 }
343
344 return NULL;
345 }
346
rkisp_update_sensor_info(struct rkisp_device * dev)347 int rkisp_update_sensor_info(struct rkisp_device *dev)
348 {
349 struct v4l2_subdev *sd = &dev->isp_sdev.sd;
350 struct rkisp_sensor_info *sensor;
351 struct v4l2_subdev *sensor_sd;
352 struct v4l2_subdev_format *fmt;
353 int i, ret = 0;
354
355 sensor_sd = get_remote_sensor(sd);
356 if (!sensor_sd)
357 return -ENODEV;
358
359 sensor = sd_to_sensor(dev, sensor_sd);
360 if (!sensor)
361 return -ENODEV;
362 ret = v4l2_subdev_call(sensor->sd, pad, get_mbus_config,
363 0, &sensor->mbus);
364 if (ret && ret != -ENOIOCTLCMD)
365 return ret;
366
367 sensor->fmt[0].pad = 0;
368 sensor->fmt[0].which = V4L2_SUBDEV_FORMAT_ACTIVE;
369 ret = v4l2_subdev_call(sensor->sd, pad, get_fmt,
370 &sensor->cfg, &sensor->fmt[0]);
371 if (ret && ret != -ENOIOCTLCMD)
372 return ret;
373
374 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY &&
375 dev->isp_ver < ISP_V30) {
376 u8 vc = 0;
377
378 sensor_sd = get_remote_sensor(sensor->sd);
379 if (!sensor_sd)
380 return -ENODEV;
381 memset(dev->csi_dev.mipi_di, 0, sizeof(dev->csi_dev.mipi_di));
382 for (i = 0; i < dev->csi_dev.max_pad - 1; i++) {
383 struct rkmodule_channel_info ch = { 0 };
384
385 fmt = &sensor->fmt[i];
386 ch.index = i;
387 ret = v4l2_subdev_call(sensor_sd, core, ioctl,
388 RKMODULE_GET_CHANNEL_INFO, &ch);
389 if (ret) {
390 if (i)
391 *fmt = sensor->fmt[0];
392 } else {
393 fmt->format.width = ch.width;
394 fmt->format.height = ch.height;
395 fmt->format.code = ch.bus_fmt;
396 }
397 ret = mbus_pixelcode_to_mipi_dt(fmt->format.code);
398 if (ret < 0) {
399 v4l2_err(&dev->v4l2_dev,
400 "Invalid mipi data type\n");
401 return ret;
402 }
403
404 switch (ch.vc) {
405 case V4L2_MBUS_CSI2_CHANNEL_3:
406 vc = 3;
407 break;
408 case V4L2_MBUS_CSI2_CHANNEL_2:
409 vc = 2;
410 break;
411 case V4L2_MBUS_CSI2_CHANNEL_1:
412 vc = 1;
413 break;
414 case V4L2_MBUS_CSI2_CHANNEL_0:
415 default:
416 vc = 0;
417 }
418 dev->csi_dev.mipi_di[i] = CIF_MIPI_DATA_SEL_DT(ret) |
419 CIF_MIPI_DATA_SEL_VC(vc);
420 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
421 "CSI ch%d vc:%d dt:0x%x %dx%d\n",
422 i, vc, ret,
423 fmt->format.width,
424 fmt->format.height);
425 }
426 }
427
428 v4l2_subdev_call(sensor->sd, video, g_frame_interval, &sensor->fi);
429 dev->active_sensor = sensor;
430 i = dev->dev_id;
431 if (sensor->fi.interval.numerator)
432 dev->hw_dev->isp_size[i].fps =
433 sensor->fi.interval.denominator / sensor->fi.interval.numerator;
434 return ret;
435 }
436
rkisp_mbus_pixelcode_to_v4l2(u32 pixelcode)437 u32 rkisp_mbus_pixelcode_to_v4l2(u32 pixelcode)
438 {
439 u32 pixelformat;
440
441 switch (pixelcode) {
442 case MEDIA_BUS_FMT_Y8_1X8:
443 pixelformat = V4L2_PIX_FMT_GREY;
444 break;
445 case MEDIA_BUS_FMT_SBGGR8_1X8:
446 pixelformat = V4L2_PIX_FMT_SBGGR8;
447 break;
448 case MEDIA_BUS_FMT_SGBRG8_1X8:
449 pixelformat = V4L2_PIX_FMT_SGBRG8;
450 break;
451 case MEDIA_BUS_FMT_SGRBG8_1X8:
452 pixelformat = V4L2_PIX_FMT_SGRBG8;
453 break;
454 case MEDIA_BUS_FMT_SRGGB8_1X8:
455 pixelformat = V4L2_PIX_FMT_SRGGB8;
456 break;
457 case MEDIA_BUS_FMT_Y10_1X10:
458 pixelformat = V4L2_PIX_FMT_Y10;
459 break;
460 case MEDIA_BUS_FMT_SBGGR10_1X10:
461 pixelformat = V4L2_PIX_FMT_SBGGR10;
462 break;
463 case MEDIA_BUS_FMT_SGBRG10_1X10:
464 pixelformat = V4L2_PIX_FMT_SGBRG10;
465 break;
466 case MEDIA_BUS_FMT_SGRBG10_1X10:
467 pixelformat = V4L2_PIX_FMT_SGRBG10;
468 break;
469 case MEDIA_BUS_FMT_SRGGB10_1X10:
470 pixelformat = V4L2_PIX_FMT_SRGGB10;
471 break;
472 case MEDIA_BUS_FMT_Y12_1X12:
473 pixelformat = V4L2_PIX_FMT_Y12;
474 break;
475 case MEDIA_BUS_FMT_SBGGR12_1X12:
476 pixelformat = V4L2_PIX_FMT_SBGGR12;
477 break;
478 case MEDIA_BUS_FMT_SGBRG12_1X12:
479 pixelformat = V4L2_PIX_FMT_SGBRG12;
480 break;
481 case MEDIA_BUS_FMT_SGRBG12_1X12:
482 pixelformat = V4L2_PIX_FMT_SGRBG12;
483 break;
484 case MEDIA_BUS_FMT_SRGGB12_1X12:
485 pixelformat = V4L2_PIX_FMT_SRGGB12;
486 break;
487 case MEDIA_BUS_FMT_EBD_1X8:
488 pixelformat = V4l2_PIX_FMT_EBD8;
489 break;
490 case MEDIA_BUS_FMT_SPD_2X8:
491 pixelformat = V4l2_PIX_FMT_SPD16;
492 break;
493 default:
494 pixelformat = V4L2_PIX_FMT_SRGGB10;
495 }
496
497 return pixelformat;
498 }
499
rkisp_dvfs(struct rkisp_device * dev)500 static void rkisp_dvfs(struct rkisp_device *dev)
501 {
502 struct rkisp_hw_dev *hw = dev->hw_dev;
503 u64 data_rate = 0;
504 int i, fps, num = 0;
505
506 if (!hw->is_dvfs)
507 return;
508 hw->is_dvfs = false;
509 for (i = 0; i < hw->dev_num; i++) {
510 if (!hw->isp_size[i].is_on)
511 continue;
512 fps = hw->isp_size[i].fps;
513 if (!fps)
514 fps = 30;
515 data_rate += (fps * hw->isp_size[i].size);
516 num++;
517 }
518 do_div(data_rate, 1000 * 1000);
519 /* increase margin: 25% * num */
520 data_rate += (data_rate >> 2) * num;
521
522 /* compare with isp clock adjustment table */
523 for (i = 0; i < hw->num_clk_rate_tbl; i++)
524 if (data_rate <= hw->clk_rate_tbl[i].clk_rate)
525 break;
526 if (i == hw->num_clk_rate_tbl)
527 i--;
528
529 /* set isp clock rate */
530 rkisp_set_clk_rate(hw->clks[0], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
531 if (hw->is_unite)
532 rkisp_set_clk_rate(hw->clks[5], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
533 /* aclk equal to core clk */
534 if (dev->isp_ver == ISP_V32)
535 rkisp_set_clk_rate(hw->clks[1], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
536 dev_info(hw->dev, "set isp clk = %luHz\n", clk_get_rate(hw->clks[0]));
537 }
538
rkisp_multi_overflow_hdl(struct rkisp_device * dev,bool on)539 static void rkisp_multi_overflow_hdl(struct rkisp_device *dev, bool on)
540 {
541 struct rkisp_hw_dev *hw = dev->hw_dev;
542
543 if (on) {
544 /* enable bay3d and mi */
545 rkisp_update_regs(dev, ISP3X_MI_WR_CTRL, ISP3X_MI_WR_CTRL);
546 rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1);
547 if (dev->isp_ver == ISP_V21) {
548 rkisp_update_regs(dev, ISP21_BAY3D_CTRL, ISP21_BAY3D_CTRL);
549 } else if (dev->isp_ver == ISP_V30) {
550 rkisp_update_regs(dev, ISP3X_MPFBC_CTRL, ISP3X_MPFBC_CTRL);
551 rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL);
552 rkisp_update_regs(dev, ISP3X_BAY3D_CTRL, ISP3X_BAY3D_CTRL);
553 rkisp_update_regs(dev, ISP3X_SWS_CFG, ISP3X_SWS_CFG);
554 } else if (dev->isp_ver == ISP_V32) {
555 rkisp_update_regs(dev, ISP3X_MI_BP_WR_CTRL, ISP3X_MI_BP_WR_CTRL);
556 rkisp_update_regs(dev, ISP32_MI_BPDS_WR_CTRL, ISP32_MI_BPDS_WR_CTRL);
557 rkisp_update_regs(dev, ISP32_MI_MPDS_WR_CTRL, ISP32_MI_MPDS_WR_CTRL);
558 rkisp_update_regs(dev, ISP3X_BAY3D_CTRL, ISP3X_BAY3D_CTRL);
559 }
560 } else {
561 /* disabled bay3d and mi. rv1106 sdmmc workaround, 3a_wr no close */
562 writel(CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN,
563 hw->base_addr + ISP3X_MI_WR_CTRL);
564 if (dev->isp_ver == ISP_V21) {
565 writel(0, hw->base_addr + ISP21_BAY3D_CTRL);
566 } else if (dev->isp_ver == ISP_V30) {
567 writel(0, hw->base_addr + ISP3X_MPFBC_CTRL);
568 writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL);
569 writel(0, hw->base_addr + ISP3X_BAY3D_CTRL);
570 writel(0xc, hw->base_addr + ISP3X_SWS_CFG);
571 if (hw->is_unite) {
572 writel(0, hw->base_next_addr + ISP3X_MI_WR_CTRL);
573 writel(0, hw->base_next_addr + ISP3X_MPFBC_CTRL);
574 writel(0, hw->base_next_addr + ISP3X_MI_BP_WR_CTRL);
575 writel(0, hw->base_next_addr + ISP3X_BAY3D_CTRL);
576 writel(0xc, hw->base_next_addr + ISP3X_SWS_CFG);
577 }
578 } else if (dev->isp_ver == ISP_V32) {
579 writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL);
580 writel(0, hw->base_addr + ISP32_MI_BPDS_WR_CTRL);
581 writel(0, hw->base_addr + ISP32_MI_MPDS_WR_CTRL);
582 writel(0, hw->base_addr + ISP3X_BAY3D_CTRL);
583 }
584 }
585 rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite);
586 }
587
588 /*
589 * for hdr read back mode, rawrd read back data
590 * this will update rawrd base addr to shadow.
591 */
rkisp_trigger_read_back(struct rkisp_device * dev,u8 dma2frm,u32 mode,bool is_try)592 void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, bool is_try)
593 {
594 struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
595 struct rkisp_isp_stats_vdev *stats_vdev = &dev->stats_vdev;
596 struct rkisp_hw_dev *hw = dev->hw_dev;
597 u32 val, cur_frame_id, tmp, rd_mode;
598 u64 iq_feature = hw->iq_feature;
599 bool is_feature_on = hw->is_feature_on;
600 bool is_upd = false, is_3dlut_upd = false;
601
602 hw->cur_dev_id = dev->dev_id;
603 rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
604
605 if (hw->is_multi_overflow && is_try)
606 goto run_next;
607
608 val = 0;
609 if (mode & (T_START_X1 | T_START_C)) {
610 rd_mode = HDR_RDBK_FRAME1;
611 } else if (mode & T_START_X2) {
612 rd_mode = HDR_RDBK_FRAME2;
613 val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
614 } else if (mode & T_START_X3) {
615 rd_mode = HDR_RDBK_FRAME3;
616 val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX3;
617 } else {
618 rd_mode = dev->rd_mode;
619 val = rkisp_read(dev, ISP_HDRMGE_BASE, false) & 0xf;
620 }
621
622 if (mode & T_START_C)
623 rkisp_expander_config(dev, NULL, true);
624 else
625 rkisp_expander_config(dev, NULL, false);
626
627 if (is_feature_on) {
628 if ((ISP2X_MODULE_HDRMGE & ~iq_feature) && (val & SW_HDRMGE_EN)) {
629 v4l2_err(&dev->v4l2_dev, "hdrmge is not supported\n");
630 return;
631 }
632 }
633
634 if (rd_mode != dev->rd_mode) {
635 rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK,
636 val, false, hw->is_unite);
637 dev->skip_frame = 2;
638 is_upd = true;
639 }
640
641 if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL && !is_try) {
642 if (dev->rd_mode != rd_mode && dev->br_dev.en) {
643 tmp = dev->isp_sdev.in_crop.height;
644 val = rkisp_read(dev, CIF_DUAL_CROP_CTRL, false);
645 if (rd_mode == HDR_RDBK_FRAME1) {
646 val |= CIF_DUAL_CROP_MP_MODE_YUV;
647 tmp += RKMODULE_EXTEND_LINE;
648 } else {
649 val &= ~CIF_DUAL_CROP_MP_MODE_YUV;
650 }
651 rkisp_write(dev, CIF_DUAL_CROP_CTRL, val, false);
652 rkisp_write(dev, CIF_ISP_ACQ_V_SIZE, tmp, false);
653 rkisp_write(dev, CIF_ISP_OUT_V_SIZE, tmp, false);
654 }
655 dev->rd_mode = rd_mode;
656 rkisp_rawrd_set_pic_size(dev,
657 dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2].out_fmt.width,
658 dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2].out_fmt.height);
659 }
660 dev->rd_mode = rd_mode;
661
662 rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
663 dev->isp_sdev.quantization);
664 rkisp_params_cfg(params_vdev, cur_frame_id);
665 rkisp_config_cmsk(dev);
666 rkisp_stream_frame_start(dev, 0);
667 if (!hw->is_single && !is_try) {
668 /* multi sensor need to reset isp resize mode if scale up */
669 val = 0;
670 if (rkisp_read(dev, ISP3X_MAIN_RESIZE_CTRL, true) & 0xf0)
671 val |= BIT(3);
672 if (dev->isp_ver != ISP_V32_L &&
673 rkisp_read(dev, ISP3X_SELF_RESIZE_CTRL, true) & 0xf0)
674 val |= BIT(4);
675 if (rkisp_read(dev, ISP32_BP_RESIZE_CTRL, true) & 0xf0)
676 val |= BIT(12);
677 if (val) {
678 writel(val, hw->base_addr + CIF_IRCL);
679 writel(0, hw->base_addr + CIF_IRCL);
680 }
681
682 rkisp_update_regs(dev, CTRL_VI_ISP_PATH, SUPER_IMP_COLOR_CR);
683 rkisp_update_regs(dev, DUAL_CROP_M_H_OFFS, ISP3X_DUAL_CROP_FBC_V_SIZE);
684 rkisp_update_regs(dev, ISP_ACQ_H_OFFS, DUAL_CROP_CTRL);
685 rkisp_update_regs(dev, SELF_RESIZE_SCALE_HY, MI_WR_CTRL);
686 rkisp_update_regs(dev, ISP32_BP_RESIZE_SCALE_HY, SELF_RESIZE_CTRL);
687 rkisp_update_regs(dev, MAIN_RESIZE_SCALE_HY, ISP32_BP_RESIZE_CTRL);
688 rkisp_update_regs(dev, ISP_GAMMA_OUT_CTRL, MAIN_RESIZE_CTRL);
689 rkisp_update_regs(dev, MI_RD_CTRL2, ISP_LSC_CTRL);
690 rkisp_update_regs(dev, MI_MP_WR_Y_BASE, MI_WR_CTRL2 - 4);
691 rkisp_update_regs(dev, ISP_LSC_XGRAD_01, ISP_RAWAWB_RAM_DATA);
692 if (dev->isp_ver == ISP_V20 &&
693 (rkisp_read(dev, ISP_DHAZ_CTRL, false) & ISP_DHAZ_ENMUX ||
694 rkisp_read(dev, ISP_HDRTMO_CTRL, false) & ISP_HDRTMO_EN)) {
695 dma2frm += (dma2frm ? 0 : 1);
696 } else if (dev->isp_ver == ISP_V21) {
697 val = rkisp_read(dev, MI_WR_CTRL2, false);
698 rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, true);
699 rkisp_write(dev, MI_WR_INIT, ISP21_SP_FORCE_UPD | ISP21_MP_FORCE_UPD, true);
700 } else {
701 if (dev->isp_ver == ISP_V32_L)
702 rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
703 rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite);
704 }
705 /* sensor mode & index */
706 if (dev->isp_ver >= ISP_V21) {
707 val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
708 val |= ISP21_SENSOR_INDEX(dev->multi_index);
709 if (dev->isp_ver == ISP_V32_L)
710 val |= ISP32L_SENSOR_MODE(dev->multi_mode);
711 else
712 val |= ISP21_SENSOR_MODE(dev->multi_mode);
713 writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
714 if (hw->is_unite)
715 writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS);
716 v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
717 "sensor mode:%d index:%d | 0x%x\n",
718 dev->multi_mode, dev->multi_index, val);
719 }
720 is_upd = true;
721 }
722
723 if (dev->isp_ver > ISP_V20)
724 dma2frm = 0;
725 if (dma2frm > 2)
726 dma2frm = 2;
727 if (dma2frm == 2)
728 dev->rdbk_cnt_x3++;
729 else if (dma2frm == 1 || dev->sw_rd_cnt)
730 dev->rdbk_cnt_x2++;
731 else
732 dev->rdbk_cnt_x1++;
733 dev->rdbk_cnt++;
734
735 rkisp_params_cfgsram(params_vdev);
736 params_vdev->rdbk_times = dma2frm + 1;
737
738 run_next:
739 if (hw->is_multi_overflow && !dev->is_first_double) {
740 stats_vdev->rdbk_drop = false;
741 if (dev->sw_rd_cnt) {
742 rkisp_multi_overflow_hdl(dev, false);
743 params_vdev->rdbk_times += dev->sw_rd_cnt;
744 stats_vdev->rdbk_drop = true;
745 is_upd = true;
746 } else if (is_try) {
747 rkisp_multi_overflow_hdl(dev, true);
748 rkisp_update_regs(dev, ISP_LDCH_BASE, ISP_LDCH_BASE);
749 is_upd = true;
750 }
751 }
752
753 /* read 3d lut at frame end */
754 if (hw->is_single && is_upd &&
755 rkisp_read_reg_cache(dev, ISP_3DLUT_UPDATE) & 0x1) {
756 rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true, hw->is_unite);
757 is_3dlut_upd = true;
758 }
759 if (is_upd) {
760 val = rkisp_read(dev, ISP_CTRL, false);
761 val |= CIF_ISP_CTRL_ISP_CFG_UPD;
762 rkisp_unite_write(dev, ISP_CTRL, val, true, hw->is_unite);
763 /* bayer pat after ISP_CFG_UPD for multi sensor to read lsc r/g/b table */
764 rkisp_update_regs(dev, ISP_ACQ_PROP, ISP_ACQ_PROP);
765 /* fix ldch multi sensor case:
766 * ldch will pre-read data when en and isp force upd or frame end,
767 * udelay for ldch pre-read data.
768 * ldch en=0 before start for frame end to stop ldch read data.
769 */
770 val = rkisp_read(dev, ISP_LDCH_BASE, true);
771 if (!hw->is_single && val & BIT(0)) {
772 udelay(50);
773 val &= ~(BIT(0) | BIT(31));
774 writel(val, hw->base_addr + ISP_LDCH_BASE);
775 if (hw->is_unite)
776 writel(val, hw->base_next_addr + ISP_LDCH_BASE);
777 }
778 }
779 if (is_3dlut_upd)
780 rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true, hw->is_unite);
781
782 /* if output stream enable, wait it end */
783 val = rkisp_read(dev, CIF_MI_CTRL_SHD, true);
784 if (val & CIF_MI_CTRL_SHD_MP_OUT_ENABLED)
785 dev->irq_ends_mask |= ISP_FRAME_MP;
786 else
787 dev->irq_ends_mask &= ~ISP_FRAME_MP;
788 if (val & CIF_MI_CTRL_SHD_SP_OUT_ENABLED)
789 dev->irq_ends_mask |= ISP_FRAME_SP;
790 else
791 dev->irq_ends_mask &= ~ISP_FRAME_SP;
792 if ((dev->isp_ver == ISP_V20 &&
793 rkisp_read(dev, ISP_MPFBC_CTRL, true) & SW_MPFBC_EN) ||
794 (dev->isp_ver == ISP_V30 &&
795 rkisp_read(dev, ISP3X_MPFBC_CTRL, true) & ISP3X_MPFBC_EN_SHD))
796 dev->irq_ends_mask |= ISP_FRAME_MPFBC;
797 else
798 dev->irq_ends_mask &= ~ISP_FRAME_MPFBC;
799 if ((dev->isp_ver == ISP_V30 &&
800 rkisp_read(dev, ISP3X_MI_BP_WR_CTRL, true) & ISP3X_BP_ENABLE) ||
801 (dev->isp_ver == ISP_V32 &&
802 rkisp_read(dev, ISP32_MI_WR_CTRL2_SHD, true) & ISP32_BP_EN_OUT_SHD))
803 dev->irq_ends_mask |= ISP_FRAME_BP;
804 else
805 dev->irq_ends_mask &= ~ISP_FRAME_BP;
806
807 val = rkisp_read(dev, CSI2RX_CTRL0, true);
808 val &= ~SW_IBUF_OP_MODE(0xf);
809 tmp = SW_IBUF_OP_MODE(dev->rd_mode);
810 val |= tmp | SW_CSI2RX_EN | SW_DMA_2FRM_MODE(dma2frm);
811 v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
812 "readback frame:%d time:%d 0x%x\n",
813 cur_frame_id, dma2frm + 1, val);
814 if (!hw->is_shutdown)
815 rkisp_unite_write(dev, CSI2RX_CTRL0, val, true, hw->is_unite);
816 }
817
rkisp_fast_switch_rx_buf(struct rkisp_device * dev,bool is_current)818 static void rkisp_fast_switch_rx_buf(struct rkisp_device *dev, bool is_current)
819 {
820 struct rkisp_stream *stream;
821 struct rkisp_buffer *buf;
822 u32 i, val;
823
824 for (i = RKISP_STREAM_RAWRD0; i < RKISP_MAX_DMARX_STREAM; i++) {
825 stream = &dev->dmarx_dev.stream[i];
826 if (!stream->ops)
827 continue;
828 buf = NULL;
829 if (is_current)
830 buf = stream->curr_buf;
831 else if (!list_empty(&stream->buf_queue))
832 buf = list_first_entry(&stream->buf_queue,
833 struct rkisp_buffer, queue);
834 if (!buf)
835 continue;
836 val = buf->buff_addr[RKISP_PLANE_Y];
837 /* f1 -> f0 -> f1 for normal
838 * L:f1 L:f1 -> L:f0 S:f0 -> L:f1 S:f1 for hdr2
839 */
840 if (dev->rd_mode == HDR_RDBK_FRAME2 && !is_current &&
841 rkisp_read_reg_cache(dev, ISP3X_HDRMGE_GAIN0) == 0xfff0040) {
842 if (i == RKISP_STREAM_RAWRD2)
843 continue;
844 else
845 rkisp_write(dev, ISP3X_MI_RAWS_RD_BASE, val, false);
846 }
847 rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
848 }
849 }
850
rkisp_rdbk_trigger_handle(struct rkisp_device * dev,u32 cmd)851 static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
852 {
853 struct rkisp_hw_dev *hw = dev->hw_dev;
854 struct rkisp_device *isp = NULL;
855 struct isp2x_csi_trigger t = { 0 };
856 unsigned long lock_flags = 0;
857 int i, times = -1, max = 0, id = 0;
858 int len[DEV_MAX] = { 0 };
859 u32 mode = 0;
860 bool is_try = false;
861
862 spin_lock_irqsave(&hw->rdbk_lock, lock_flags);
863 if (cmd == T_CMD_END) {
864 if (dev->sw_rd_cnt) {
865 dev->sw_rd_cnt--;
866 isp = dev;
867 is_try = true;
868 times = 0;
869 goto end;
870 }
871 hw->is_idle = true;
872 hw->pre_dev_id = dev->dev_id;
873 }
874 if (hw->is_shutdown)
875 hw->is_idle = false;
876 if (!hw->is_idle)
877 goto end;
878 if (hw->monitor.state & ISP_MIPI_ERROR && hw->monitor.is_en)
879 goto end;
880 if (!IS_HDR_RDBK(dev->rd_mode))
881 goto end;
882
883 for (i = 0; i < hw->dev_num; i++) {
884 isp = hw->isp[i];
885 if (!isp ||
886 (isp && !(isp->isp_state & ISP_START)))
887 continue;
888 rkisp_rdbk_trigger_event(isp, T_CMD_LEN, &len[i]);
889 if (max < len[i]) {
890 max = len[i];
891 id = i;
892 }
893 }
894
895 /* wait 2 frame to start isp for fast */
896 if (dev->is_pre_on && max == 1 && !atomic_read(&dev->isp_sdev.frm_sync_seq))
897 goto end;
898
899 if (max) {
900 isp = hw->isp[id];
901 v4l2_dbg(2, rkisp_debug, &isp->v4l2_dev,
902 "trigger fifo len:%d\n", max);
903 rkisp_rdbk_trigger_event(isp, T_CMD_DEQUEUE, &t);
904 isp->dmarx_dev.pre_frame = isp->dmarx_dev.cur_frame;
905 if (t.frame_id > isp->dmarx_dev.pre_frame.id &&
906 t.frame_id - isp->dmarx_dev.pre_frame.id > 1)
907 isp->isp_sdev.dbg.frameloss +=
908 t.frame_id - isp->dmarx_dev.pre_frame.id + 1;
909 isp->dmarx_dev.cur_frame.id = t.frame_id;
910 isp->dmarx_dev.cur_frame.sof_timestamp = t.sof_timestamp;
911 isp->dmarx_dev.cur_frame.timestamp = t.frame_timestamp;
912 isp->isp_sdev.frm_timestamp = t.sof_timestamp;
913 atomic_set(&isp->isp_sdev.frm_sync_seq, t.frame_id + 1);
914 mode = t.mode;
915 times = t.times;
916 hw->cur_dev_id = id;
917 hw->is_idle = false;
918 isp->sw_rd_cnt = 0;
919 if (hw->is_multi_overflow && (hw->pre_dev_id != id)) {
920 isp->sw_rd_cnt = 1;
921 times = 0;
922 }
923 if (isp->is_pre_on && t.frame_id == 0) {
924 isp->is_first_double = true;
925 isp->skip_frame = 1;
926 isp->sw_rd_cnt = 0;
927 rkisp_fast_switch_rx_buf(isp, false);
928 }
929 }
930 end:
931 spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
932 if (times >= 0)
933 rkisp_trigger_read_back(isp, times, mode, is_try);
934 }
935
rkisp_rdbk_trigger_event(struct rkisp_device * dev,u32 cmd,void * arg)936 int rkisp_rdbk_trigger_event(struct rkisp_device *dev, u32 cmd, void *arg)
937 {
938 struct kfifo *fifo = &dev->rdbk_kfifo;
939 struct isp2x_csi_trigger *trigger = NULL;
940 unsigned long lock_flags = 0;
941 int val, ret = 0;
942
943 spin_lock_irqsave(&dev->rdbk_lock, lock_flags);
944 switch (cmd) {
945 case T_CMD_QUEUE:
946 trigger = arg;
947 if (!trigger)
948 break;
949 if (!kfifo_is_full(fifo))
950 kfifo_in(fifo, trigger, sizeof(*trigger));
951 else
952 v4l2_err(&dev->v4l2_dev, "rdbk fifo is full\n");
953 break;
954 case T_CMD_DEQUEUE:
955 if (!kfifo_is_empty(fifo))
956 ret = kfifo_out(fifo, arg, sizeof(struct isp2x_csi_trigger));
957 if (!ret)
958 ret = -EINVAL;
959 break;
960 case T_CMD_LEN:
961 val = kfifo_len(fifo) / sizeof(struct isp2x_csi_trigger);
962 *(u32 *)arg = val;
963 break;
964 default:
965 break;
966 }
967 spin_unlock_irqrestore(&dev->rdbk_lock, lock_flags);
968
969 if (cmd == T_CMD_QUEUE || cmd == T_CMD_END)
970 rkisp_rdbk_trigger_handle(dev, cmd);
971 return ret;
972 }
973
rkisp_rdbk_work(struct work_struct * work)974 static void rkisp_rdbk_work(struct work_struct *work)
975 {
976 struct rkisp_device *dev = container_of(work, struct rkisp_device, rdbk_work);
977
978 rkisp_dvfs(dev);
979 rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL);
980 }
981
rkisp_check_idle(struct rkisp_device * dev,u32 irq)982 void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
983 {
984 u32 val = 0;
985
986 if (dev->hw_dev->is_multi_overflow &&
987 dev->sw_rd_cnt &&
988 irq & ISP_FRAME_END &&
989 !dev->is_first_double)
990 goto end;
991
992 dev->irq_ends |= (irq & dev->irq_ends_mask);
993 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
994 "%s irq:0x%x ends:0x%x mask:0x%x\n",
995 __func__, irq, dev->irq_ends, dev->irq_ends_mask);
996 if (dev->irq_ends == dev->irq_ends_mask && dev->hw_dev->monitor.is_en) {
997 dev->hw_dev->monitor.retry = 0;
998 dev->hw_dev->monitor.state |= ISP_FRAME_END;
999 if (!completion_done(&dev->hw_dev->monitor.cmpl))
1000 complete(&dev->hw_dev->monitor.cmpl);
1001 }
1002 if ((dev->irq_ends & dev->irq_ends_mask) != dev->irq_ends_mask ||
1003 !IS_HDR_RDBK(dev->rd_mode))
1004 return;
1005
1006 if (dev->is_first_double) {
1007 rkisp_fast_switch_rx_buf(dev, true);
1008 dev->skip_frame = 0;
1009 dev->irq_ends = 0;
1010 return;
1011 }
1012
1013 /* check output stream is off */
1014 val = ISP_FRAME_MP | ISP_FRAME_SP | ISP_FRAME_MPFBC | ISP_FRAME_BP;
1015 if (!(dev->irq_ends_mask & val)) {
1016 u32 state = dev->isp_state;
1017 struct rkisp_stream *s;
1018
1019 for (val = 0; val < RKISP_STREAM_VIR; val++) {
1020 s = &dev->cap_dev.stream[val];
1021 dev->isp_state = ISP_STOP;
1022 if (s->streaming) {
1023 dev->isp_state = state;
1024 break;
1025 }
1026 }
1027 }
1028
1029 val = 0;
1030 switch (dev->rd_mode) {
1031 case HDR_RDBK_FRAME3://for rd1 rd0 rd2
1032 val |= RAW1_RD_FRAME;
1033 /* FALLTHROUGH */
1034 case HDR_RDBK_FRAME2://for rd0 rd2
1035 val |= RAW0_RD_FRAME;
1036 /* FALLTHROUGH */
1037 default:// for rd2
1038 val |= RAW2_RD_FRAME;
1039 /* FALLTHROUGH */
1040 }
1041 rkisp2_rawrd_isr(val, dev);
1042
1043 end:
1044 dev->irq_ends = 0;
1045 if (dev->hw_dev->is_dvfs)
1046 schedule_work(&dev->rdbk_work);
1047 else
1048 rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL);
1049 if (dev->isp_state == ISP_STOP)
1050 wake_up(&dev->sync_onoff);
1051 }
1052
rkisp_set_state(u32 * state,u32 val)1053 static void rkisp_set_state(u32 *state, u32 val)
1054 {
1055 u32 mask = 0xff;
1056
1057 if (val < ISP_STOP)
1058 mask = 0xff00;
1059 *state &= mask;
1060 *state |= val;
1061 }
1062
1063 /*
1064 * Image Stabilization.
1065 * This should only be called when configuring CIF
1066 * or at the frame end interrupt
1067 */
rkisp_config_ism(struct rkisp_device * dev)1068 static void rkisp_config_ism(struct rkisp_device *dev)
1069 {
1070 struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop;
1071 u32 width = out_crop->width, mult = 1;
1072 bool is_unite = dev->hw_dev->is_unite;
1073
1074 /* isp2.0 no ism */
1075 if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 ||
1076 dev->isp_ver == ISP_V32_L)
1077 return;
1078
1079 if (is_unite)
1080 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1081 rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false, is_unite);
1082 rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false, is_unite);
1083 rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false, is_unite);
1084 rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false, is_unite);
1085 rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false, is_unite);
1086 rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false, is_unite);
1087 rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false, is_unite);
1088 if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced)
1089 mult = 2;
1090 rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult,
1091 false, is_unite);
1092
1093 if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)
1094 return;
1095
1096 /* IS(Image Stabilization) is always on, working as output crop */
1097 rkisp_write(dev, CIF_ISP_IS_CTRL, 1, false);
1098 }
1099
rkisp_reset_handle_v2x(struct rkisp_device * dev)1100 static int rkisp_reset_handle_v2x(struct rkisp_device *dev)
1101 {
1102 void __iomem *base = dev->base_addr;
1103 void *reg_buf = NULL;
1104 u32 *reg, *reg1, i;
1105 struct backup_reg backup[] = {
1106 {
1107 .base = MI_MP_WR_Y_BASE,
1108 .shd = MI_MP_WR_Y_BASE_SHD,
1109 }, {
1110 .base = MI_MP_WR_CB_BASE,
1111 .shd = MI_MP_WR_CB_BASE_SHD,
1112 }, {
1113 .base = MI_MP_WR_CR_BASE,
1114 .shd = MI_MP_WR_CR_BASE_SHD,
1115 }, {
1116 .base = MI_SP_WR_Y_BASE,
1117 .shd = MI_SP_WR_Y_BASE_SHD,
1118 }, {
1119 .base = MI_SP_WR_CB_BASE,
1120 .shd = MI_SP_WR_CB_BASE_AD_SHD,
1121 }, {
1122 .base = MI_SP_WR_CR_BASE,
1123 .shd = MI_SP_WR_CR_BASE_AD_SHD,
1124 }, {
1125 .base = MI_RAW0_WR_BASE,
1126 .shd = MI_RAW0_WR_BASE_SHD,
1127 }, {
1128 .base = MI_RAW1_WR_BASE,
1129 .shd = MI_RAW1_WR_BASE_SHD,
1130 }, {
1131 .base = MI_RAW2_WR_BASE,
1132 .shd = MI_RAW2_WR_BASE_SHD,
1133 }, {
1134 .base = MI_RAW3_WR_BASE,
1135 .shd = MI_RAW3_WR_BASE_SHD,
1136 }, {
1137 .base = MI_RAW0_RD_BASE,
1138 .shd = MI_RAW0_RD_BASE_SHD,
1139 }, {
1140 .base = MI_RAW1_RD_BASE,
1141 .shd = MI_RAW1_RD_BASE_SHD,
1142 }, {
1143 .base = MI_RAW2_RD_BASE,
1144 .shd = MI_RAW2_RD_BASE_SHD,
1145 }, {
1146 .base = MI_GAIN_WR_BASE,
1147 .shd = MI_GAIN_WR_BASE_SHD,
1148 }
1149 };
1150
1151 reg_buf = kzalloc(RKISP_ISP_SW_REG_SIZE, GFP_KERNEL);
1152 if (!reg_buf)
1153 return -ENOMEM;
1154
1155 dev_info(dev->dev, "%s enter\n", __func__);
1156
1157 memcpy_fromio(reg_buf, base, RKISP_ISP_SW_REG_SIZE);
1158 rkisp_soft_reset(dev->hw_dev, true);
1159
1160 /* process special reg */
1161 reg = reg_buf + ISP_CTRL;
1162 *reg &= ~(CIF_ISP_CTRL_ISP_ENABLE |
1163 CIF_ISP_CTRL_ISP_INFORM_ENABLE |
1164 CIF_ISP_CTRL_ISP_CFG_UPD);
1165 reg = reg_buf + MI_WR_INIT;
1166 *reg = 0;
1167 reg = reg_buf + CSI2RX_CTRL0;
1168 *reg &= ~SW_CSI2RX_EN;
1169 /* skip mmu range */
1170 memcpy_toio(base, reg_buf, ISP21_MI_BAY3D_RD_BASE_SHD);
1171 memcpy_toio(base + CSI2RX_CTRL0, reg_buf + CSI2RX_CTRL0,
1172 RKISP_ISP_SW_REG_SIZE - CSI2RX_CTRL0);
1173 /* config shd_reg to base_reg */
1174 for (i = 0; i < ARRAY_SIZE(backup); i++) {
1175 reg = reg_buf + backup[i].base;
1176 reg1 = reg_buf + backup[i].shd;
1177 backup[i].val = *reg;
1178 writel(*reg1, base + backup[i].base);
1179 }
1180
1181 /* clear state */
1182 dev->isp_err_cnt = 0;
1183 dev->isp_state &= ~ISP_ERROR;
1184 rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
1185 dev->hw_dev->monitor.state = ISP_FRAME_END;
1186
1187 /* update module */
1188 reg = reg_buf + DUAL_CROP_CTRL;
1189 if (*reg & 0xf)
1190 writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
1191 reg = reg_buf + SELF_RESIZE_CTRL;
1192 if (*reg & 0xf)
1193 writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + SELF_RESIZE_CTRL);
1194 reg = reg_buf + MAIN_RESIZE_CTRL;
1195 if (*reg & 0xf)
1196 writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
1197
1198 /* update mi and isp, base_reg will update to shd_reg */
1199 force_cfg_update(dev);
1200 reg = reg_buf + ISP_CTRL;
1201 *reg |= CIF_ISP_CTRL_ISP_ENABLE |
1202 CIF_ISP_CTRL_ISP_INFORM_ENABLE |
1203 CIF_ISP_CTRL_ISP_CFG_UPD;
1204 writel(*reg, base + ISP_CTRL);
1205 udelay(50);
1206 /* config base_reg */
1207 for (i = 0; i < ARRAY_SIZE(backup); i++)
1208 writel(backup[i].val, base + backup[i].base);
1209 /* mpfbc base_reg = shd_reg, write is base but read is shd */
1210 if (dev->isp_ver == ISP_V20)
1211 writel(rkisp_read_reg_cache(dev, ISP_MPFBC_HEAD_PTR),
1212 base + ISP_MPFBC_HEAD_PTR);
1213 rkisp_set_bits(dev, CIF_ISP_IMSC, 0, CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR, true);
1214 if (IS_HDR_RDBK(dev->hdr.op_mode)) {
1215 if (!dev->hw_dev->is_idle)
1216 rkisp_trigger_read_back(dev, 1, 0, true);
1217 else
1218 rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, NULL);
1219 }
1220 kfree(reg_buf);
1221 dev_info(dev->dev, "%s exit\n", __func__);
1222 return 0;
1223 }
1224
rkisp_restart_monitor(struct work_struct * work)1225 static void rkisp_restart_monitor(struct work_struct *work)
1226 {
1227 struct rkisp_monitor *monitor =
1228 container_of(work, struct rkisp_monitor, work);
1229 struct rkisp_hw_dev *hw = monitor->dev;
1230 struct rkisp_device *isp;
1231 struct rkisp_pipeline *p;
1232 int ret, i, j, timeout = 5, mipi_irq_cnt = 0;
1233
1234 if (!monitor->reset_handle) {
1235 monitor->is_en = false;
1236 return;
1237 }
1238
1239 dev_info(hw->dev, "%s enter\n", __func__);
1240 while (!(monitor->state & ISP_STOP) && monitor->is_en) {
1241 ret = wait_for_completion_timeout(&monitor->cmpl,
1242 msecs_to_jiffies(100));
1243 /* isp stop to exit
1244 * isp err to reset
1245 * mipi err wait isp idle, then reset
1246 */
1247 if (monitor->state & ISP_STOP ||
1248 (ret && !(monitor->state & ISP_ERROR)) ||
1249 (!ret &&
1250 monitor->state & ISP_FRAME_END &&
1251 !(monitor->state & ISP_MIPI_ERROR))) {
1252 for (i = 0; i < hw->dev_num; i++) {
1253 isp = hw->isp[i];
1254 if (!isp || (isp && !(isp->isp_inp & INP_CSI)))
1255 continue;
1256 if (!(isp->isp_state & ISP_START))
1257 break;
1258 if (isp->csi_dev.irq_cnt != mipi_irq_cnt) {
1259 mipi_irq_cnt = isp->csi_dev.irq_cnt;
1260 timeout = 5;
1261 } else if (mipi_irq_cnt && timeout-- == 0) {
1262 /* mipi no input */
1263 monitor->state |= ISP_MIPI_ERROR;
1264 }
1265 }
1266 continue;
1267 }
1268 dev_info(hw->dev, "isp%d to restart state:0x%x try:%d mipi_irq_cnt:%d\n",
1269 hw->cur_dev_id, monitor->state, monitor->retry, mipi_irq_cnt);
1270 if (monitor->retry++ > RKISP_MAX_RETRY_CNT || hw->is_shutdown) {
1271 monitor->is_en = false;
1272 break;
1273 }
1274 for (i = 0; i < hw->dev_num; i++) {
1275 isp = hw->isp[i];
1276 if (!isp)
1277 continue;
1278 if (isp->isp_inp & INP_CSI ||
1279 isp->isp_inp & INP_DVP ||
1280 isp->isp_inp & INP_LVDS) {
1281 if (!(isp->isp_state & ISP_START))
1282 break;
1283 /* subdev stream off */
1284 p = &isp->pipe;
1285 for (j = p->num_subdevs - 1; j >= 0; j--)
1286 v4l2_subdev_call(p->subdevs[j], video, s_stream, 0);
1287 for (i = 0; i < ISP2X_MIPI_RAW_MAX; i++) {
1288 isp->luma_vdev.ystat_isrcnt[i] = 0;
1289 isp->luma_vdev.ystat_rdflg[i] = 0;
1290 }
1291 }
1292 }
1293
1294 /* restart isp */
1295 isp = hw->isp[hw->cur_dev_id];
1296 ret = monitor->reset_handle(isp);
1297 if (ret) {
1298 monitor->is_en = false;
1299 break;
1300 }
1301
1302 for (i = 0; i < hw->dev_num; i++) {
1303 isp = hw->isp[i];
1304 if (!isp)
1305 continue;
1306 if (isp->isp_inp & INP_CSI ||
1307 isp->isp_inp & INP_DVP ||
1308 isp->isp_inp & INP_LVDS) {
1309 if (!(isp->isp_state & ISP_START))
1310 break;
1311 if (isp->isp_inp & INP_CSI) {
1312 rkisp_write(isp, CSI2RX_MASK_PHY, 0xF0FFFF, true);
1313 rkisp_write(isp, CSI2RX_MASK_PACKET, 0xF1FFFFF, true);
1314 rkisp_write(isp, CSI2RX_MASK_OVERFLOW, 0x7F7FF1, true);
1315 }
1316 /* subdev stream on */
1317 isp->csi_dev.err_cnt = 0;
1318 isp->isp_state &= ~ISP_MIPI_ERROR;
1319 p = &isp->pipe;
1320 for (j = 0; j < p->num_subdevs; j++)
1321 v4l2_subdev_call(p->subdevs[j], video, s_stream, 1);
1322 }
1323 }
1324 }
1325 dev_dbg(hw->dev, "%s exit\n", __func__);
1326 }
1327
rkisp_monitor_init(struct rkisp_device * dev)1328 static void rkisp_monitor_init(struct rkisp_device *dev)
1329 {
1330 struct rkisp_monitor *monitor = &dev->hw_dev->monitor;
1331
1332 monitor->dev = dev->hw_dev;
1333 monitor->reset_handle = NULL;
1334 if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21)
1335 monitor->reset_handle = rkisp_reset_handle_v2x;
1336
1337 init_completion(&monitor->cmpl);
1338 INIT_WORK(&monitor->work, rkisp_restart_monitor);
1339 }
1340
1341 /*
1342 * RGB to YUV color space, default BT601
1343 * BT601:
1344 * Y = 0.299R + 0.587G + 0.114B
1345 * CB = -0.1687R - 0.3313G + 0.5B
1346 * CR = 0.5R - 0.4187G - 0.0813B
1347 * BT709:
1348 * Y = 0.2126R + 0.7152G + 0.0722B
1349 * CB = -0.1146R - 0.3854G + 0.5B
1350 * CR = 0.5R - 0.4542G - 0.0458B
1351 * BT2020:
1352 * Y = 0.2627R + 0.678G + 0.0593B
1353 * CB = -0.1396R - 0.3604G + 0.5B
1354 * CR = 0.5R - 0.4598G - 0.0402B
1355 * 9 bit coeffs are signed integer values with 7 bit fractional
1356 */
rkisp_config_color_space(struct rkisp_device * dev)1357 static void rkisp_config_color_space(struct rkisp_device *dev)
1358 {
1359 u32 val = 0;
1360
1361 u16 bt601_coeff[] = {
1362 0x0026, 0x004b, 0x000f,
1363 0x01ea, 0x01d6, 0x0040,
1364 0x0040, 0x01ca, 0x01f6
1365 };
1366 u16 bt709_coeff[] = {
1367 0x001b, 0x005c, 0x0009,
1368 0x01f1, 0x01cf, 0x0040,
1369 0x0040, 0x01c6, 0x01fa
1370 };
1371 u16 bt2020_coeff[] = {
1372 0x0022, 0x0057, 0x0008,
1373 0x01ee, 0x01d2, 0x0040,
1374 0x0040, 0x01c5, 0x01fb
1375 };
1376 u16 i, *coeff;
1377
1378 switch (dev->isp_sdev.colorspace) {
1379 case V4L2_COLORSPACE_REC709:
1380 coeff = bt709_coeff;
1381 break;
1382 case V4L2_COLORSPACE_BT2020:
1383 coeff = bt2020_coeff;
1384 break;
1385 case V4L2_COLORSPACE_SMPTE170M:
1386 default:
1387 coeff = bt601_coeff;
1388 break;
1389 }
1390
1391 for (i = 0; i < 9; i++)
1392 rkisp_unite_write(dev, CIF_ISP_CC_COEFF_0 + i * 4,
1393 *(coeff + i), false, dev->hw_dev->is_unite);
1394
1395 val = rkisp_read_reg_cache(dev, CIF_ISP_CTRL);
1396
1397 if (dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
1398 rkisp_unite_write(dev, CIF_ISP_CTRL, val |
1399 CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
1400 CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA,
1401 false, dev->hw_dev->is_unite);
1402 else
1403 rkisp_unite_write(dev, CIF_ISP_CTRL, val &
1404 ~(CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
1405 CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA),
1406 false, dev->hw_dev->is_unite);
1407 }
1408
rkisp_config_cmsk_single(struct rkisp_device * dev,struct rkisp_cmsk_cfg * cfg)1409 static void rkisp_config_cmsk_single(struct rkisp_device *dev,
1410 struct rkisp_cmsk_cfg *cfg)
1411 {
1412 u32 i, val, ctrl = 0;
1413 u32 mp_en = cfg->win[0].win_en;
1414 u32 sp_en = cfg->win[1].win_en;
1415 u32 bp_en = cfg->win[2].win_en;
1416 u32 win_max = (dev->isp_ver == ISP_V30) ?
1417 RKISP_CMSK_WIN_MAX_V30 : RKISP_CMSK_WIN_MAX;
1418
1419 if (mp_en) {
1420 ctrl |= ISP3X_SW_CMSK_EN_MP;
1421 rkisp_write(dev, ISP3X_CMSK_CTRL1, mp_en, false);
1422 val = cfg->win[0].mode;
1423 rkisp_write(dev, ISP3X_CMSK_CTRL4, val, false);
1424 }
1425
1426 if (sp_en) {
1427 ctrl |= ISP3X_SW_CMSK_EN_SP;
1428 rkisp_write(dev, ISP3X_CMSK_CTRL2, sp_en, false);
1429 val = cfg->win[1].mode;
1430 rkisp_write(dev, ISP3X_CMSK_CTRL5, val, false);
1431 }
1432
1433 if (bp_en) {
1434 ctrl |= ISP3X_SW_CMSK_EN_BP;
1435 rkisp_write(dev, ISP3X_CMSK_CTRL3, bp_en, false);
1436 val = cfg->win[2].mode;
1437 rkisp_write(dev, ISP3X_CMSK_CTRL6, val, false);
1438 }
1439
1440 for (i = 0; i < win_max; i++) {
1441 if (!(mp_en & BIT(i)) && !(sp_en & BIT(i)) && !(bp_en & BIT(i)))
1442 continue;
1443
1444 val = ISP3X_SW_CMSK_YUV(cfg->win[i].cover_color_y,
1445 cfg->win[i].cover_color_u,
1446 cfg->win[i].cover_color_v);
1447 rkisp_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
1448
1449 val = ISP_PACK_2SHORT(cfg->win[i].h_offs, cfg->win[i].v_offs);
1450 rkisp_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
1451
1452 val = ISP_PACK_2SHORT(cfg->win[i].h_size, cfg->win[i].v_size);
1453 rkisp_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
1454 }
1455
1456 if (ctrl) {
1457 val = ISP_PACK_2SHORT(dev->isp_sdev.out_crop.width,
1458 dev->isp_sdev.out_crop.height);
1459 rkisp_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
1460 ctrl |= ISP3X_SW_CMSK_EN | ISP3X_SW_CMSK_ORDER_MODE;
1461 ctrl |= ISP3X_SW_CMSK_BLKSIZE(cfg->mosaic_block);
1462 }
1463 rkisp_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
1464
1465 val = rkisp_read(dev, ISP3X_CMSK_CTRL0, true);
1466 if (dev->hw_dev->is_single &&
1467 ((val & ISP32_SW_CMSK_EN_PATH) != (val & ISP32_SW_CMSK_EN_PATH_SHD)))
1468 rkisp_write(dev, ISP3X_CMSK_CTRL0, val | ISP3X_SW_CMSK_FORCE_UPD, true);
1469 }
1470
rkisp_config_cmsk_dual(struct rkisp_device * dev,struct rkisp_cmsk_cfg * cfg)1471 static void rkisp_config_cmsk_dual(struct rkisp_device *dev,
1472 struct rkisp_cmsk_cfg *cfg)
1473 {
1474 struct rkisp_cmsk_cfg left = *cfg;
1475 struct rkisp_cmsk_cfg right = *cfg;
1476 u32 width = dev->isp_sdev.out_crop.width;
1477 u32 height = dev->isp_sdev.out_crop.height;
1478 u32 w = width / 2;
1479 u32 i, val, h_offs, h_size, ctrl;
1480 u8 mp_en = cfg->win[0].win_en;
1481 u8 sp_en = cfg->win[1].win_en;
1482 u8 bp_en = cfg->win[2].win_en;
1483 u32 win_max = (dev->isp_ver == ISP_V30) ?
1484 RKISP_CMSK_WIN_MAX_V30 : RKISP_CMSK_WIN_MAX;
1485
1486 for (i = 0; i < win_max; i++) {
1487 if (!(mp_en & BIT(i)) && !(sp_en & BIT(i)) && !(bp_en & BIT(i)))
1488 continue;
1489
1490 h_offs = cfg->win[i].h_offs;
1491 h_size = cfg->win[i].h_size;
1492 if (h_offs + h_size <= w) {
1493 /* cmsk window at left isp */
1494 right.win[0].win_en &= ~BIT(i);
1495 right.win[1].win_en &= ~BIT(i);
1496 right.win[2].win_en &= ~BIT(i);
1497 } else if (h_offs >= w) {
1498 /* cmsk window at right isp */
1499 left.win[0].win_en &= ~BIT(i);
1500 left.win[1].win_en &= ~BIT(i);
1501 left.win[2].win_en &= ~BIT(i);
1502 } else {
1503 /* cmsk window at dual isp */
1504 left.win[i].h_size = ALIGN(w - h_offs, 8);
1505
1506 right.win[i].h_offs = RKMOUDLE_UNITE_EXTEND_PIXEL;
1507 val = h_offs + h_size - w;
1508 right.win[i].h_size = ALIGN(val, 8);
1509 right.win[i].h_offs -= right.win[i].h_size - val;
1510 }
1511
1512 val = ISP3X_SW_CMSK_YUV(left.win[i].cover_color_y,
1513 left.win[i].cover_color_u,
1514 left.win[i].cover_color_v);
1515 rkisp_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
1516 rkisp_next_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
1517
1518 val = ISP_PACK_2SHORT(left.win[i].h_offs, left.win[i].v_offs);
1519 rkisp_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
1520 val = ISP_PACK_2SHORT(left.win[i].h_size, left.win[i].v_size);
1521 rkisp_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
1522
1523 val = ISP_PACK_2SHORT(right.win[i].h_offs, right.win[i].v_offs);
1524 rkisp_next_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
1525 val = ISP_PACK_2SHORT(right.win[i].h_size, right.win[i].v_size);
1526 rkisp_next_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
1527 }
1528
1529 w += RKMOUDLE_UNITE_EXTEND_PIXEL;
1530 ctrl = 0;
1531 if (left.win[0].win_en) {
1532 ctrl |= ISP3X_SW_CMSK_EN_MP;
1533 rkisp_write(dev, ISP3X_CMSK_CTRL1, left.win[0].win_en, false);
1534 val = left.win[0].mode;
1535 rkisp_write(dev, ISP3X_CMSK_CTRL4, val, false);
1536 }
1537 if (left.win[1].win_en) {
1538 ctrl |= ISP3X_SW_CMSK_EN_SP;
1539 rkisp_write(dev, ISP3X_CMSK_CTRL2, left.win[1].win_en, false);
1540 val = left.win[1].mode;
1541 rkisp_write(dev, ISP3X_CMSK_CTRL5, val, false);
1542 }
1543 if (left.win[2].win_en) {
1544 ctrl |= ISP3X_SW_CMSK_EN_BP;
1545 rkisp_write(dev, ISP3X_CMSK_CTRL3, left.win[2].win_en, false);
1546 val = left.win[2].mode;
1547 rkisp_write(dev, ISP3X_CMSK_CTRL6, val, false);
1548 }
1549 if (ctrl) {
1550 val = ISP_PACK_2SHORT(w, height);
1551 rkisp_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
1552 ctrl |= ISP3X_SW_CMSK_EN | ISP3X_SW_CMSK_ORDER_MODE;
1553 }
1554 rkisp_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
1555
1556 ctrl = 0;
1557 if (right.win[0].win_en) {
1558 ctrl |= ISP3X_SW_CMSK_EN_MP;
1559 rkisp_next_write(dev, ISP3X_CMSK_CTRL1, right.win[0].win_en, false);
1560 val = right.win[0].mode;
1561 rkisp_next_write(dev, ISP3X_CMSK_CTRL4, val, false);
1562 }
1563 if (right.win[1].win_en) {
1564 ctrl |= ISP3X_SW_CMSK_EN_SP;
1565 rkisp_next_write(dev, ISP3X_CMSK_CTRL2, right.win[1].win_en, false);
1566 val = right.win[1].mode;
1567 rkisp_next_write(dev, ISP3X_CMSK_CTRL5, val, false);
1568 }
1569 if (right.win[2].win_en) {
1570 ctrl |= ISP3X_SW_CMSK_EN_BP;
1571 rkisp_next_write(dev, ISP3X_CMSK_CTRL3, right.win[2].win_en, false);
1572 val = right.win[2].mode;
1573 rkisp_next_write(dev, ISP3X_CMSK_CTRL6, val, false);
1574 }
1575 if (ctrl) {
1576 val = ISP_PACK_2SHORT(w, height);
1577 rkisp_next_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
1578 ctrl |= ISP3X_SW_CMSK_EN | ISP3X_SW_CMSK_ORDER_MODE;
1579 }
1580 rkisp_next_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
1581
1582 val = rkisp_next_read(dev, ISP3X_CMSK_CTRL0, true);
1583 if (dev->hw_dev->is_single &&
1584 ((val & ISP32_SW_CMSK_EN_PATH) != (val & ISP32_SW_CMSK_EN_PATH_SHD)))
1585 rkisp_next_write(dev, ISP3X_CMSK_CTRL0, val | ISP3X_SW_CMSK_FORCE_UPD, false);
1586 }
1587
rkisp_config_cmsk(struct rkisp_device * dev)1588 static void rkisp_config_cmsk(struct rkisp_device *dev)
1589 {
1590 unsigned long lock_flags = 0;
1591 struct rkisp_cmsk_cfg cfg;
1592
1593 if (dev->isp_ver != ISP_V30 && dev->isp_ver != ISP_V32)
1594 return;
1595
1596 spin_lock_irqsave(&dev->cmsk_lock, lock_flags);
1597 if (!dev->is_cmsk_upd) {
1598 spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
1599 return;
1600 }
1601 dev->is_cmsk_upd = false;
1602 cfg = dev->cmsk_cfg;
1603 spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
1604
1605 if (!dev->hw_dev->is_unite)
1606 rkisp_config_cmsk_single(dev, &cfg);
1607 else
1608 rkisp_config_cmsk_dual(dev, &cfg);
1609 }
1610
1611 /*
1612 * configure isp blocks with input format, size......
1613 */
rkisp_config_isp(struct rkisp_device * dev)1614 static int rkisp_config_isp(struct rkisp_device *dev)
1615 {
1616 struct ispsd_in_fmt *in_fmt;
1617 struct ispsd_out_fmt *out_fmt;
1618 struct v4l2_rect *in_crop;
1619 struct rkisp_sensor_info *sensor;
1620 bool is_unite = dev->hw_dev->is_unite;
1621 u32 isp_ctrl = 0;
1622 u32 irq_mask = 0;
1623 u32 signal = 0;
1624 u32 acq_mult = 0;
1625 u32 acq_prop = 0;
1626 u32 extend_line = 0;
1627 u32 width;
1628
1629 sensor = dev->active_sensor;
1630 in_fmt = &dev->isp_sdev.in_fmt;
1631 out_fmt = &dev->isp_sdev.out_fmt;
1632 in_crop = &dev->isp_sdev.in_crop;
1633 width = in_crop->width;
1634
1635 if (in_fmt->fmt_type == FMT_BAYER) {
1636 acq_mult = 1;
1637 if (out_fmt->fmt_type == FMT_BAYER) {
1638 if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
1639 isp_ctrl =
1640 CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656;
1641 else
1642 isp_ctrl =
1643 CIF_ISP_CTRL_ISP_MODE_RAW_PICT;
1644 } else {
1645 /* demosaicing bypass for grey sensor */
1646 if (in_fmt->mbus_code == MEDIA_BUS_FMT_Y8_1X8 ||
1647 in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 ||
1648 in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12) {
1649 if (dev->isp_ver >= ISP_V20)
1650 rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
1651 0, false, is_unite);
1652 else
1653 rkisp_write(dev, CIF_ISP_DEMOSAIC,
1654 CIF_ISP_DEMOSAIC_BYPASS |
1655 CIF_ISP_DEMOSAIC_TH(0xc), false);
1656 } else {
1657 if (dev->isp_ver >= ISP_V20)
1658 rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
1659 SW_DEBAYER_EN |
1660 SW_DEBAYER_FILTER_G_EN |
1661 SW_DEBAYER_FILTER_C_EN,
1662 false, is_unite);
1663 else
1664 rkisp_write(dev, CIF_ISP_DEMOSAIC,
1665 CIF_ISP_DEMOSAIC_TH(0xc), false);
1666 }
1667
1668 if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
1669 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656;
1670 else
1671 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;
1672
1673 if (dev->isp_ver == ISP_V20 &&
1674 dev->rd_mode == HDR_RDBK_FRAME1)
1675 extend_line = RKMODULE_EXTEND_LINE;
1676 }
1677
1678 if (dev->isp_inp == INP_DMARX_ISP)
1679 acq_prop = CIF_ISP_ACQ_PROP_DMA_RGB;
1680 } else if (in_fmt->fmt_type == FMT_YUV) {
1681 acq_mult = 2;
1682 if (sensor &&
1683 (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
1684 sensor->mbus.type == V4L2_MBUS_CCP2)) {
1685 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
1686 } else {
1687 if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
1688 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU656;
1689 else
1690 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
1691
1692 }
1693
1694 irq_mask |= CIF_ISP_DATA_LOSS;
1695 if (dev->isp_inp == INP_DMARX_ISP)
1696 acq_prop = CIF_ISP_ACQ_PROP_DMA_YUV;
1697 }
1698
1699 /* Set up input acquisition properties */
1700 if (sensor && (sensor->mbus.type == V4L2_MBUS_BT656 ||
1701 sensor->mbus.type == V4L2_MBUS_PARALLEL)) {
1702 if (sensor->mbus.flags &
1703 V4L2_MBUS_PCLK_SAMPLE_RISING)
1704 signal = CIF_ISP_ACQ_PROP_POS_EDGE;
1705 }
1706
1707 if (sensor && sensor->mbus.type == V4L2_MBUS_PARALLEL) {
1708 if (sensor->mbus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1709 signal |= CIF_ISP_ACQ_PROP_VSYNC_LOW;
1710
1711 if (sensor->mbus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1712 signal |= CIF_ISP_ACQ_PROP_HSYNC_LOW;
1713 }
1714
1715 if (rkisp_read_reg_cache(dev, CIF_ISP_CTRL) & ISP32_MIR_ENABLE)
1716 isp_ctrl |= ISP32_MIR_ENABLE;
1717
1718 rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false, is_unite);
1719 acq_prop |= signal | in_fmt->yuv_seq |
1720 CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) |
1721 CIF_ISP_ACQ_PROP_FIELD_SEL_ALL;
1722 rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false, is_unite);
1723 rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true, is_unite);
1724
1725 if (is_unite)
1726 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1727 /* Acquisition Size */
1728 rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left,
1729 false, is_unite);
1730 rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top,
1731 false, is_unite);
1732 rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width,
1733 false, is_unite);
1734
1735 /* ISP Out Area differ with ACQ is only FIFO, so don't crop in this */
1736 rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true, is_unite);
1737 rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true, is_unite);
1738 rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false, is_unite);
1739
1740 if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
1741 rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2,
1742 false, is_unite);
1743 rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2,
1744 false, is_unite);
1745 } else {
1746 rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line,
1747 false, is_unite);
1748 rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line,
1749 false, is_unite);
1750 }
1751
1752 /* interrupt mask */
1753 irq_mask |= CIF_ISP_FRAME | CIF_ISP_V_START | CIF_ISP_PIC_SIZE_ERROR;
1754 if (dev->isp_ver >= ISP_V20)
1755 irq_mask |= ISP2X_LSC_LUT_ERR;
1756 if (dev->is_pre_on)
1757 irq_mask |= CIF_ISP_FRAME_IN;
1758 rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true, is_unite);
1759
1760 if ((dev->isp_ver == ISP_V20 ||
1761 dev->isp_ver == ISP_V21) &&
1762 IS_HDR_RDBK(dev->hdr.op_mode)) {
1763 irq_mask = ISP2X_3A_RAWAE_BIG;
1764 rkisp_write(dev, ISP_ISP3A_IMSC, irq_mask, true);
1765 }
1766
1767 if (out_fmt->fmt_type == FMT_BAYER) {
1768 rkisp_params_disable_isp(&dev->params_vdev);
1769 } else {
1770 rkisp_config_color_space(dev);
1771 rkisp_params_first_cfg(&dev->params_vdev, in_fmt,
1772 dev->isp_sdev.quantization);
1773 }
1774 if (!dev->hw_dev->is_single && atomic_read(&dev->hw_dev->refcnt) <= 1) {
1775 rkisp_update_regs(dev, CIF_ISP_ACQ_H_OFFS, CIF_ISP_ACQ_V_SIZE);
1776 rkisp_update_regs(dev, CIF_ISP_OUT_H_SIZE, CIF_ISP_OUT_V_SIZE);
1777 }
1778
1779 rkisp_config_cmsk(dev);
1780 return 0;
1781 }
1782
rkisp_config_dvp(struct rkisp_device * dev)1783 static int rkisp_config_dvp(struct rkisp_device *dev)
1784 {
1785 struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt;
1786 void __iomem *base = dev->base_addr;
1787 u32 val, input_sel, data_width;
1788
1789 switch (in_fmt->bus_width) {
1790 case 8:
1791 input_sel = CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
1792 data_width = ISP_CIF_DATA_WIDTH_8B;
1793 break;
1794 case 10:
1795 input_sel = CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
1796 data_width = ISP_CIF_DATA_WIDTH_10B;
1797 break;
1798 case 12:
1799 input_sel = CIF_ISP_ACQ_PROP_IN_SEL_12B;
1800 data_width = ISP_CIF_DATA_WIDTH_12B;
1801 break;
1802 default:
1803 v4l2_err(&dev->v4l2_dev, "Invalid bus width\n");
1804 return -EINVAL;
1805 }
1806
1807 val = readl(base + CIF_ISP_ACQ_PROP);
1808 writel(val | input_sel, base + CIF_ISP_ACQ_PROP);
1809
1810 if (!IS_ERR(dev->hw_dev->grf) &&
1811 (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13))
1812 regmap_update_bits(dev->hw_dev->grf, GRF_VI_CON0,
1813 ISP_CIF_DATA_WIDTH_MASK, data_width);
1814 return 0;
1815 }
1816
rkisp_config_lvds(struct rkisp_device * dev)1817 static int rkisp_config_lvds(struct rkisp_device *dev)
1818 {
1819 struct rkisp_sensor_info *sensor = dev->active_sensor;
1820 struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt;
1821 struct rkmodule_lvds_cfg cfg;
1822 struct v4l2_subdev *sd = NULL;
1823 u32 ret = 0, val, lane, data;
1824
1825 sd = get_remote_sensor(sensor->sd);
1826 ret = v4l2_subdev_call(sd, core, ioctl, RKMODULE_GET_LVDS_CFG, &cfg);
1827 if (ret)
1828 goto err;
1829
1830 switch (sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) {
1831 case V4L2_MBUS_CSI2_1_LANE:
1832 lane = 1;
1833 break;
1834 case V4L2_MBUS_CSI2_2_LANE:
1835 lane = 2;
1836 break;
1837 case V4L2_MBUS_CSI2_3_LANE:
1838 lane = 3;
1839 break;
1840 case V4L2_MBUS_CSI2_4_LANE:
1841 default:
1842 lane = 4;
1843 }
1844 lane = BIT(lane) - 1;
1845
1846 switch (in_fmt->bus_width) {
1847 case 8:
1848 data = 0;
1849 break;
1850 case 10:
1851 data = 1;
1852 break;
1853 case 12:
1854 data = 2;
1855 break;
1856 default:
1857 ret = -EINVAL;
1858 goto err;
1859 }
1860
1861 val = SW_LVDS_SAV(cfg.frm_sync_code[LVDS_CODE_GRP_LINEAR].odd_sync_code.act.sav) |
1862 SW_LVDS_EAV(cfg.frm_sync_code[LVDS_CODE_GRP_LINEAR].odd_sync_code.act.eav);
1863 writel(val, dev->base_addr + LVDS_SAV_EAV_ACT);
1864 val = SW_LVDS_SAV(cfg.frm_sync_code[LVDS_CODE_GRP_LINEAR].odd_sync_code.blk.sav) |
1865 SW_LVDS_EAV(cfg.frm_sync_code[LVDS_CODE_GRP_LINEAR].odd_sync_code.blk.eav);
1866 writel(val, dev->base_addr + LVDS_SAV_EAV_BLK);
1867 val = SW_LVDS_EN | SW_LVDS_WIDTH(data) | SW_LVDS_LANE_EN(lane) | cfg.mode;
1868 writel(val, dev->base_addr + LVDS_CTRL);
1869 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1870 "lvds CTRL:0x%x ACT:0x%x BLK:0x%x\n",
1871 readl(dev->base_addr + LVDS_CTRL),
1872 readl(dev->base_addr + LVDS_SAV_EAV_ACT),
1873 readl(dev->base_addr + LVDS_SAV_EAV_BLK));
1874 return ret;
1875 err:
1876 v4l2_err(&dev->v4l2_dev, "%s error ret:%d\n", __func__, ret);
1877 return ret;
1878 }
1879
1880 /* Configure MUX */
rkisp_config_path(struct rkisp_device * dev)1881 static int rkisp_config_path(struct rkisp_device *dev)
1882 {
1883 struct rkisp_sensor_info *sensor = dev->active_sensor;
1884 int ret = 0;
1885 u32 dpcl = 0;
1886
1887 /* isp input interface selects */
1888 if ((sensor && sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) ||
1889 dev->isp_inp & (INP_RAWRD0 | INP_RAWRD1 | INP_RAWRD2 | INP_CIF)) {
1890 /* mipi sensor->isp or isp read from ddr */
1891 dpcl |= CIF_VI_DPCL_IF_SEL_MIPI;
1892 } else if (sensor &&
1893 (sensor->mbus.type == V4L2_MBUS_BT656 ||
1894 sensor->mbus.type == V4L2_MBUS_PARALLEL)) {
1895 /* dvp sensor->isp */
1896 ret = rkisp_config_dvp(dev);
1897 dpcl |= CIF_VI_DPCL_IF_SEL_PARALLEL;
1898 } else if (dev->isp_inp == INP_DMARX_ISP) {
1899 /* read from ddr, no sensor connect, debug only */
1900 dpcl |= CIF_VI_DPCL_DMA_SW_ISP;
1901 } else if (sensor && sensor->mbus.type == V4L2_MBUS_CCP2) {
1902 /* lvds sensor->isp */
1903 ret = rkisp_config_lvds(dev);
1904 dpcl |= VI_DPCL_IF_SEL_LVDS;
1905 } else {
1906 v4l2_err(&dev->v4l2_dev, "Invalid input\n");
1907 ret = -EINVAL;
1908 }
1909
1910 if (dev->isp_ver == ISP_V32)
1911 dpcl |= BIT(0);
1912
1913 rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true,
1914 dev->hw_dev->is_unite);
1915 return ret;
1916 }
1917
1918 /* Hareware configure Entry */
rkisp_config_cif(struct rkisp_device * dev)1919 static int rkisp_config_cif(struct rkisp_device *dev)
1920 {
1921 int ret = 0;
1922
1923 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1924 "%s CIF_ID:0x%x SP:%d, MP:%d\n", __func__,
1925 readl(dev->base_addr + CIF_VI_ID),
1926 dev->cap_dev.stream[RKISP_STREAM_SP].streaming,
1927 dev->cap_dev.stream[RKISP_STREAM_MP].streaming);
1928
1929 ret = rkisp_config_isp(dev);
1930 if (ret < 0)
1931 return ret;
1932 ret = rkisp_config_path(dev);
1933 if (ret < 0)
1934 return ret;
1935 rkisp_config_ism(dev);
1936
1937 return 0;
1938 }
1939
rkisp_is_need_3a(struct rkisp_device * dev)1940 static bool rkisp_is_need_3a(struct rkisp_device *dev)
1941 {
1942 struct rkisp_isp_subdev *isp_sdev = &dev->isp_sdev;
1943
1944 return isp_sdev->in_fmt.fmt_type == FMT_BAYER &&
1945 isp_sdev->out_fmt.fmt_type == FMT_YUV;
1946 }
1947
rkisp_start_3a_run(struct rkisp_device * dev)1948 static void rkisp_start_3a_run(struct rkisp_device *dev)
1949 {
1950 struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
1951 struct video_device *vdev = ¶ms_vdev->vnode.vdev;
1952 struct v4l2_event ev = {
1953 .type = CIFISP_V4L2_EVENT_STREAM_START,
1954 };
1955 int ret = 1000;
1956
1957 if (!rkisp_is_need_3a(dev) || dev->isp_ver == ISP_V20 ||
1958 !params_vdev->is_subs_evt)
1959 return;
1960
1961 v4l2_event_queue(vdev, &ev);
1962 /* rk3326/px30 require first params queued before
1963 * rkisp_params_configure_isp() called
1964 */
1965 ret = wait_event_timeout(dev->sync_onoff,
1966 params_vdev->streamon && !params_vdev->first_params,
1967 msecs_to_jiffies(ret));
1968 if (!ret)
1969 v4l2_warn(&dev->v4l2_dev,
1970 "waiting on params stream on event timeout\n");
1971 else
1972 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1973 "Waiting for 3A on use %d ms\n", 1000 - jiffies_to_msecs(ret));
1974 }
1975
rkisp_stop_3a_run(struct rkisp_device * dev)1976 static void rkisp_stop_3a_run(struct rkisp_device *dev)
1977 {
1978 struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
1979 struct video_device *vdev = ¶ms_vdev->vnode.vdev;
1980 struct v4l2_event ev = {
1981 .type = CIFISP_V4L2_EVENT_STREAM_STOP,
1982 };
1983 int ret = 1000;
1984
1985 if (!rkisp_is_need_3a(dev) || dev->isp_ver == ISP_V20 ||
1986 !params_vdev->is_subs_evt || dev->hw_dev->is_shutdown)
1987 return;
1988
1989 v4l2_event_queue(vdev, &ev);
1990 ret = wait_event_timeout(dev->sync_onoff, !params_vdev->streamon,
1991 msecs_to_jiffies(ret));
1992 if (!ret)
1993 v4l2_warn(&dev->v4l2_dev,
1994 "waiting on params stream off event timeout\n");
1995 else
1996 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1997 "Waiting for 3A off use %d ms\n", 1000 - jiffies_to_msecs(ret));
1998 }
1999
2000 /* Mess register operations to stop isp */
rkisp_isp_stop(struct rkisp_device * dev)2001 static int rkisp_isp_stop(struct rkisp_device *dev)
2002 {
2003 struct rkisp_hw_dev *hw = dev->hw_dev;
2004 void __iomem *base = dev->base_addr;
2005 unsigned long old_rate, safe_rate;
2006 u32 val;
2007 u32 i;
2008
2009 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2010 "%s refcnt:%d\n", __func__,
2011 atomic_read(&dev->hw_dev->refcnt));
2012
2013 if (atomic_read(&dev->hw_dev->refcnt) > 1)
2014 goto end;
2015 /*
2016 * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
2017 * Stop ISP(isp) ->wait for ISP isp off
2018 */
2019 /* stop and clear MI, MIPI, and ISP interrupts */
2020 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
2021 writel(0, base + CIF_ISP_CSI0_MASK1);
2022 writel(0, base + CIF_ISP_CSI0_MASK2);
2023 writel(0, base + CIF_ISP_CSI0_MASK3);
2024 readl(base + CIF_ISP_CSI0_ERR1);
2025 readl(base + CIF_ISP_CSI0_ERR2);
2026 readl(base + CIF_ISP_CSI0_ERR3);
2027 } else if (dev->isp_ver >= ISP_V20) {
2028 writel(0, base + CSI2RX_MASK_PHY);
2029 writel(0, base + CSI2RX_MASK_PACKET);
2030 writel(0, base + CSI2RX_MASK_OVERFLOW);
2031 writel(0, base + CSI2RX_MASK_STAT);
2032 readl(base + CSI2RX_ERR_PHY);
2033 readl(base + CSI2RX_ERR_PACKET);
2034 readl(base + CSI2RX_ERR_OVERFLOW);
2035 readl(base + CSI2RX_ERR_STAT);
2036 } else {
2037 writel(0, base + CIF_MIPI_IMSC);
2038 writel(~0, base + CIF_MIPI_ICR);
2039 }
2040
2041 writel(0, base + CIF_ISP_IMSC);
2042 writel(~0, base + CIF_ISP_ICR);
2043
2044 if (dev->isp_ver >= ISP_V20) {
2045 writel(0, base + ISP_ISP3A_IMSC);
2046 writel(~0, base + ISP_ISP3A_ICR);
2047 }
2048
2049 writel(0, base + CIF_MI_IMSC);
2050 writel(~0, base + CIF_MI_ICR);
2051 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
2052 writel(0, base + CIF_ISP_CSI0_CTRL0);
2053 } else if (dev->isp_ver < ISP_V12) {
2054 val = readl(base + CIF_MIPI_CTRL);
2055 val = val & (~CIF_MIPI_CTRL_SHUTDOWNLANES(0xf));
2056 writel(val & (~CIF_MIPI_CTRL_OUTPUT_ENA), base + CIF_MIPI_CTRL);
2057 udelay(20);
2058 }
2059 /* stop lsc to avoid lsclut error */
2060 if (dev->isp_ver >= ISP_V20)
2061 writel(0, base + ISP_LSC_CTRL);
2062 /* stop ISP */
2063 val = readl(base + CIF_ISP_CTRL);
2064 val &= ~(CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_ENABLE);
2065 writel(val, base + CIF_ISP_CTRL);
2066
2067 val = readl(base + CIF_ISP_CTRL);
2068 writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL);
2069 if (hw->is_unite)
2070 rkisp_next_write(dev, CIF_ISP_CTRL,
2071 val | CIF_ISP_CTRL_ISP_CFG_UPD, true);
2072
2073 readx_poll_timeout_atomic(readl, base + CIF_ISP_RIS,
2074 val, val & CIF_ISP_OFF, 20, 100);
2075 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2076 "MI_CTRL:%x, ISP_CTRL:%x\n",
2077 readl(base + CIF_MI_CTRL), readl(base + CIF_ISP_CTRL));
2078
2079 if (!in_interrupt()) {
2080 /* normal case */
2081 /* check the isp_clk before isp reset operation */
2082 old_rate = clk_get_rate(hw->clks[0]);
2083 safe_rate = hw->clk_rate_tbl[0].clk_rate * 1000000UL;
2084 if (old_rate > safe_rate) {
2085 rkisp_set_clk_rate(hw->clks[0], safe_rate);
2086 if (hw->is_unite)
2087 rkisp_set_clk_rate(hw->clks[5], safe_rate);
2088 udelay(100);
2089 }
2090 rkisp_soft_reset(dev->hw_dev, false);
2091 }
2092
2093 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
2094 writel(0, base + CIF_ISP_CSI0_CSI2_RESETN);
2095 writel(0, base + CIF_ISP_CSI0_CTRL0);
2096 writel(0, base + CIF_ISP_CSI0_MASK1);
2097 writel(0, base + CIF_ISP_CSI0_MASK2);
2098 writel(0, base + CIF_ISP_CSI0_MASK3);
2099 } else if (dev->isp_ver >= ISP_V20) {
2100 writel(0, base + CSI2RX_CSI2_RESETN);
2101 if (hw->is_unite)
2102 rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true);
2103 }
2104
2105 hw->is_dvfs = false;
2106 hw->is_runing = false;
2107 dev->hw_dev->is_idle = true;
2108 dev->hw_dev->is_mi_update = false;
2109 end:
2110 dev->irq_ends_mask = 0;
2111 dev->hdr.op_mode = 0;
2112 dev->sw_rd_cnt = 0;
2113 dev->stats_vdev.rdbk_drop = false;
2114 rkisp_set_state(&dev->isp_state, ISP_STOP);
2115
2116 if (dev->isp_ver >= ISP_V20)
2117 kfifo_reset(&dev->rdbk_kfifo);
2118 if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)
2119 memset(&dev->cmsk_cfg, 0, sizeof(dev->cmsk_cfg));
2120 if (dev->emd_vc <= CIF_ISP_ADD_DATA_VC_MAX) {
2121 for (i = 0; i < RKISP_EMDDATA_FIFO_MAX; i++)
2122 kfifo_free(&dev->emd_data_fifo[i].mipi_kfifo);
2123 dev->emd_vc = 0xFF;
2124 }
2125
2126 if (dev->hdr.sensor)
2127 dev->hdr.sensor = NULL;
2128
2129 return 0;
2130 }
2131
2132 /* Mess register operations to start isp */
rkisp_isp_start(struct rkisp_device * dev)2133 static int rkisp_isp_start(struct rkisp_device *dev)
2134 {
2135 struct rkisp_sensor_info *sensor = dev->active_sensor;
2136 void __iomem *base = dev->base_addr;
2137 bool is_direct = true;
2138 u32 val;
2139
2140 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2141 "%s refcnt:%d link_num:%d\n", __func__,
2142 atomic_read(&dev->hw_dev->refcnt),
2143 dev->hw_dev->dev_link_num);
2144
2145 dev->cap_dev.is_done_early = false;
2146 if (dev->cap_dev.wait_line >= dev->isp_sdev.out_crop.height)
2147 dev->cap_dev.wait_line = 0;
2148 if (dev->cap_dev.wait_line) {
2149 dev->cap_dev.is_done_early = true;
2150 if (dev->isp_ver >= ISP_V32) {
2151 val = dev->cap_dev.wait_line;
2152 rkisp_write(dev, ISP32_ISP_IRQ_CFG0, val << 16, false);
2153 rkisp_set_bits(dev, CIF_ISP_IMSC, 0, ISP3X_OUT_FRM_HALF, false);
2154 } else {
2155 /* using AF 15x15 block */
2156 val = dev->isp_sdev.out_crop.height / 15;
2157 val = dev->cap_dev.wait_line / val;
2158 val = ISP3X_RAWAF_INELINE0(val) | ISP3X_RAWAF_INTLINE0_EN;
2159 rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE,
2160 val, false, dev->hw_dev->is_unite);
2161 rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0,
2162 ISP2X_3A_RAWAF, false, dev->hw_dev->is_unite);
2163 rkisp_unite_clear_bits(dev, CIF_ISP_IMSC,
2164 ISP2X_LSC_LUT_ERR, false, dev->hw_dev->is_unite);
2165 dev->rawaf_irq_cnt = 0;
2166 }
2167 }
2168
2169 /* Activate MIPI */
2170 if (sensor && sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
2171 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
2172 /* clear interrupts state */
2173 readl(base + CIF_ISP_CSI0_ERR1);
2174 readl(base + CIF_ISP_CSI0_ERR2);
2175 readl(base + CIF_ISP_CSI0_ERR3);
2176 /* csi2host enable */
2177 writel(1, base + CIF_ISP_CSI0_CTRL0);
2178 } else if (dev->isp_ver < ISP_V12) {
2179 val = readl(base + CIF_MIPI_CTRL);
2180 writel(val | CIF_MIPI_CTRL_OUTPUT_ENA,
2181 base + CIF_MIPI_CTRL);
2182 }
2183 }
2184 /* Activate ISP */
2185 val = rkisp_read_reg_cache(dev, CIF_ISP_CTRL);
2186 val |= CIF_ISP_CTRL_ISP_CFG_UPD | CIF_ISP_CTRL_ISP_ENABLE |
2187 CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT;
2188 if (dev->isp_ver == ISP_V20)
2189 val |= NOC_HURRY_PRIORITY(2) | NOC_HURRY_W_MODE(2) | NOC_HURRY_R_MODE(1);
2190 if (atomic_read(&dev->hw_dev->refcnt) > 1)
2191 is_direct = false;
2192 rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct, dev->hw_dev->is_unite);
2193 rkisp_clear_reg_cache_bits(dev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_CFG_UPD);
2194
2195 dev->isp_err_cnt = 0;
2196 dev->isp_isr_cnt = 0;
2197 dev->irq_ends_mask |= ISP_FRAME_END;
2198 dev->irq_ends = 0;
2199
2200 /* XXX: Is the 1000us too long?
2201 * CIF spec says to wait for sufficient time after enabling
2202 * the MIPI interface and before starting the sensor output.
2203 */
2204 if (dev->hw_dev->is_single)
2205 usleep_range(1000, 1200);
2206
2207 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2208 "%s MI_CTRL 0x%08x ISP_CTRL 0x%08x\n", __func__,
2209 readl(base + CIF_MI_CTRL), readl(base + CIF_ISP_CTRL));
2210
2211 if (dev->hw_dev->monitor.is_en && atomic_read(&dev->hw_dev->refcnt) < 2) {
2212 dev->hw_dev->monitor.retry = 0;
2213 dev->hw_dev->monitor.state = ISP_FRAME_END;
2214 schedule_work(&dev->hw_dev->monitor.work);
2215 }
2216 return 0;
2217 }
2218
2219 /***************************** isp sub-devs *******************************/
2220
2221 static const struct ispsd_in_fmt rkisp_isp_input_formats[] = {
2222 {
2223 .name = "SBGGR10_1X10",
2224 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
2225 .fmt_type = FMT_BAYER,
2226 .mipi_dt = CIF_CSI2_DT_RAW10,
2227 .bayer_pat = RAW_BGGR,
2228 .bus_width = 10,
2229 }, {
2230 .name = "SRGGB10_1X10",
2231 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
2232 .fmt_type = FMT_BAYER,
2233 .mipi_dt = CIF_CSI2_DT_RAW10,
2234 .bayer_pat = RAW_RGGB,
2235 .bus_width = 10,
2236 }, {
2237 .name = "SGBRG10_1X10",
2238 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
2239 .fmt_type = FMT_BAYER,
2240 .mipi_dt = CIF_CSI2_DT_RAW10,
2241 .bayer_pat = RAW_GBRG,
2242 .bus_width = 10,
2243 }, {
2244 .name = "SGRBG10_1X10",
2245 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
2246 .fmt_type = FMT_BAYER,
2247 .mipi_dt = CIF_CSI2_DT_RAW10,
2248 .bayer_pat = RAW_GRBG,
2249 .bus_width = 10,
2250 }, {
2251 .name = "SRGGB12_1X12",
2252 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
2253 .fmt_type = FMT_BAYER,
2254 .mipi_dt = CIF_CSI2_DT_RAW12,
2255 .bayer_pat = RAW_RGGB,
2256 .bus_width = 12,
2257 }, {
2258 .name = "SBGGR12_1X12",
2259 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
2260 .fmt_type = FMT_BAYER,
2261 .mipi_dt = CIF_CSI2_DT_RAW12,
2262 .bayer_pat = RAW_BGGR,
2263 .bus_width = 12,
2264 }, {
2265 .name = "SGBRG12_1X12",
2266 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
2267 .fmt_type = FMT_BAYER,
2268 .mipi_dt = CIF_CSI2_DT_RAW12,
2269 .bayer_pat = RAW_GBRG,
2270 .bus_width = 12,
2271 }, {
2272 .name = "SGRBG12_1X12",
2273 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
2274 .fmt_type = FMT_BAYER,
2275 .mipi_dt = CIF_CSI2_DT_RAW12,
2276 .bayer_pat = RAW_GRBG,
2277 .bus_width = 12,
2278 }, {
2279 .name = "SRGGB8_1X8",
2280 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
2281 .fmt_type = FMT_BAYER,
2282 .mipi_dt = CIF_CSI2_DT_RAW8,
2283 .bayer_pat = RAW_RGGB,
2284 .bus_width = 8,
2285 }, {
2286 .name = "SBGGR8_1X8",
2287 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
2288 .fmt_type = FMT_BAYER,
2289 .mipi_dt = CIF_CSI2_DT_RAW8,
2290 .bayer_pat = RAW_BGGR,
2291 .bus_width = 8,
2292 }, {
2293 .name = "SGBRG8_1X8",
2294 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
2295 .fmt_type = FMT_BAYER,
2296 .mipi_dt = CIF_CSI2_DT_RAW8,
2297 .bayer_pat = RAW_GBRG,
2298 .bus_width = 8,
2299 }, {
2300 .name = "SGRBG8_1X8",
2301 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
2302 .fmt_type = FMT_BAYER,
2303 .mipi_dt = CIF_CSI2_DT_RAW8,
2304 .bayer_pat = RAW_GRBG,
2305 .bus_width = 8,
2306 }, {
2307 .name = "YUYV8_2X8",
2308 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
2309 .fmt_type = FMT_YUV,
2310 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2311 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2312 .bus_width = 8,
2313 }, {
2314 .name = "YVYU8_2X8",
2315 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
2316 .fmt_type = FMT_YUV,
2317 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2318 .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
2319 .bus_width = 8,
2320 }, {
2321 .name = "UYVY8_2X8",
2322 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
2323 .fmt_type = FMT_YUV,
2324 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2325 .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
2326 .bus_width = 8,
2327 }, {
2328 .name = "VYUY8_2X8",
2329 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
2330 .fmt_type = FMT_YUV,
2331 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2332 .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
2333 .bus_width = 8,
2334 }, {
2335 .name = "YUYV10_2X10",
2336 .mbus_code = MEDIA_BUS_FMT_YUYV10_2X10,
2337 .fmt_type = FMT_YUV,
2338 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2339 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2340 .bus_width = 10,
2341 }, {
2342 .name = "YVYU10_2X10",
2343 .mbus_code = MEDIA_BUS_FMT_YVYU10_2X10,
2344 .fmt_type = FMT_YUV,
2345 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2346 .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
2347 .bus_width = 10,
2348 }, {
2349 .name = "UYVY10_2X10",
2350 .mbus_code = MEDIA_BUS_FMT_UYVY10_2X10,
2351 .fmt_type = FMT_YUV,
2352 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2353 .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
2354 .bus_width = 10,
2355 }, {
2356 .name = "VYUY10_2X10",
2357 .mbus_code = MEDIA_BUS_FMT_VYUY10_2X10,
2358 .fmt_type = FMT_YUV,
2359 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2360 .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
2361 .bus_width = 10,
2362 }, {
2363 .name = "YUYV12_2X12",
2364 .mbus_code = MEDIA_BUS_FMT_YUYV12_2X12,
2365 .fmt_type = FMT_YUV,
2366 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2367 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2368 .bus_width = 12,
2369 }, {
2370 .name = "YVYU12_2X12",
2371 .mbus_code = MEDIA_BUS_FMT_YVYU12_2X12,
2372 .fmt_type = FMT_YUV,
2373 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2374 .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
2375 .bus_width = 12,
2376 }, {
2377 .name = "UYVY12_2X12",
2378 .mbus_code = MEDIA_BUS_FMT_UYVY12_2X12,
2379 .fmt_type = FMT_YUV,
2380 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2381 .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
2382 .bus_width = 12,
2383 }, {
2384 .name = "VYUY12_2X12",
2385 .mbus_code = MEDIA_BUS_FMT_VYUY12_2X12,
2386 .fmt_type = FMT_YUV,
2387 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2388 .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
2389 .bus_width = 12,
2390 }, {
2391 .name = "Y8_1X8",
2392 .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
2393 .fmt_type = FMT_BAYER,
2394 .mipi_dt = CIF_CSI2_DT_RAW8,
2395 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2396 .bus_width = 8,
2397 }, {
2398 .name = "Y10_1X8",
2399 .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
2400 .fmt_type = FMT_BAYER,
2401 .mipi_dt = CIF_CSI2_DT_RAW10,
2402 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2403 .bus_width = 10,
2404 }, {
2405 .name = "Y12_1X12",
2406 .mbus_code = MEDIA_BUS_FMT_Y12_1X12,
2407 .fmt_type = FMT_BAYER,
2408 .mipi_dt = CIF_CSI2_DT_RAW12,
2409 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2410 .bus_width = 12,
2411 }
2412 };
2413
2414 static const struct ispsd_out_fmt rkisp_isp_output_formats[] = {
2415 {
2416 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
2417 .fmt_type = FMT_YUV,
2418 }, {
2419 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
2420 .fmt_type = FMT_BAYER,
2421 }, {
2422 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
2423 .fmt_type = FMT_BAYER,
2424 }, {
2425 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
2426 .fmt_type = FMT_BAYER,
2427 }, {
2428 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
2429 .fmt_type = FMT_BAYER,
2430 }, {
2431 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
2432 .fmt_type = FMT_BAYER,
2433 }, {
2434 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
2435 .fmt_type = FMT_BAYER,
2436 }, {
2437 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
2438 .fmt_type = FMT_BAYER,
2439 }, {
2440 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
2441 .fmt_type = FMT_BAYER,
2442 }, {
2443 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
2444 .fmt_type = FMT_BAYER,
2445 }, {
2446 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
2447 .fmt_type = FMT_BAYER,
2448 }, {
2449 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
2450 .fmt_type = FMT_BAYER,
2451 }, {
2452 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
2453 .fmt_type = FMT_BAYER,
2454 },
2455 };
2456
find_in_fmt(u32 mbus_code)2457 static const struct ispsd_in_fmt *find_in_fmt(u32 mbus_code)
2458 {
2459 const struct ispsd_in_fmt *fmt;
2460 int i, array_size = ARRAY_SIZE(rkisp_isp_input_formats);
2461
2462 for (i = 0; i < array_size; i++) {
2463 fmt = &rkisp_isp_input_formats[i];
2464 if (fmt->mbus_code == mbus_code)
2465 return fmt;
2466 }
2467
2468 return NULL;
2469 }
2470
find_out_fmt(u32 mbus_code)2471 static const struct ispsd_out_fmt *find_out_fmt(u32 mbus_code)
2472 {
2473 const struct ispsd_out_fmt *fmt;
2474 int i, array_size = ARRAY_SIZE(rkisp_isp_output_formats);
2475
2476 for (i = 0; i < array_size; i++) {
2477 fmt = &rkisp_isp_output_formats[i];
2478 if (fmt->mbus_code == mbus_code)
2479 return fmt;
2480 }
2481
2482 return NULL;
2483 }
2484
rkisp_isp_sd_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)2485 static int rkisp_isp_sd_enum_mbus_code(struct v4l2_subdev *sd,
2486 struct v4l2_subdev_pad_config *cfg,
2487 struct v4l2_subdev_mbus_code_enum *code)
2488 {
2489 unsigned int i = code->index;
2490
2491 if (code->pad == RKISP_ISP_PAD_SINK) {
2492 if (i >= ARRAY_SIZE(rkisp_isp_input_formats))
2493 return -EINVAL;
2494 code->code = rkisp_isp_input_formats[i].mbus_code;
2495 } else {
2496 if (i >= ARRAY_SIZE(rkisp_isp_output_formats))
2497 return -EINVAL;
2498 code->code = rkisp_isp_output_formats[i].mbus_code;
2499 }
2500
2501 return 0;
2502 }
2503
2504 #define sd_to_isp_sd(_sd) container_of(_sd, struct rkisp_isp_subdev, sd)
rkisp_isp_sd_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)2505 static int rkisp_isp_sd_get_fmt(struct v4l2_subdev *sd,
2506 struct v4l2_subdev_pad_config *cfg,
2507 struct v4l2_subdev_format *fmt)
2508 {
2509 struct v4l2_mbus_framefmt *mf;
2510 struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
2511
2512 if (!fmt)
2513 goto err;
2514
2515 if (fmt->pad != RKISP_ISP_PAD_SINK &&
2516 fmt->pad != RKISP_ISP_PAD_SOURCE_PATH)
2517 goto err;
2518
2519 mf = &fmt->format;
2520 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
2521 if (!cfg)
2522 goto err;
2523 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
2524 }
2525
2526 if (fmt->pad == RKISP_ISP_PAD_SINK) {
2527 *mf = isp_sd->in_frm;
2528 } else if (fmt->pad == RKISP_ISP_PAD_SOURCE_PATH) {
2529 /* format of source pad */
2530 mf->code = isp_sd->out_fmt.mbus_code;
2531 /* window size of source pad */
2532 mf->width = isp_sd->out_crop.width;
2533 mf->height = isp_sd->out_crop.height;
2534 mf->quantization = isp_sd->quantization;
2535 mf->colorspace = isp_sd->colorspace;
2536 }
2537 mf->field = V4L2_FIELD_NONE;
2538
2539 return 0;
2540 err:
2541 return -EINVAL;
2542 }
2543
rkisp_isp_sd_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)2544 static int rkisp_isp_sd_set_fmt(struct v4l2_subdev *sd,
2545 struct v4l2_subdev_pad_config *cfg,
2546 struct v4l2_subdev_format *fmt)
2547 {
2548 struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
2549 struct rkisp_isp_subdev *isp_sd = &isp_dev->isp_sdev;
2550 struct v4l2_mbus_framefmt *mf;
2551
2552 if (!fmt)
2553 goto err;
2554
2555 if (fmt->pad != RKISP_ISP_PAD_SINK &&
2556 fmt->pad != RKISP_ISP_PAD_SOURCE_PATH)
2557 goto err;
2558
2559 mf = &fmt->format;
2560 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
2561 if (!cfg)
2562 goto err;
2563 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
2564 }
2565
2566 if (fmt->pad == RKISP_ISP_PAD_SINK) {
2567 const struct ispsd_in_fmt *in_fmt;
2568
2569 in_fmt = find_in_fmt(mf->code);
2570 if (!in_fmt ||
2571 mf->width < CIF_ISP_INPUT_W_MIN ||
2572 mf->height < CIF_ISP_INPUT_H_MIN)
2573 goto err;
2574
2575 isp_sd->in_fmt = *in_fmt;
2576 isp_sd->in_frm = *mf;
2577 } else if (fmt->pad == RKISP_ISP_PAD_SOURCE_PATH) {
2578 const struct ispsd_out_fmt *out_fmt;
2579
2580 out_fmt = find_out_fmt(mf->code);
2581 if (!out_fmt)
2582 goto err;
2583 isp_sd->out_fmt = *out_fmt;
2584 /* window size is set in s_selection */
2585 mf->width = isp_sd->out_crop.width;
2586 mf->height = isp_sd->out_crop.height;
2587 /* full range by default */
2588 if (mf->quantization == V4L2_QUANTIZATION_DEFAULT)
2589 mf->quantization = V4L2_QUANTIZATION_FULL_RANGE;
2590 /* BT601 default */
2591 if (mf->colorspace != V4L2_COLORSPACE_SMPTE170M &&
2592 mf->colorspace != V4L2_COLORSPACE_REC709 &&
2593 mf->colorspace != V4L2_COLORSPACE_BT2020)
2594 mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
2595 isp_sd->quantization = mf->quantization;
2596 isp_sd->colorspace = mf->colorspace;
2597 }
2598
2599 mf->field = V4L2_FIELD_NONE;
2600 return 0;
2601 err:
2602 return -EINVAL;
2603 }
2604
rkisp_isp_sd_try_crop(struct v4l2_subdev * sd,struct v4l2_rect * crop,u32 pad)2605 static void rkisp_isp_sd_try_crop(struct v4l2_subdev *sd,
2606 struct v4l2_rect *crop,
2607 u32 pad)
2608 {
2609 struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
2610 struct rkisp_device *dev = sd_to_isp_dev(sd);
2611 struct v4l2_rect in_crop = isp_sd->in_crop;
2612
2613 crop->left = ALIGN(crop->left, 2);
2614 crop->width = ALIGN(crop->width, 2);
2615
2616 if (pad == RKISP_ISP_PAD_SINK) {
2617 /* update sensor info if sensor link be changed */
2618 rkisp_update_sensor_info(dev);
2619 rkisp_align_sensor_resolution(dev, crop, true);
2620 } else if (pad == RKISP_ISP_PAD_SOURCE_PATH) {
2621 crop->left = clamp_t(u32, crop->left, 0, in_crop.width);
2622 crop->top = clamp_t(u32, crop->top, 0, in_crop.height);
2623 crop->width = clamp_t(u32, crop->width, CIF_ISP_OUTPUT_W_MIN,
2624 in_crop.width - crop->left);
2625 crop->height = clamp_t(u32, crop->height, CIF_ISP_OUTPUT_H_MIN,
2626 in_crop.height - crop->top);
2627 }
2628 }
2629
rkisp_isp_sd_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)2630 static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd,
2631 struct v4l2_subdev_pad_config *cfg,
2632 struct v4l2_subdev_selection *sel)
2633 {
2634 struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
2635 struct rkisp_device *dev = sd_to_isp_dev(sd);
2636 struct v4l2_rect *crop;
2637 u32 max_w, max_h, max_size;
2638
2639 if (!sel)
2640 goto err;
2641 if (sel->pad != RKISP_ISP_PAD_SOURCE_PATH &&
2642 sel->pad != RKISP_ISP_PAD_SINK)
2643 goto err;
2644
2645 crop = &sel->r;
2646 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
2647 if (!cfg)
2648 goto err;
2649 crop = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
2650 }
2651
2652 *crop = isp_sd->in_crop;
2653 switch (sel->target) {
2654 case V4L2_SEL_TGT_CROP_BOUNDS:
2655 crop->left = 0;
2656 crop->top = 0;
2657 if (sel->pad == RKISP_ISP_PAD_SINK) {
2658 switch (dev->isp_ver) {
2659 case ISP_V12:
2660 max_w = CIF_ISP_INPUT_W_MAX_V12;
2661 max_h = CIF_ISP_INPUT_H_MAX_V12;
2662 break;
2663 case ISP_V13:
2664 max_w = CIF_ISP_INPUT_W_MAX_V13;
2665 max_h = CIF_ISP_INPUT_H_MAX_V13;
2666 break;
2667 case ISP_V21:
2668 max_w = CIF_ISP_INPUT_W_MAX_V21;
2669 max_h = CIF_ISP_INPUT_H_MAX_V21;
2670 break;
2671 case ISP_V30:
2672 max_w = dev->hw_dev->is_unite ?
2673 CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
2674 max_h = dev->hw_dev->is_unite ?
2675 CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
2676 break;
2677 case ISP_V32:
2678 max_w = CIF_ISP_INPUT_W_MAX_V32;
2679 max_h = CIF_ISP_INPUT_H_MAX_V32;
2680 break;
2681 case ISP_V32_L:
2682 max_w = CIF_ISP_INPUT_W_MAX_V32_L;
2683 max_h = CIF_ISP_INPUT_H_MAX_V32_L;
2684 break;
2685 default:
2686 max_w = CIF_ISP_INPUT_W_MAX;
2687 max_h = CIF_ISP_INPUT_H_MAX;
2688 }
2689 max_size = max_w * max_h;
2690 max_h = max_size / isp_sd->in_frm.width;
2691
2692 crop->width = min_t(u32, isp_sd->in_frm.width, max_w);
2693 crop->height = min_t(u32, isp_sd->in_frm.height, max_h);
2694 }
2695 break;
2696 case V4L2_SEL_TGT_CROP:
2697 if (sel->pad == RKISP_ISP_PAD_SOURCE_PATH)
2698 *crop = isp_sd->out_crop;
2699 break;
2700 default:
2701 goto err;
2702 }
2703
2704 return 0;
2705 err:
2706 return -EINVAL;
2707 }
2708
rkisp_check_stream_dcrop(struct rkisp_device * dev,struct v4l2_rect * crop)2709 static void rkisp_check_stream_dcrop(struct rkisp_device *dev,
2710 struct v4l2_rect *crop)
2711 {
2712 struct rkisp_stream *stream;
2713 struct v4l2_rect *dcrop;
2714 u32 i;
2715
2716 for (i = 0; i < RKISP_MAX_STREAM; i++) {
2717 if (i != RKISP_STREAM_MP && i != RKISP_STREAM_SP &&
2718 i != RKISP_STREAM_FBC && i != RKISP_STREAM_BP)
2719 continue;
2720 stream = &dev->cap_dev.stream[i];
2721 dcrop = &stream->dcrop;
2722 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2723 "%s id:%d %dx%d(%d %d) from %dx%d(%d %d)\n",
2724 __func__, i,
2725 dcrop->width, dcrop->height, dcrop->left, dcrop->top,
2726 crop->width, crop->height, crop->left, crop->top);
2727 /* make sure dcrop window in isp output window */
2728 if (dcrop->width > crop->width) {
2729 dcrop->width = crop->width;
2730 dcrop->left = 0;
2731 } else if ((dcrop->left + dcrop->width) > crop->width) {
2732 dcrop->left = crop->width - dcrop->width;
2733 }
2734 if (dcrop->height > crop->height) {
2735 dcrop->height = crop->height;
2736 dcrop->top = 0;
2737 } else if ((dcrop->top + dcrop->height) > crop->height) {
2738 dcrop->top = crop->height - dcrop->height;
2739 }
2740 }
2741 }
2742
rkisp_isp_sd_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)2743 static int rkisp_isp_sd_set_selection(struct v4l2_subdev *sd,
2744 struct v4l2_subdev_pad_config *cfg,
2745 struct v4l2_subdev_selection *sel)
2746 {
2747 struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
2748 struct rkisp_device *dev = sd_to_isp_dev(sd);
2749 struct v4l2_rect *crop;
2750
2751 if (!sel)
2752 goto err;
2753 if (sel->pad != RKISP_ISP_PAD_SOURCE_PATH &&
2754 sel->pad != RKISP_ISP_PAD_SINK)
2755 goto err;
2756 if (sel->target != V4L2_SEL_TGT_CROP)
2757 goto err;
2758
2759 crop = &sel->r;
2760 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
2761 if (!cfg)
2762 goto err;
2763 crop = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
2764 }
2765
2766 rkisp_isp_sd_try_crop(sd, crop, sel->pad);
2767
2768 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2769 "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__, sel->pad,
2770 crop->left, crop->top, crop->width, crop->height);
2771
2772 if (sel->pad == RKISP_ISP_PAD_SINK) {
2773 isp_sd->in_crop = *crop;
2774 /* don't have out crop */
2775 if (dev->isp_ver >= ISP_V20) {
2776 isp_sd->out_crop = *crop;
2777 isp_sd->out_crop.left = 0;
2778 isp_sd->out_crop.top = 0;
2779 dev->br_dev.crop = isp_sd->out_crop;
2780 }
2781 } else {
2782 if (dev->isp_ver >= ISP_V20)
2783 *crop = isp_sd->out_crop;
2784 isp_sd->out_crop = *crop;
2785 }
2786
2787 rkisp_check_stream_dcrop(dev, crop);
2788
2789 return 0;
2790 err:
2791 return -EINVAL;
2792 }
2793
rkisp_isp_read_add_fifo_data(struct rkisp_device * dev)2794 static void rkisp_isp_read_add_fifo_data(struct rkisp_device *dev)
2795 {
2796 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
2797 void __iomem *base = dev->base_addr;
2798 u32 mipi_status = 0;
2799 u32 data_len = 0;
2800 u32 fifo_data = 0;
2801 u32 i, idx, cur_frame_id;
2802
2803 if (dev->isp_ver != ISP_V10 &&
2804 dev->isp_ver != ISP_V10_1)
2805 return;
2806
2807 cur_frame_id = atomic_read(&dev->isp_sdev.frm_sync_seq) - 1;
2808 idx = dev->emd_data_idx;
2809 dev->emd_data_fifo[idx].frame_id = 0;
2810 kfifo_reset_out(&dev->emd_data_fifo[idx].mipi_kfifo);
2811 for (i = 0; i < CIFISP_ADD_DATA_FIFO_SIZE / 4; i++) {
2812 mipi_status = readl(base + CIF_MIPI_STATUS);
2813 if (!(mipi_status & 0x01))
2814 break;
2815
2816 fifo_data = readl(base + CIF_MIPI_ADD_DATA_FIFO);
2817 kfifo_in(&dev->emd_data_fifo[idx].mipi_kfifo,
2818 &fifo_data, sizeof(fifo_data));
2819 data_len += 4;
2820
2821 if (kfifo_is_full(&dev->emd_data_fifo[idx].mipi_kfifo))
2822 v4l2_warn(v4l2_dev, "%s: mipi_kfifo is full!\n",
2823 __func__);
2824 }
2825
2826 if (data_len) {
2827 dev->emd_data_fifo[idx].frame_id = cur_frame_id;
2828 dev->emd_data_fifo[idx].data_len = data_len;
2829 dev->emd_data_idx = (idx + 1) % RKISP_EMDDATA_FIFO_MAX;
2830 }
2831
2832 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2833 "emd kfifo size: %d, frame_id %d\n",
2834 kfifo_len(&dev->emd_data_fifo[idx].mipi_kfifo),
2835 dev->emd_data_fifo[idx].frame_id);
2836 }
2837
rkisp_global_update_mi(struct rkisp_device * dev)2838 static void rkisp_global_update_mi(struct rkisp_device *dev)
2839 {
2840 struct rkisp_stream *stream;
2841 int i;
2842
2843 rkisp_stats_first_ddr_config(&dev->stats_vdev);
2844 if (dev->hw_dev->is_mi_update)
2845 return;
2846
2847 rkisp_config_dmatx_valid_buf(dev);
2848
2849 force_cfg_update(dev);
2850
2851 hdr_update_dmatx_buf(dev);
2852 if (dev->hw_dev->is_single) {
2853 for (i = 0; i < RKISP_MAX_STREAM; i++) {
2854 stream = &dev->cap_dev.stream[i];
2855 if (stream->id == RKISP_STREAM_VIR ||
2856 stream->id == RKISP_STREAM_LUMA)
2857 continue;
2858 if (stream->streaming && !stream->curr_buf)
2859 stream->ops->frame_end(stream, FRAME_INIT);
2860 }
2861 }
2862 rkisp_stats_next_ddr_config(&dev->stats_vdev);
2863 }
2864
rkisp_isp_sd_s_stream(struct v4l2_subdev * sd,int on)2865 static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on)
2866 {
2867 struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
2868 struct rkisp_hw_dev *hw_dev = isp_dev->hw_dev;
2869
2870 if (!on) {
2871 if (IS_HDR_RDBK(isp_dev->rd_mode)) {
2872 struct rkisp_stream *s;
2873 int i;
2874
2875 for (i = RKISP_STREAM_RAWRD0; i <= RKISP_STREAM_RAWRD2; i++) {
2876 s = &isp_dev->dmarx_dev.stream[i];
2877 if (s->stopping)
2878 wake_up(&s->done);
2879 }
2880 }
2881 wait_event_timeout(isp_dev->sync_onoff,
2882 isp_dev->isp_state & ISP_STOP ||
2883 !IS_HDR_RDBK(isp_dev->rd_mode),
2884 msecs_to_jiffies(50));
2885 rkisp_isp_stop(isp_dev);
2886 atomic_dec(&hw_dev->refcnt);
2887 rkisp_params_stream_stop(&isp_dev->params_vdev);
2888 atomic_set(&isp_dev->isp_sdev.frm_sync_seq, 0);
2889 rkisp_stop_3a_run(isp_dev);
2890 return 0;
2891 }
2892
2893 hw_dev->is_runing = true;
2894 rkisp_start_3a_run(isp_dev);
2895 memset(&isp_dev->isp_sdev.dbg, 0, sizeof(isp_dev->isp_sdev.dbg));
2896 if (atomic_inc_return(&hw_dev->refcnt) > hw_dev->dev_link_num) {
2897 dev_err(isp_dev->dev, "%s fail: input link before hw start\n", __func__);
2898 atomic_dec(&hw_dev->refcnt);
2899 return -EINVAL;
2900 }
2901
2902 rkisp_config_cif(isp_dev);
2903 rkisp_isp_start(isp_dev);
2904 rkisp_global_update_mi(isp_dev);
2905 isp_dev->isp_state = ISP_START | ISP_FRAME_END;
2906 rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL);
2907 return 0;
2908 }
2909
rkisp_rx_buf_free(struct rkisp_device * dev,struct rkisp_rx_buf * dbufs)2910 static void rkisp_rx_buf_free(struct rkisp_device *dev, struct rkisp_rx_buf *dbufs)
2911 {
2912 const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
2913 struct rkisp_rx_buf_pool *pool;
2914 int i = 0;
2915
2916 if (!dbufs)
2917 return;
2918
2919 for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
2920 pool = &dev->pv_pool[i];
2921 if (dbufs == pool->dbufs) {
2922 if (pool->mem_priv) {
2923 g_ops->unmap_dmabuf(pool->mem_priv);
2924 g_ops->detach_dmabuf(pool->mem_priv);
2925 dma_buf_put(pool->dbufs->dbuf);
2926 pool->mem_priv = NULL;
2927 }
2928 pool->dbufs = NULL;
2929 break;
2930 }
2931 }
2932 }
2933
rkisp_rx_qbuf_online(struct rkisp_stream * stream,struct rkisp_rx_buf_pool * pool)2934 static void rkisp_rx_qbuf_online(struct rkisp_stream *stream,
2935 struct rkisp_rx_buf_pool *pool)
2936 {
2937 struct rkisp_device *dev = stream->ispdev;
2938 u32 val = pool->buf.buff_addr[RKISP_PLANE_Y];
2939
2940 rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
2941 if (dev->hw_dev->is_unite) {
2942 u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
2943
2944 if (stream->memory)
2945 offs *= DIV_ROUND_UP(stream->out_isp_fmt.bpp[0], 8);
2946 else
2947 offs = offs * stream->out_isp_fmt.bpp[0] / 8;
2948 val += offs;
2949 rkisp_next_write(dev, stream->config->mi.y_base_ad_init, val, false);
2950 }
2951 }
2952
rkisp_rx_qbuf_rdbk(struct rkisp_stream * stream,struct rkisp_rx_buf_pool * pool)2953 static void rkisp_rx_qbuf_rdbk(struct rkisp_stream *stream,
2954 struct rkisp_rx_buf_pool *pool)
2955 {
2956 struct rkisp_device *dev = stream->ispdev;
2957 unsigned long lock_flags = 0;
2958 struct rkisp_buffer *ispbuf = &pool->buf;
2959 struct isp2x_csi_trigger trigger = {
2960 .frame_timestamp = ispbuf->vb.vb2_buf.timestamp,
2961 .sof_timestamp = ispbuf->vb.vb2_buf.timestamp,
2962 .frame_id = ispbuf->vb.sequence,
2963 .mode = 0,
2964 .times = 0,
2965 };
2966 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
2967 if (list_empty(&stream->buf_queue) && !stream->curr_buf) {
2968 stream->curr_buf = ispbuf;
2969 stream->ops->update_mi(stream);
2970 } else {
2971 list_add_tail(&ispbuf->queue, &stream->buf_queue);
2972 }
2973 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
2974 if (stream->id == RKISP_STREAM_RAWRD2)
2975 rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, &trigger);
2976 }
2977
rkisp_rx_qbuf(struct rkisp_device * dev,struct rkisp_rx_buf * dbufs)2978 static int rkisp_rx_qbuf(struct rkisp_device *dev,
2979 struct rkisp_rx_buf *dbufs)
2980 {
2981 struct rkisp_stream *stream;
2982 struct rkisp_rx_buf_pool *pool;
2983 int i;
2984
2985 for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
2986 pool = &dev->pv_pool[i];
2987 if (dbufs == pool->dbufs)
2988 break;
2989 }
2990
2991 if (pool->dbufs == NULL || pool->dbufs != dbufs)
2992 return -EINVAL;
2993 switch (dbufs->type) {
2994 case BUF_SHORT:
2995 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
2996 break;
2997 case BUF_MIDDLE:
2998 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
2999 break;
3000 case BUF_LONG:
3001 default:
3002 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
3003 }
3004
3005 v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
3006 "%s rd_mode:%d seq:%d dma:0x%x\n",
3007 __func__, dev->rd_mode, dbufs->sequence,
3008 pool->buf.buff_addr[RKISP_PLANE_Y]);
3009
3010 if (!IS_HDR_RDBK(dev->rd_mode)) {
3011 rkisp_rx_qbuf_online(stream, pool);
3012 } else {
3013 pool->buf.vb.vb2_buf.timestamp = dbufs->timestamp;
3014 pool->buf.vb.sequence = dbufs->sequence;
3015 rkisp_rx_qbuf_rdbk(stream, pool);
3016 }
3017 return 0;
3018 }
3019
rkisp_rx_buf_pool_free(struct rkisp_device * dev)3020 void rkisp_rx_buf_pool_free(struct rkisp_device *dev)
3021 {
3022 const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
3023 struct rkisp_rx_buf_pool *pool;
3024 int i;
3025
3026 for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
3027 pool = &dev->pv_pool[i];
3028 if (!pool->dbufs)
3029 break;
3030 if (pool->mem_priv) {
3031 g_ops->unmap_dmabuf(pool->mem_priv);
3032 g_ops->detach_dmabuf(pool->mem_priv);
3033 dma_buf_put(pool->dbufs->dbuf);
3034 pool->mem_priv = NULL;
3035 }
3036 pool->dbufs = NULL;
3037 }
3038 }
3039
rkisp_rx_buf_pool_init(struct rkisp_device * dev,struct rkisp_rx_buf * dbufs)3040 static int rkisp_rx_buf_pool_init(struct rkisp_device *dev,
3041 struct rkisp_rx_buf *dbufs)
3042 {
3043 const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
3044 struct rkisp_stream *stream;
3045 struct rkisp_rx_buf_pool *pool;
3046 struct sg_table *sg_tbl;
3047 dma_addr_t dma;
3048 int i, ret;
3049 void *mem, *vaddr = NULL;
3050
3051 for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
3052 pool = &dev->pv_pool[i];
3053 if (!pool->dbufs)
3054 break;
3055 }
3056
3057 pool->dbufs = dbufs;
3058 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
3059 "%s type:0x%x dbufs[%d]:%p", __func__, dbufs->type, i, dbufs);
3060
3061 if (dbufs->is_resmem) {
3062 dma = dbufs->dma;
3063 goto end;
3064 }
3065 mem = g_ops->attach_dmabuf(dev->hw_dev->dev, dbufs->dbuf,
3066 dbufs->dbuf->size, DMA_BIDIRECTIONAL);
3067 if (IS_ERR(mem)) {
3068 ret = PTR_ERR(mem);
3069 goto err;
3070 }
3071 pool->mem_priv = mem;
3072 ret = g_ops->map_dmabuf(mem);
3073 if (ret)
3074 goto err;
3075 if (dev->hw_dev->is_dma_sg_ops) {
3076 sg_tbl = (struct sg_table *)g_ops->cookie(mem);
3077 dma = sg_dma_address(sg_tbl->sgl);
3078 } else {
3079 dma = *((dma_addr_t *)g_ops->cookie(mem));
3080 }
3081 get_dma_buf(dbufs->dbuf);
3082 vaddr = g_ops->vaddr(mem);
3083 end:
3084 dbufs->is_init = true;
3085 pool->buf.other = dbufs;
3086 pool->buf.buff_addr[RKISP_PLANE_Y] = dma;
3087 pool->buf.vaddr[RKISP_PLANE_Y] = vaddr;
3088
3089 switch (dbufs->type) {
3090 case BUF_SHORT:
3091 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
3092 break;
3093 case BUF_MIDDLE:
3094 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
3095 break;
3096 case BUF_LONG:
3097 default:
3098 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
3099 }
3100 if (dbufs->is_first) {
3101 stream->memory = 0;
3102 if (dbufs->is_uncompact)
3103 stream->memory = SW_CSI_RAW_WR_SIMG_MODE;
3104 rkisp_dmarx_set_fmt(stream, stream->out_fmt);
3105 stream->ops->config_mi(stream);
3106 dbufs->is_first = false;
3107 }
3108 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
3109 "%s dma:0x%x vaddr:%p", __func__, (u32)dma, vaddr);
3110 return 0;
3111 err:
3112 rkisp_rx_buf_pool_free(dev);
3113 return ret;
3114 }
3115
rkisp_sd_s_rx_buffer(struct v4l2_subdev * sd,void * buf,unsigned int * size)3116 static int rkisp_sd_s_rx_buffer(struct v4l2_subdev *sd,
3117 void *buf, unsigned int *size)
3118 {
3119 struct rkisp_device *dev = sd_to_isp_dev(sd);
3120 struct rkisp_rx_buf *dbufs;
3121 int ret = 0;
3122
3123 if (!buf)
3124 return -EINVAL;
3125
3126 dbufs = buf;
3127 if (!dbufs->is_init)
3128 ret = rkisp_rx_buf_pool_init(dev, dbufs);
3129 if (!ret)
3130 ret = rkisp_rx_qbuf(dev, dbufs);
3131
3132 return ret;
3133 }
3134
rkisp_isp_sd_s_power(struct v4l2_subdev * sd,int on)3135 static int rkisp_isp_sd_s_power(struct v4l2_subdev *sd, int on)
3136 {
3137 struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
3138 int ret;
3139
3140 v4l2_dbg(1, rkisp_debug, &isp_dev->v4l2_dev,
3141 "%s on:%d\n", __func__, on);
3142
3143 if (on) {
3144 if (isp_dev->isp_ver >= ISP_V20)
3145 kfifo_reset(&isp_dev->rdbk_kfifo);
3146 ret = pm_runtime_get_sync(isp_dev->dev);
3147 } else {
3148 ret = pm_runtime_put_sync(isp_dev->dev);
3149 }
3150
3151 if (ret < 0)
3152 v4l2_err(sd, "%s on:%d failed:%d\n", __func__, on, ret);
3153 return ret;
3154 }
3155
rkisp_subdev_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)3156 static int rkisp_subdev_link_setup(struct media_entity *entity,
3157 const struct media_pad *local,
3158 const struct media_pad *remote,
3159 u32 flags)
3160 {
3161 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
3162 struct rkisp_device *dev;
3163 struct rkisp_stream *stream = NULL;
3164 u8 rawrd = INP_RAWRD0 | INP_RAWRD1 | INP_RAWRD2;
3165
3166 if (local->index != RKISP_ISP_PAD_SINK &&
3167 local->index != RKISP_ISP_PAD_SOURCE_PATH)
3168 return 0;
3169 if (!sd)
3170 return -ENODEV;
3171 dev = sd_to_isp_dev(sd);
3172 if (!dev)
3173 return -ENODEV;
3174
3175 if (dev->hw_dev->is_runing &&
3176 (!dev->isp_inp ||
3177 !(dev->isp_inp & ~rawrd) ||
3178 !strcmp(remote->entity->name, CSI_DEV_NAME) ||
3179 strstr(remote->entity->name, "rkcif"))) {
3180 v4l2_err(sd, "no support link for isp hw working\n");
3181 return -EINVAL;
3182 }
3183
3184 if (!strcmp(remote->entity->name, DMA_VDEV_NAME)) {
3185 stream = &dev->dmarx_dev.stream[RKISP_STREAM_DMARX];
3186 if (flags & MEDIA_LNK_FL_ENABLED) {
3187 if (dev->isp_inp & ~INP_DMARX_ISP)
3188 goto err;
3189 dev->isp_inp = INP_DMARX_ISP;
3190 } else {
3191 if (dev->active_sensor)
3192 dev->active_sensor = NULL;
3193 dev->isp_inp = INP_INVAL;
3194 }
3195 } else if (!strcmp(remote->entity->name, CSI_DEV_NAME)) {
3196 if (flags & MEDIA_LNK_FL_ENABLED) {
3197 if (dev->isp_inp & ~(INP_CSI | INP_CIF | rawrd))
3198 goto err;
3199 dev->isp_inp |= INP_CSI;
3200 } else {
3201 if (dev->active_sensor)
3202 dev->active_sensor = NULL;
3203 dev->isp_inp &= ~INP_CSI;
3204 }
3205 } else if (!strcmp(remote->entity->name, DMARX0_VDEV_NAME)) {
3206 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
3207 if (flags & MEDIA_LNK_FL_ENABLED) {
3208 if (dev->isp_inp & ~(INP_CSI | INP_CIF | rawrd))
3209 goto err;
3210 dev->isp_inp |= INP_RAWRD0;
3211 } else {
3212 dev->isp_inp &= ~INP_RAWRD0;
3213 }
3214 } else if (!strcmp(remote->entity->name, DMARX1_VDEV_NAME)) {
3215 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
3216 if (flags & MEDIA_LNK_FL_ENABLED) {
3217 if (dev->isp_inp & ~(INP_CSI | INP_CIF | rawrd))
3218 goto err;
3219 dev->isp_inp |= INP_RAWRD1;
3220 } else {
3221 dev->isp_inp &= ~INP_RAWRD1;
3222 }
3223 } else if (!strcmp(remote->entity->name, DMARX2_VDEV_NAME)) {
3224 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
3225 if (flags & MEDIA_LNK_FL_ENABLED) {
3226 if (dev->isp_inp & ~(INP_CSI | INP_CIF | rawrd))
3227 goto err;
3228 dev->isp_inp |= INP_RAWRD2;
3229 } else {
3230 dev->isp_inp &= ~INP_RAWRD2;
3231 }
3232 } else if (!strcmp(remote->entity->name, FBC_VDEV_NAME)) {
3233 stream = &dev->cap_dev.stream[RKISP_STREAM_FBC];
3234 } else if (!strcmp(remote->entity->name, BP_VDEV_NAME)) {
3235 stream = &dev->cap_dev.stream[RKISP_STREAM_BP];
3236 } else if (!strcmp(remote->entity->name, MPDS_VDEV_NAME)) {
3237 stream = &dev->cap_dev.stream[RKISP_STREAM_MPDS];
3238 } else if (!strcmp(remote->entity->name, BPDS_VDEV_NAME)) {
3239 stream = &dev->cap_dev.stream[RKISP_STREAM_BPDS];
3240 } else if (!strcmp(remote->entity->name, LUMA_VDEV_NAME)) {
3241 stream = &dev->cap_dev.stream[RKISP_STREAM_LUMA];
3242 } else if (!strcmp(remote->entity->name, VIR_VDEV_NAME)) {
3243 stream = &dev->cap_dev.stream[RKISP_STREAM_VIR];
3244 } else if (!strcmp(remote->entity->name, SP_VDEV_NAME)) {
3245 stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
3246 } else if (!strcmp(remote->entity->name, MP_VDEV_NAME)) {
3247 stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
3248 if (flags & MEDIA_LNK_FL_ENABLED &&
3249 dev->br_dev.linked)
3250 goto err;
3251 } else if (!strcmp(remote->entity->name, BRIDGE_DEV_NAME)) {
3252 if (flags & MEDIA_LNK_FL_ENABLED &&
3253 dev->cap_dev.stream[RKISP_STREAM_MP].linked)
3254 goto err;
3255 dev->br_dev.linked = flags & MEDIA_LNK_FL_ENABLED;
3256 } else if (!strcmp(remote->entity->name, "rockchip-mipi-dphy-rx")) {
3257 if (flags & MEDIA_LNK_FL_ENABLED) {
3258 if (dev->isp_inp & ~INP_LVDS)
3259 goto err;
3260 dev->isp_inp |= INP_LVDS;
3261 } else {
3262 if (dev->active_sensor)
3263 dev->active_sensor = NULL;
3264 dev->isp_inp &= ~INP_LVDS;
3265 }
3266 } else if (strstr(remote->entity->name, "rkcif")) {
3267 if (flags & MEDIA_LNK_FL_ENABLED) {
3268 if (dev->isp_inp & ~(INP_CIF | rawrd))
3269 goto err;
3270 dev->isp_inp |= INP_CIF;
3271 } else {
3272 dev->isp_inp &= ~INP_CIF;
3273 }
3274 } else {
3275 if (flags & MEDIA_LNK_FL_ENABLED) {
3276 if (dev->isp_inp & ~INP_DVP)
3277 goto err;
3278 dev->isp_inp |= INP_DVP;
3279 } else {
3280 if (dev->active_sensor)
3281 dev->active_sensor = NULL;
3282 dev->isp_inp &= ~INP_INVAL;
3283 }
3284 }
3285
3286 if (stream)
3287 stream->linked = flags & MEDIA_LNK_FL_ENABLED;
3288 if (dev->isp_inp & rawrd) {
3289 dev->dmarx_dev.trigger = T_MANUAL;
3290 dev->is_rdbk_auto = false;
3291 } else {
3292 dev->dmarx_dev.trigger = T_AUTO;
3293 }
3294 if (dev->isp_inp & INP_CIF) {
3295 struct v4l2_subdev *remote = get_remote_sensor(sd);
3296 struct rkisp_vicap_mode mode;
3297
3298 memset(&mode, 0, sizeof(mode));
3299 mode.name = dev->name;
3300 mode.rdbk_mode = !!(dev->isp_inp & rawrd);
3301 /* read back mode only */
3302 if (dev->isp_ver < ISP_V30 || !dev->hw_dev->is_single)
3303 mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
3304 v4l2_subdev_call(remote, core, ioctl,
3305 RKISP_VICAP_CMD_MODE, &mode);
3306 dev->vicap_in = mode.input;
3307 }
3308
3309 if (!dev->isp_inp)
3310 dev->is_hw_link = false;
3311 else
3312 dev->is_hw_link = true;
3313 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
3314 "isp input:0x%x\n", dev->isp_inp);
3315 return 0;
3316 err:
3317 v4l2_err(sd, "link error %s -> %s\n"
3318 "\tcsi dvp lvds dmaread can't work together\n"
3319 "\trawrd can't work with dvp lvds dmaread\n"
3320 "\tbridge can't work with mainpath/selfpath\n",
3321 local->entity->name, remote->entity->name);
3322 return -EINVAL;
3323 }
3324
rkisp_subdev_link_validate(struct media_link * link)3325 static int rkisp_subdev_link_validate(struct media_link *link)
3326 {
3327 if (link->source->index == RKISP_ISP_PAD_SINK_PARAMS)
3328 return 0;
3329
3330 return v4l2_subdev_link_validate(link);
3331 }
3332
3333 #ifdef CONFIG_MEDIA_CONTROLLER
rkisp_subdev_fmt_link_validate(struct v4l2_subdev * sd,struct media_link * link,struct v4l2_subdev_format * source_fmt,struct v4l2_subdev_format * sink_fmt)3334 static int rkisp_subdev_fmt_link_validate(struct v4l2_subdev *sd,
3335 struct media_link *link,
3336 struct v4l2_subdev_format *source_fmt,
3337 struct v4l2_subdev_format *sink_fmt)
3338 {
3339 if (source_fmt->format.code != sink_fmt->format.code)
3340 return -EINVAL;
3341
3342 /* Crop is available */
3343 if (source_fmt->format.width < sink_fmt->format.width ||
3344 source_fmt->format.height < sink_fmt->format.height)
3345 return -EINVAL;
3346
3347 return 0;
3348 }
3349 #endif
3350
3351 void
rkisp_isp_queue_event_sof(struct rkisp_isp_subdev * isp)3352 rkisp_isp_queue_event_sof(struct rkisp_isp_subdev *isp)
3353 {
3354 struct v4l2_event event = {
3355 .type = V4L2_EVENT_FRAME_SYNC,
3356 .u.frame_sync.frame_sequence =
3357 atomic_inc_return(&isp->frm_sync_seq) - 1,
3358 };
3359
3360 v4l2_event_queue(isp->sd.devnode, &event);
3361 }
3362
rkisp_isp_sd_subs_evt(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)3363 static int rkisp_isp_sd_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh,
3364 struct v4l2_event_subscription *sub)
3365 {
3366 if (sub->type != V4L2_EVENT_FRAME_SYNC)
3367 return -EINVAL;
3368
3369 /* Line number. For now only zero accepted. */
3370 if (sub->id != 0)
3371 return -EINVAL;
3372
3373 return v4l2_event_subscribe(fh, sub, ISP_V4L2_EVENT_ELEMS, NULL);
3374 }
3375
rkisp_get_info(struct rkisp_device * dev,struct rkisp_isp_info * info)3376 static int rkisp_get_info(struct rkisp_device *dev, struct rkisp_isp_info *info)
3377 {
3378 struct v4l2_rect *in_crop = &dev->isp_sdev.in_crop;
3379 u32 rd_mode, mode = 0, bit = 0;
3380 int ret;
3381
3382 if (!(dev->isp_state & ISP_START)) {
3383 struct rkmodule_hdr_cfg cfg;
3384
3385 ret = rkisp_csi_get_hdr_cfg(dev, &cfg);
3386 if (ret)
3387 return ret;
3388 rd_mode = cfg.hdr_mode;
3389 if (rd_mode == HDR_COMPR)
3390 bit = cfg.compr.bit > 20 ? 20 : cfg.compr.bit;
3391 } else {
3392 rd_mode = dev->rd_mode;
3393 bit = dev->hdr.compr_bit;
3394 }
3395
3396 switch (rd_mode) {
3397 case HDR_RDBK_FRAME2:
3398 case HDR_FRAMEX2_DDR:
3399 case HDR_LINEX2_DDR:
3400 mode = RKISP_ISP_HDR2;
3401 break;
3402 case HDR_RDBK_FRAME3:
3403 case HDR_FRAMEX3_DDR:
3404 case HDR_LINEX3_DDR:
3405 mode = RKISP_ISP_HDR3;
3406 break;
3407 default:
3408 mode = RKISP_ISP_NORMAL;
3409 }
3410 if (bit)
3411 mode = RKISP_ISP_COMPR;
3412 info->compr_bit = bit;
3413
3414 if (dev->is_bigmode)
3415 mode |= RKISP_ISP_BIGMODE;
3416 info->mode = mode;
3417 if (dev->hw_dev->is_unite)
3418 info->act_width = in_crop->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
3419 else
3420 info->act_width = in_crop->width;
3421 info->act_height = in_crop->height;
3422 return 0;
3423 }
3424
rkisp_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)3425 static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3426 {
3427 struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
3428 struct rkisp_thunderboot_resmem *resmem;
3429 struct rkisp32_thunderboot_resmem_head *tb_head_v32;
3430 struct rkisp_thunderboot_resmem_head *head;
3431 struct rkisp_thunderboot_shmem *shmem;
3432 struct isp2x_buf_idxfd *idxfd;
3433 struct rkisp_rx_buf *dbufs;
3434 void *resmem_va;
3435 long ret = 0;
3436
3437 if (!arg &&
3438 (cmd != RKISP_CMD_FREE_SHARED_BUF &&
3439 cmd != RKISP_CMD_MULTI_DEV_FORCE_ENUM))
3440 return -EINVAL;
3441
3442 switch (cmd) {
3443 case RKISP_CMD_TRIGGER_READ_BACK:
3444 rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, arg);
3445 break;
3446 case RKISP_CMD_GET_ISP_INFO:
3447 rkisp_get_info(isp_dev, arg);
3448 break;
3449 case RKISP_CMD_GET_TB_HEAD_V32:
3450 if (isp_dev->tb_head.complete != RKISP_TB_OK || !isp_dev->is_pre_on) {
3451 ret = -EINVAL;
3452 break;
3453 }
3454 tb_head_v32 = arg;
3455 memcpy(tb_head_v32, &isp_dev->tb_head,
3456 sizeof(struct rkisp_thunderboot_resmem_head));
3457 memcpy(&tb_head_v32->cfg, isp_dev->params_vdev.isp32_params,
3458 sizeof(struct isp32_isp_params_cfg));
3459 break;
3460 case RKISP_CMD_GET_SHARED_BUF:
3461 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
3462 ret = -ENOIOCTLCMD;
3463 break;
3464 }
3465 resmem = (struct rkisp_thunderboot_resmem *)arg;
3466 resmem->resmem_padr = isp_dev->resmem_pa;
3467 resmem->resmem_size = isp_dev->resmem_size;
3468 if (!isp_dev->resmem_pa || !isp_dev->resmem_size) {
3469 v4l2_info(sd, "no reserved memory for thunderboot\n");
3470 break;
3471 }
3472
3473 rkisp_chk_tb_over(isp_dev);
3474 dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr,
3475 sizeof(struct rkisp_thunderboot_resmem_head),
3476 DMA_FROM_DEVICE);
3477
3478 resmem_va = phys_to_virt(isp_dev->resmem_pa);
3479 head = (struct rkisp_thunderboot_resmem_head *)resmem_va;
3480 if (head->complete != RKISP_TB_OK) {
3481 resmem->resmem_size = 0;
3482 dma_unmap_single(isp_dev->dev, isp_dev->resmem_pa,
3483 sizeof(struct rkisp_thunderboot_resmem_head),
3484 DMA_FROM_DEVICE);
3485 free_reserved_area(phys_to_virt(isp_dev->resmem_pa),
3486 phys_to_virt(isp_dev->resmem_pa) + isp_dev->resmem_size,
3487 -1, "rkisp_thunderboot");
3488
3489 isp_dev->resmem_pa = 0;
3490 isp_dev->resmem_size = 0;
3491 }
3492 break;
3493 case RKISP_CMD_FREE_SHARED_BUF:
3494 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
3495 ret = -ENOIOCTLCMD;
3496 break;
3497 }
3498 if (isp_dev->resmem_pa && isp_dev->resmem_size) {
3499 dma_unmap_single(isp_dev->dev, isp_dev->resmem_pa,
3500 sizeof(struct rkisp_thunderboot_resmem_head),
3501 DMA_FROM_DEVICE);
3502 free_reserved_area(phys_to_virt(isp_dev->resmem_pa),
3503 phys_to_virt(isp_dev->resmem_pa) + isp_dev->resmem_size,
3504 -1, "rkisp_thunderboot");
3505 }
3506
3507 isp_dev->resmem_pa = 0;
3508 isp_dev->resmem_size = 0;
3509 break;
3510 case RKISP_CMD_GET_LDCHBUF_INFO:
3511 case RKISP_CMD_GET_MESHBUF_INFO:
3512 rkisp_params_get_meshbuf_inf(&isp_dev->params_vdev, arg);
3513 break;
3514 case RKISP_CMD_SET_LDCHBUF_SIZE:
3515 case RKISP_CMD_SET_MESHBUF_SIZE:
3516 ret = rkisp_params_set_meshbuf_size(&isp_dev->params_vdev, arg);
3517 break;
3518 case RKISP_CMD_GET_SHM_BUFFD:
3519 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
3520 ret = -ENOIOCTLCMD;
3521 break;
3522 }
3523 shmem = (struct rkisp_thunderboot_shmem *)arg;
3524 ret = rkisp_tb_shm_ioctl(shmem);
3525 break;
3526 case RKISP_CMD_GET_FBCBUF_FD:
3527 idxfd = (struct isp2x_buf_idxfd *)arg;
3528 ret = rkisp_bridge_get_fbcbuf_fd(isp_dev, idxfd);
3529 break;
3530 case RKISP_CMD_INFO2DDR:
3531 ret = rkisp_params_info2ddr_cfg(&isp_dev->params_vdev, arg);
3532 break;
3533 case RKISP_CMD_MESHBUF_FREE:
3534 rkisp_params_meshbuf_free(&isp_dev->params_vdev, *(u64 *)arg);
3535 break;
3536 case RKISP_VICAP_CMD_RX_BUFFER_FREE:
3537 dbufs = (struct rkisp_rx_buf *)arg;
3538 rkisp_rx_buf_free(isp_dev, dbufs);
3539 break;
3540 case RKISP_CMD_MULTI_DEV_FORCE_ENUM:
3541 if (isp_dev->hw_dev->is_runing) {
3542 ret = -EINVAL;
3543 } else {
3544 isp_dev->hw_dev->is_single = true;
3545 isp_dev->hw_dev->is_multi_overflow = false;
3546 rkisp_hw_enum_isp_size(isp_dev->hw_dev);
3547 }
3548 break;
3549 default:
3550 ret = -ENOIOCTLCMD;
3551 }
3552
3553 return ret;
3554 }
3555
3556 #ifdef CONFIG_COMPAT
rkisp_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)3557 static long rkisp_compat_ioctl32(struct v4l2_subdev *sd,
3558 unsigned int cmd, unsigned long arg)
3559 {
3560 void __user *up = compat_ptr(arg);
3561 struct isp2x_csi_trigger trigger;
3562 struct rkisp_thunderboot_resmem resmem;
3563 struct rkisp_ldchbuf_info ldchbuf;
3564 struct rkisp_ldchbuf_size ldchsize;
3565 struct rkisp_meshbuf_info meshbuf;
3566 struct rkisp_meshbuf_size meshsize;
3567 struct rkisp_thunderboot_shmem shmem;
3568 struct isp2x_buf_idxfd idxfd;
3569 struct rkisp_info2ddr info2ddr;
3570 long ret = 0;
3571 u64 module_id;
3572
3573 if (!up && cmd != RKISP_CMD_FREE_SHARED_BUF)
3574 return -EINVAL;
3575
3576 switch (cmd) {
3577 case RKISP_CMD_TRIGGER_READ_BACK:
3578 if (copy_from_user(&trigger, up, sizeof(trigger)))
3579 return -EFAULT;
3580 ret = rkisp_ioctl(sd, cmd, &trigger);
3581 break;
3582 case RKISP_CMD_GET_SHARED_BUF:
3583 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
3584 ret = -ENOIOCTLCMD;
3585 break;
3586 }
3587 ret = rkisp_ioctl(sd, cmd, &resmem);
3588 if (!ret && copy_to_user(up, &resmem, sizeof(resmem)))
3589 ret = -EFAULT;
3590 break;
3591 case RKISP_CMD_FREE_SHARED_BUF:
3592 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
3593 ret = -ENOIOCTLCMD;
3594 break;
3595 }
3596 ret = rkisp_ioctl(sd, cmd, NULL);
3597 break;
3598 case RKISP_CMD_GET_LDCHBUF_INFO:
3599 ret = rkisp_ioctl(sd, cmd, &ldchbuf);
3600 if (!ret && copy_to_user(up, &ldchbuf, sizeof(ldchbuf)))
3601 ret = -EFAULT;
3602 break;
3603 case RKISP_CMD_SET_LDCHBUF_SIZE:
3604 if (copy_from_user(&ldchsize, up, sizeof(ldchsize)))
3605 return -EFAULT;
3606 ret = rkisp_ioctl(sd, cmd, &ldchsize);
3607 break;
3608 case RKISP_CMD_GET_MESHBUF_INFO:
3609 if (copy_from_user(&meshbuf, up, sizeof(meshbuf)))
3610 return -EFAULT;
3611 ret = rkisp_ioctl(sd, cmd, &meshbuf);
3612 if (!ret && copy_to_user(up, &meshbuf, sizeof(meshbuf)))
3613 ret = -EFAULT;
3614 break;
3615 case RKISP_CMD_SET_MESHBUF_SIZE:
3616 if (copy_from_user(&meshsize, up, sizeof(meshsize)))
3617 return -EFAULT;
3618 ret = rkisp_ioctl(sd, cmd, &meshsize);
3619 break;
3620 case RKISP_CMD_GET_SHM_BUFFD:
3621 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
3622 ret = -ENOIOCTLCMD;
3623 break;
3624 }
3625 if (copy_from_user(&shmem, up, sizeof(shmem)))
3626 return -EFAULT;
3627 ret = rkisp_ioctl(sd, cmd, &shmem);
3628 if (!ret && copy_to_user(up, &shmem, sizeof(shmem)))
3629 ret = -EFAULT;
3630 break;
3631 case RKISP_CMD_GET_FBCBUF_FD:
3632 ret = rkisp_ioctl(sd, cmd, &idxfd);
3633 if (!ret && copy_to_user(up, &idxfd, sizeof(idxfd)))
3634 ret = -EFAULT;
3635 break;
3636 case RKISP_CMD_INFO2DDR:
3637 if (copy_from_user(&info2ddr, up, sizeof(info2ddr)))
3638 return -EFAULT;
3639 ret = rkisp_ioctl(sd, cmd, &info2ddr);
3640 if (!ret && copy_to_user(up, &info2ddr, sizeof(info2ddr)))
3641 ret = -EFAULT;
3642 break;
3643 case RKISP_CMD_MESHBUF_FREE:
3644 if (copy_from_user(&module_id, up, sizeof(module_id)))
3645 return -EFAULT;
3646 ret = rkisp_ioctl(sd, cmd, &module_id);
3647 break;
3648 case RKISP_CMD_MULTI_DEV_FORCE_ENUM:
3649 ret = rkisp_ioctl(sd, cmd, NULL);
3650 break;
3651 default:
3652 ret = -ENOIOCTLCMD;
3653 }
3654
3655 return ret;
3656 }
3657 #endif
3658
3659 static const struct v4l2_subdev_pad_ops rkisp_isp_sd_pad_ops = {
3660 .enum_mbus_code = rkisp_isp_sd_enum_mbus_code,
3661 .get_selection = rkisp_isp_sd_get_selection,
3662 .set_selection = rkisp_isp_sd_set_selection,
3663 .get_fmt = rkisp_isp_sd_get_fmt,
3664 .set_fmt = rkisp_isp_sd_set_fmt,
3665 #ifdef CONFIG_MEDIA_CONTROLLER
3666 .link_validate = rkisp_subdev_fmt_link_validate,
3667 #endif
3668 };
3669
3670 static const struct media_entity_operations rkisp_isp_sd_media_ops = {
3671 .link_setup = rkisp_subdev_link_setup,
3672 .link_validate = rkisp_subdev_link_validate,
3673 };
3674
3675 static const struct v4l2_subdev_video_ops rkisp_isp_sd_video_ops = {
3676 .s_stream = rkisp_isp_sd_s_stream,
3677 .s_rx_buffer = rkisp_sd_s_rx_buffer,
3678 };
3679
3680 static const struct v4l2_subdev_core_ops rkisp_isp_core_ops = {
3681 .subscribe_event = rkisp_isp_sd_subs_evt,
3682 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3683 .s_power = rkisp_isp_sd_s_power,
3684 .ioctl = rkisp_ioctl,
3685 #ifdef CONFIG_COMPAT
3686 .compat_ioctl32 = rkisp_compat_ioctl32,
3687 #endif
3688 };
3689
3690 static struct v4l2_subdev_ops rkisp_isp_sd_ops = {
3691 .core = &rkisp_isp_core_ops,
3692 .video = &rkisp_isp_sd_video_ops,
3693 .pad = &rkisp_isp_sd_pad_ops,
3694 };
3695
rkisp_isp_sd_init_default_fmt(struct rkisp_isp_subdev * isp_sd)3696 static void rkisp_isp_sd_init_default_fmt(struct rkisp_isp_subdev *isp_sd)
3697 {
3698 struct v4l2_mbus_framefmt *in_frm = &isp_sd->in_frm;
3699 struct v4l2_rect *in_crop = &isp_sd->in_crop;
3700 struct v4l2_rect *out_crop = &isp_sd->out_crop;
3701 struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt;
3702 struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt;
3703
3704 *in_fmt = rkisp_isp_input_formats[0];
3705 in_frm->width = RKISP_DEFAULT_WIDTH;
3706 in_frm->height = RKISP_DEFAULT_HEIGHT;
3707 in_frm->code = in_fmt->mbus_code;
3708
3709 in_crop->width = in_frm->width;
3710 in_crop->height = in_frm->height;
3711 in_crop->left = 0;
3712 in_crop->top = 0;
3713
3714 /* propagate to source */
3715 *out_crop = *in_crop;
3716 *out_fmt = rkisp_isp_output_formats[0];
3717 isp_sd->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3718 isp_sd->colorspace = V4L2_COLORSPACE_SMPTE170M;
3719 }
3720
rkisp_register_isp_subdev(struct rkisp_device * isp_dev,struct v4l2_device * v4l2_dev)3721 int rkisp_register_isp_subdev(struct rkisp_device *isp_dev,
3722 struct v4l2_device *v4l2_dev)
3723 {
3724 struct rkisp_isp_subdev *isp_sdev = &isp_dev->isp_sdev;
3725 struct v4l2_subdev *sd = &isp_sdev->sd;
3726 int ret;
3727
3728 mutex_init(&isp_dev->buf_lock);
3729 spin_lock_init(&isp_dev->cmsk_lock);
3730 spin_lock_init(&isp_dev->rdbk_lock);
3731 ret = kfifo_alloc(&isp_dev->rdbk_kfifo,
3732 16 * sizeof(struct isp2x_csi_trigger), GFP_KERNEL);
3733 if (ret < 0) {
3734 v4l2_err(v4l2_dev, "Failed to alloc csi kfifo %d", ret);
3735 return ret;
3736 }
3737
3738 v4l2_subdev_init(sd, &rkisp_isp_sd_ops);
3739 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3740 sd->entity.ops = &rkisp_isp_sd_media_ops;
3741 sd->entity.function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
3742 snprintf(sd->name, sizeof(sd->name), ISP_SUBDEV_NAME);
3743
3744 isp_sdev->pads[RKISP_ISP_PAD_SINK].flags =
3745 MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
3746 isp_sdev->pads[RKISP_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
3747 isp_sdev->pads[RKISP_ISP_PAD_SOURCE_PATH].flags = MEDIA_PAD_FL_SOURCE;
3748 isp_sdev->pads[RKISP_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE;
3749 ret = media_entity_pads_init(&sd->entity, RKISP_ISP_PAD_MAX,
3750 isp_sdev->pads);
3751 if (ret < 0)
3752 goto free_kfifo;
3753
3754 sd->owner = THIS_MODULE;
3755 v4l2_set_subdevdata(sd, isp_dev);
3756
3757 sd->grp_id = GRP_ID_ISP;
3758 ret = v4l2_device_register_subdev(v4l2_dev, sd);
3759 if (ret < 0) {
3760 v4l2_err(sd, "Failed to register isp subdev\n");
3761 goto err_cleanup_media_entity;
3762 }
3763
3764 rkisp_isp_sd_init_default_fmt(isp_sdev);
3765 isp_dev->hdr.sensor = NULL;
3766 isp_dev->isp_state = ISP_STOP;
3767 atomic_set(&isp_sdev->frm_sync_seq, 0);
3768 rkisp_monitor_init(isp_dev);
3769 INIT_WORK(&isp_dev->rdbk_work, rkisp_rdbk_work);
3770 return 0;
3771 err_cleanup_media_entity:
3772 media_entity_cleanup(&sd->entity);
3773 free_kfifo:
3774 kfifo_free(&isp_dev->rdbk_kfifo);
3775 return ret;
3776 }
3777
rkisp_unregister_isp_subdev(struct rkisp_device * isp_dev)3778 void rkisp_unregister_isp_subdev(struct rkisp_device *isp_dev)
3779 {
3780 struct v4l2_subdev *sd = &isp_dev->isp_sdev.sd;
3781
3782 kfifo_free(&isp_dev->rdbk_kfifo);
3783 v4l2_device_unregister_subdev(sd);
3784 media_entity_cleanup(&sd->entity);
3785 }
3786
3787 #define shm_head_poll_timeout(isp_dev, cond, sleep_us, timeout_us) \
3788 ({ \
3789 u64 __timeout_us = (timeout_us); \
3790 unsigned long __sleep_us = (sleep_us); \
3791 ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
3792 might_sleep_if((__sleep_us) != 0); \
3793 for (;;) { \
3794 dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr, \
3795 sizeof(struct rkisp_thunderboot_resmem_head), \
3796 DMA_FROM_DEVICE); \
3797 if (cond) \
3798 break; \
3799 if (__timeout_us && \
3800 ktime_compare(ktime_get(), __timeout) > 0) { \
3801 break; \
3802 } \
3803 if (__sleep_us) \
3804 usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
3805 } \
3806 (cond) ? 0 : -ETIMEDOUT; \
3807 })
3808
3809 #ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
rkisp_chk_tb_over(struct rkisp_device * isp_dev)3810 void rkisp_chk_tb_over(struct rkisp_device *isp_dev)
3811 {
3812 struct rkisp_hw_dev *hw = isp_dev->hw_dev;
3813 struct rkisp_thunderboot_resmem_head *head;
3814 enum rkisp_tb_state tb_state;
3815 void *resmem_va;
3816
3817 if (!isp_dev->is_thunderboot)
3818 return;
3819
3820 resmem_va = phys_to_virt(isp_dev->resmem_pa);
3821 head = (struct rkisp_thunderboot_resmem_head *)resmem_va;
3822 dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr,
3823 sizeof(struct rkisp_thunderboot_resmem_head),
3824 DMA_FROM_DEVICE);
3825
3826 shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 400 * USEC_PER_MSEC);
3827 if (head->complete != RKISP_TB_OK) {
3828 v4l2_err(&isp_dev->v4l2_dev, "wait thunderboot over timeout\n");
3829 } else {
3830 struct rkisp_isp_params_vdev *params_vdev = &isp_dev->params_vdev;
3831 void *param = NULL;
3832 u32 size = 0, offset = 0, timeout = 50;
3833
3834 /* wait for all isp dev to register */
3835 if (head->camera_num > 1) {
3836 while (timeout--) {
3837 if (hw->dev_num >= head->camera_num &&
3838 hw->isp[hw->dev_num - 1]->is_probe_end)
3839 break;
3840 usleep_range(200, 210);
3841 }
3842 }
3843
3844 switch (isp_dev->isp_ver) {
3845 case ISP_V32:
3846 size = sizeof(struct rkisp32_thunderboot_resmem_head);
3847 offset = size * isp_dev->dev_id;
3848 break;
3849 default:
3850 break;
3851 }
3852
3853 if (size && size < isp_dev->resmem_size) {
3854 dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr + offset,
3855 size, DMA_FROM_DEVICE);
3856 params_vdev->is_first_cfg = true;
3857 if (isp_dev->isp_ver == ISP_V32) {
3858 struct rkisp32_thunderboot_resmem_head *tmp = resmem_va + offset;
3859
3860 param = &tmp->cfg;
3861 head = &tmp->head;
3862 v4l2_info(&isp_dev->v4l2_dev,
3863 "tb param module en:0x%llx upd:0x%llx cfg upd:0x%llx\n",
3864 tmp->cfg.module_en_update,
3865 tmp->cfg.module_ens,
3866 tmp->cfg.module_cfg_update);
3867 }
3868 if (param)
3869 params_vdev->ops->save_first_param(params_vdev, param);
3870 } else if (size > isp_dev->resmem_size) {
3871 v4l2_err(&isp_dev->v4l2_dev,
3872 "resmem size:%zu no enough for head:%d\n",
3873 isp_dev->resmem_size, size);
3874 head->complete = RKISP_TB_NG;
3875 }
3876 }
3877 memcpy(&isp_dev->tb_head, head, sizeof(*head));
3878 v4l2_info(&isp_dev->v4l2_dev,
3879 "thunderboot info: %d, %d, %d, %d, %d, %d | %d %d\n",
3880 head->enable,
3881 head->complete,
3882 head->frm_total,
3883 head->hdr_mode,
3884 head->width,
3885 head->height,
3886 head->camera_num,
3887 head->camera_index);
3888
3889 tb_state = RKISP_TB_OK;
3890 if (head->complete != RKISP_TB_OK) {
3891 head->frm_total = 0;
3892 tb_state = RKISP_TB_NG;
3893 }
3894
3895 if (hw->is_thunderboot) {
3896 rkisp_register_irq(hw);
3897 rkisp_tb_set_state(tb_state);
3898 rkisp_tb_unprotect_clk();
3899 hw->is_thunderboot = false;
3900 }
3901 isp_dev->is_thunderboot = false;
3902 }
3903 #endif
3904
3905 /**************** Interrupter Handler ****************/
3906
rkisp_mipi_isr(unsigned int mis,struct rkisp_device * dev)3907 void rkisp_mipi_isr(unsigned int mis, struct rkisp_device *dev)
3908 {
3909 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3910 void __iomem *base = dev->base_addr;
3911 u32 val;
3912
3913 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
3914 "mipi isr:0x%x\n", mis);
3915
3916 writel(~0, base + CIF_MIPI_ICR);
3917
3918 /*
3919 * Disable DPHY errctrl interrupt, because this dphy
3920 * erctrl signal is asserted until the next changes
3921 * of line state. This time is may be too long and cpu
3922 * is hold in this interrupt.
3923 */
3924 if (mis & CIF_MIPI_ERR_DPHY) {
3925 val = readl(base + CIF_MIPI_IMSC);
3926 writel(val & ~CIF_MIPI_ERR_DPHY, base + CIF_MIPI_IMSC);
3927 dev->isp_sdev.dphy_errctrl_disabled = true;
3928 }
3929
3930 /*
3931 * Enable DPHY errctrl interrupt again, if mipi have receive
3932 * the whole frame without any error.
3933 */
3934 if (mis == CIF_MIPI_FRAME_END) {
3935 /*
3936 * Enable DPHY errctrl interrupt again, if mipi have receive
3937 * the whole frame without any error.
3938 */
3939 if (dev->isp_sdev.dphy_errctrl_disabled) {
3940 val = readl(base + CIF_MIPI_IMSC);
3941 val |= CIF_MIPI_ERR_DPHY;
3942 writel(val, base + CIF_MIPI_IMSC);
3943 dev->isp_sdev.dphy_errctrl_disabled = false;
3944 }
3945 } else {
3946 v4l2_warn(v4l2_dev, "MIPI mis error: 0x%08x\n", mis);
3947 val = readl(base + CIF_MIPI_CTRL);
3948 writel(val | CIF_MIPI_CTRL_FLUSH_FIFO, base + CIF_MIPI_CTRL);
3949 }
3950 }
3951
rkisp_mipi_v13_isr(unsigned int err1,unsigned int err2,unsigned int err3,struct rkisp_device * dev)3952 void rkisp_mipi_v13_isr(unsigned int err1, unsigned int err2,
3953 unsigned int err3, struct rkisp_device *dev)
3954 {
3955 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3956 void __iomem *base = dev->base_addr;
3957 u32 val, mask;
3958
3959 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
3960 "mipi isr err1:0x%x err2:0x%x err3:0x%x\n",
3961 err1, err2, err3);
3962
3963 /*
3964 * Disable DPHY errctrl interrupt, because this dphy
3965 * erctrl signal is asserted until the next changes
3966 * of line state. This time is may be too long and cpu
3967 * is hold in this interrupt.
3968 */
3969 mask = CIF_ISP_CSI0_IMASK1_PHY_ERRSOTSYNC(0x0F) |
3970 CIF_ISP_CSI0_IMASK1_PHY_ERREOTSYNC(0x0F);
3971 if (mask & err1) {
3972 val = readl(base + CIF_ISP_CSI0_MASK1);
3973 writel(val & ~mask, base + CIF_ISP_CSI0_MASK1);
3974 dev->isp_sdev.dphy_errctrl_disabled = true;
3975 }
3976
3977 mask = CIF_ISP_CSI0_IMASK2_PHY_ERRSOTHS(0x0F) |
3978 CIF_ISP_CSI0_IMASK2_PHY_ERRCONTROL(0x0F);
3979 if (mask & err2) {
3980 val = readl(base + CIF_ISP_CSI0_MASK2);
3981 writel(val & ~mask, base + CIF_ISP_CSI0_MASK2);
3982 dev->isp_sdev.dphy_errctrl_disabled = true;
3983 }
3984
3985 mask = CIF_ISP_CSI0_IMASK_FRAME_END(0x3F);
3986 if ((err3 & mask) && !err1 && !err2) {
3987 /*
3988 * Enable DPHY errctrl interrupt again, if mipi have receive
3989 * the whole frame without any error.
3990 */
3991 if (dev->isp_sdev.dphy_errctrl_disabled) {
3992 writel(0x1FFFFFF0, base + CIF_ISP_CSI0_MASK1);
3993 writel(0x03FFFFFF, base + CIF_ISP_CSI0_MASK2);
3994 dev->isp_sdev.dphy_errctrl_disabled = false;
3995 }
3996 }
3997
3998 if (err1)
3999 v4l2_warn(v4l2_dev, "MIPI error: err1: 0x%08x\n", err1);
4000
4001 if (err2)
4002 v4l2_warn(v4l2_dev, "MIPI error: err2: 0x%08x\n", err2);
4003 }
4004
rkisp_isp_isr(unsigned int isp_mis,unsigned int isp3a_mis,struct rkisp_device * dev)4005 void rkisp_isp_isr(unsigned int isp_mis,
4006 unsigned int isp3a_mis,
4007 struct rkisp_device *dev)
4008 {
4009 struct rkisp_hw_dev *hw = dev->hw_dev;
4010 void __iomem *base = !hw->is_unite ?
4011 hw->base_addr : hw->base_next_addr;
4012 unsigned int isp_mis_tmp = 0;
4013 unsigned int isp_err = 0;
4014 u32 si3a_isr_mask = ISP2X_SIAWB_DONE | ISP2X_SIAF_FIN |
4015 ISP2X_YUVAE_END | ISP2X_SIHST_RDY;
4016 u32 raw3a_isr_mask = ISP2X_3A_RAWAE_BIG | ISP2X_3A_RAWAE_CH0 |
4017 ISP2X_3A_RAWAE_CH1 | ISP2X_3A_RAWAE_CH2 |
4018 ISP2X_3A_RAWHIST_BIG | ISP2X_3A_RAWHIST_CH0 |
4019 ISP2X_3A_RAWHIST_CH1 | ISP2X_3A_RAWHIST_CH2 |
4020 ISP2X_3A_RAWAF_SUM | ISP2X_3A_RAWAF_LUM |
4021 ISP2X_3A_RAWAWB;
4022 bool sof_event_later = false;
4023
4024 /*
4025 * The last time that rx perform 'back read' don't clear done flag
4026 * in advance, otherwise the statistics will be abnormal.
4027 */
4028 if (isp3a_mis & ISP2X_3A_RAWAE_BIG && dev->params_vdev.rdbk_times > 0)
4029 writel(BIT(31), base + RAWAE_BIG1_BASE + RAWAE_BIG_CTRL);
4030
4031 if (hw->is_unite) {
4032 u32 val = rkisp_read(dev, ISP3X_ISP_RIS, true);
4033
4034 if (val) {
4035 rkisp_write(dev, ISP3X_ISP_ICR, val, true);
4036 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
4037 "left isp isr:0x%x\n", val);
4038 if (isp_mis & CIF_ISP_FRAME && !(val & CIF_ISP_FRAME)) {
4039 /* wait isp0 frame end */
4040 int timeout = read_poll_timeout_atomic(rkisp_read,
4041 val, val & CIF_ISP_FRAME, 20, 20 * 50, true, dev, ISP3X_ISP_RIS, true);
4042
4043 if (val)
4044 rkisp_write(dev, ISP3X_ISP_ICR, val, true);
4045 if (timeout)
4046 dev_err(dev->dev, "wait isp end timeout\n");
4047 }
4048 }
4049 }
4050 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
4051 "isp isr:0x%x, 0x%x\n", isp_mis, isp3a_mis);
4052 dev->isp_isr_cnt++;
4053 /* start edge of v_sync */
4054 if (isp_mis & CIF_ISP_V_START) {
4055 if (dev->hw_dev->monitor.is_en) {
4056 rkisp_set_state(&dev->hw_dev->monitor.state, ISP_FRAME_VS);
4057 if (!completion_done(&dev->hw_dev->monitor.cmpl))
4058 complete(&dev->hw_dev->monitor.cmpl);
4059 }
4060
4061 if (IS_HDR_RDBK(dev->hdr.op_mode)) {
4062 /* read 3d lut at isp readback */
4063 if (!dev->hw_dev->is_single)
4064 rkisp_write(dev, ISP_3DLUT_UPDATE, 0, true);
4065 rkisp_stats_rdbk_enable(&dev->stats_vdev, true);
4066 goto vs_skip;
4067 }
4068 if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
4069 /* 0 = ODD 1 = EVEN */
4070 if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
4071 void __iomem *addr = NULL;
4072
4073 if (dev->isp_ver == ISP_V10 ||
4074 dev->isp_ver == ISP_V10_1)
4075 addr = base + CIF_MIPI_FRAME;
4076 else if (dev->isp_ver == ISP_V12 ||
4077 dev->isp_ver == ISP_V13)
4078 addr = base + CIF_ISP_CSI0_FRAME_NUM_RO;
4079
4080 if (addr)
4081 dev->cap_dev.stream[RKISP_STREAM_SP].u.sp.field =
4082 (readl(addr) >> 16) % 2;
4083 } else {
4084 dev->cap_dev.stream[RKISP_STREAM_SP].u.sp.field =
4085 (readl(base + CIF_ISP_FLAGS_SHD) >> 2) & BIT(0);
4086 }
4087 }
4088
4089 if (isp_mis & CIF_ISP_FRAME)
4090 sof_event_later = true;
4091 if (dev->vs_irq < 0 && !sof_event_later) {
4092 dev->isp_sdev.frm_timestamp = ktime_get_ns();
4093 rkisp_isp_queue_event_sof(&dev->isp_sdev);
4094 rkisp_stream_frame_start(dev, isp_mis);
4095 }
4096 vs_skip:
4097 writel(CIF_ISP_V_START, base + CIF_ISP_ICR);
4098 isp_mis_tmp = readl(base + CIF_ISP_MIS);
4099 if (isp_mis_tmp & CIF_ISP_V_START)
4100 v4l2_err(&dev->v4l2_dev, "isp icr v_statr err: 0x%x\n",
4101 isp_mis_tmp);
4102 }
4103
4104 if ((isp_mis & (CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR))) {
4105 if ((isp_mis & CIF_ISP_PIC_SIZE_ERROR)) {
4106 /* Clear pic_size_error */
4107 writel(CIF_ISP_PIC_SIZE_ERROR, base + CIF_ISP_ICR);
4108 isp_err = readl(base + CIF_ISP_ERR);
4109 v4l2_err(&dev->v4l2_dev,
4110 "CIF_ISP_PIC_SIZE_ERROR (0x%08x)", isp_err);
4111 writel(isp_err, base + CIF_ISP_ERR_CLR);
4112 }
4113
4114 if ((isp_mis & CIF_ISP_DATA_LOSS)) {
4115 /* Clear data_loss */
4116 writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
4117 v4l2_err(&dev->v4l2_dev, "CIF_ISP_DATA_LOSS\n");
4118 writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
4119 }
4120
4121 if (dev->isp_err_cnt++ > RKISP_CONTI_ERR_MAX) {
4122 if (!(dev->isp_state & ISP_ERROR)) {
4123 rkisp_set_state(&dev->isp_state, ISP_ERROR);
4124 rkisp_clear_bits(dev, CIF_ISP_IMSC,
4125 CIF_ISP_DATA_LOSS |
4126 CIF_ISP_PIC_SIZE_ERROR, true);
4127 writel(CIF_ISP_PIC_SIZE_ERROR, base + CIF_ISP_ICR);
4128 writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
4129 if (dev->hw_dev->monitor.is_en) {
4130 rkisp_set_state(&dev->hw_dev->monitor.state, ISP_ERROR);
4131 if (!completion_done(&dev->hw_dev->monitor.cmpl))
4132 complete(&dev->hw_dev->monitor.cmpl);
4133 }
4134 }
4135 }
4136 }
4137
4138 if (isp3a_mis & ISP2X_3A_RAWAF) {
4139 writel(ISP3X_3A_RAWAF, base + ISP3X_ISP_3A_ICR);
4140 /* 3a irq will with lsc_lut_err irq if isp version below isp32 */
4141 if (isp_mis & ISP2X_LSC_LUT_ERR)
4142 isp_mis &= ~ISP2X_LSC_LUT_ERR;
4143 if (dev->rawaf_irq_cnt == 0)
4144 rkisp_stream_buf_done_early(dev);
4145 dev->rawaf_irq_cnt++;
4146 }
4147
4148 if (isp_mis & ISP2X_LSC_LUT_ERR) {
4149 writel(ISP2X_LSC_LUT_ERR, base + CIF_ISP_ICR);
4150
4151 isp_err = readl(base + CIF_ISP_ERR);
4152 v4l2_err(&dev->v4l2_dev,
4153 "ISP2X_LSC_LUT_ERR. ISP_ERR 0x%x\n", isp_err);
4154 writel(isp_err, base + CIF_ISP_ERR_CLR);
4155 }
4156
4157 /* sampled input frame is complete */
4158 if (isp_mis & CIF_ISP_FRAME_IN) {
4159 dev->isp_sdev.dbg.interval =
4160 ktime_get_ns() - dev->isp_sdev.dbg.timestamp;
4161 rkisp_set_state(&dev->isp_state, ISP_FRAME_IN);
4162 writel(CIF_ISP_FRAME_IN, base + CIF_ISP_ICR);
4163 isp_mis_tmp = readl(base + CIF_ISP_MIS);
4164 if (isp_mis_tmp & CIF_ISP_FRAME_IN)
4165 v4l2_err(&dev->v4l2_dev, "isp icr frame_in err: 0x%x\n",
4166 isp_mis_tmp);
4167 }
4168
4169 /* frame was completely put out */
4170 if (isp_mis & CIF_ISP_FRAME) {
4171 dev->rawaf_irq_cnt = 0;
4172 if (!dev->is_pre_on || !IS_HDR_RDBK(dev->rd_mode))
4173 dev->isp_sdev.dbg.interval =
4174 ktime_get_ns() - dev->isp_sdev.dbg.timestamp;
4175 /* Clear Frame In (ISP) */
4176 rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
4177 writel(CIF_ISP_FRAME, base + CIF_ISP_ICR);
4178 isp_mis_tmp = readl(base + CIF_ISP_MIS);
4179 if (isp_mis_tmp & CIF_ISP_FRAME)
4180 v4l2_err(&dev->v4l2_dev,
4181 "isp icr frame end err: 0x%x\n", isp_mis_tmp);
4182 rkisp_dmarx_get_frame(dev, &dev->isp_sdev.dbg.id, NULL, NULL, true);
4183 rkisp_isp_read_add_fifo_data(dev);
4184
4185 dev->isp_err_cnt = 0;
4186 dev->isp_state &= ~ISP_ERROR;
4187 }
4188
4189 if (isp_mis & CIF_ISP_V_START) {
4190 if (dev->isp_state & ISP_FRAME_END) {
4191 u64 tmp = dev->isp_sdev.dbg.interval +
4192 dev->isp_sdev.dbg.timestamp;
4193
4194 dev->isp_sdev.dbg.timestamp = ktime_get_ns();
4195 /* v-blank: frame(N)start - frame(N-1)end */
4196 dev->isp_sdev.dbg.delay = dev->isp_sdev.dbg.timestamp - tmp;
4197 }
4198 rkisp_set_state(&dev->isp_state, ISP_FRAME_VS);
4199 if (dev->procfs.is_fs_wait) {
4200 dev->procfs.is_fs_wait = false;
4201 wake_up(&dev->procfs.fs_wait);
4202 }
4203 }
4204
4205 if ((isp_mis & (CIF_ISP_FRAME | si3a_isr_mask)) ||
4206 (isp3a_mis & raw3a_isr_mask)) {
4207 u32 irq = isp_mis;
4208
4209 /* FRAME to get EXP and HIST together */
4210 if (isp_mis & CIF_ISP_FRAME)
4211 irq |= ((CIF_ISP_EXP_END |
4212 CIF_ISP_HIST_MEASURE_RDY) &
4213 readl(base + CIF_ISP_RIS));
4214
4215 rkisp_stats_isr(&dev->stats_vdev, irq, isp3a_mis);
4216
4217 if ((isp_mis & CIF_ISP_FRAME) && dev->stats_vdev.rdbk_mode)
4218 rkisp_stats_rdbk_enable(&dev->stats_vdev, false);
4219
4220 if (!IS_HDR_RDBK(dev->hdr.op_mode))
4221 rkisp_config_cmsk(dev);
4222 }
4223
4224 if (isp_mis & CIF_ISP_FRAME) {
4225 if (dev->hw_dev->isp_ver == ISP_V32) {
4226 struct rkisp_stream *s = &dev->cap_dev.stream[RKISP_STREAM_LUMA];
4227
4228 s->ops->frame_end(s, FRAME_IRQ);
4229 }
4230 if (dev->procfs.is_fe_wait) {
4231 dev->procfs.is_fe_wait = false;
4232 wake_up(&dev->procfs.fe_wait);
4233 }
4234 }
4235
4236 /*
4237 * Then update changed configs. Some of them involve
4238 * lot of register writes. Do those only one per frame.
4239 * Do the updates in the order of the processing flow.
4240 */
4241 if (isp_mis & (CIF_ISP_V_START | CIF_ISP_FRAME))
4242 rkisp_params_isr(&dev->params_vdev, isp_mis);
4243
4244 /* cur frame end and next frame start irq togeter */
4245 if (dev->vs_irq < 0 && sof_event_later) {
4246 dev->isp_sdev.frm_timestamp = ktime_get_ns();
4247 rkisp_isp_queue_event_sof(&dev->isp_sdev);
4248 rkisp_stream_frame_start(dev, isp_mis);
4249 }
4250
4251 if (isp_mis & ISP3X_OUT_FRM_QUARTER) {
4252 writel(ISP3X_OUT_FRM_QUARTER, base + CIF_ISP_ICR);
4253 rkisp_dvbm_event(dev, ISP3X_OUT_FRM_QUARTER);
4254 }
4255 if (isp_mis & ISP3X_OUT_FRM_HALF) {
4256 writel(ISP3X_OUT_FRM_HALF, base + CIF_ISP_ICR);
4257 rkisp_dvbm_event(dev, ISP3X_OUT_FRM_HALF);
4258 rkisp_stream_buf_done_early(dev);
4259 }
4260 if (isp_mis & ISP3X_OUT_FRM_END) {
4261 writel(ISP3X_OUT_FRM_END, base + CIF_ISP_ICR);
4262 rkisp_dvbm_event(dev, ISP3X_OUT_FRM_END);
4263 }
4264
4265 if (isp_mis & CIF_ISP_FRAME)
4266 rkisp_check_idle(dev, ISP_FRAME_END);
4267 }
4268
rkisp_vs_isr_handler(int irq,void * ctx)4269 irqreturn_t rkisp_vs_isr_handler(int irq, void *ctx)
4270 {
4271 struct device *dev = ctx;
4272 struct rkisp_device *rkisp_dev = dev_get_drvdata(dev);
4273
4274 if (rkisp_dev->vs_irq >= 0)
4275 rkisp_isp_queue_event_sof(&rkisp_dev->isp_sdev);
4276
4277 return IRQ_HANDLED;
4278 }
4279
4280