xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/lt6911uxe.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * lt6911uxe HDMI to MIPI CSI-2 bridge driver.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Jianwei Fan <jianwei.fan@rock-chips.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * V0.0X01.0X00 first version.
10*4882a593Smuzhiyun  * V0.0X01.0X01 support DPHY 4K60.
11*4882a593Smuzhiyun  * V0.0X01.0X02 support BGR888 format.
12*4882a593Smuzhiyun  * V0.0X01.0X03 add more timing support.
13*4882a593Smuzhiyun  * V0.0X01.0X04
14*4882a593Smuzhiyun  *  1.fix some errors.
15*4882a593Smuzhiyun  *  2.add dphy timing reg.
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun // #define DEBUG
19*4882a593Smuzhiyun #include <linux/clk.h>
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
22*4882a593Smuzhiyun #include <linux/hdmi.h>
23*4882a593Smuzhiyun #include <linux/i2c.h>
24*4882a593Smuzhiyun #include <linux/interrupt.h>
25*4882a593Smuzhiyun #include <linux/kernel.h>
26*4882a593Smuzhiyun #include <linux/module.h>
27*4882a593Smuzhiyun #include <linux/of_graph.h>
28*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
29*4882a593Smuzhiyun #include <linux/slab.h>
30*4882a593Smuzhiyun #include <linux/timer.h>
31*4882a593Smuzhiyun #include <linux/v4l2-dv-timings.h>
32*4882a593Smuzhiyun #include <linux/version.h>
33*4882a593Smuzhiyun #include <linux/videodev2.h>
34*4882a593Smuzhiyun #include <linux/workqueue.h>
35*4882a593Smuzhiyun #include <linux/compat.h>
36*4882a593Smuzhiyun #include <media/v4l2-controls_rockchip.h>
37*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
38*4882a593Smuzhiyun #include <media/v4l2-device.h>
39*4882a593Smuzhiyun #include <media/v4l2-dv-timings.h>
40*4882a593Smuzhiyun #include <media/v4l2-event.h>
41*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x04)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static int debug;
46*4882a593Smuzhiyun module_param(debug, int, 0644);
47*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "debug level (0-3)");
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #define I2C_MAX_XFER_SIZE	128
50*4882a593Smuzhiyun #define POLL_INTERVAL_MS	1000
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define LT6911UXE_LINK_FREQ_1250M	1250000000
53*4882a593Smuzhiyun #define LT6911UXE_LINK_FREQ_900M	900000000
54*4882a593Smuzhiyun #define LT6911UXE_LINK_FREQ_600M	600000000
55*4882a593Smuzhiyun #define LT6911UXE_LINK_FREQ_450M	450000000
56*4882a593Smuzhiyun #define LT6911UXE_LINK_FREQ_400M	400000000
57*4882a593Smuzhiyun #define LT6911UXE_LINK_FREQ_300M	300000000
58*4882a593Smuzhiyun #define LT6911UXE_LINK_FREQ_200M	200000000
59*4882a593Smuzhiyun #define LT6911UXE_LINK_FREQ_150M	150000000
60*4882a593Smuzhiyun #define LT6911UXE_LINK_FREQ_100M	100000000
61*4882a593Smuzhiyun #define LT6911UXE_PIXEL_RATE		800000000
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define LT6911UXE_CHIPID	0x0221
64*4882a593Smuzhiyun #define CHIPID_REGH		0xe101
65*4882a593Smuzhiyun #define CHIPID_REGL		0xe100
66*4882a593Smuzhiyun #define I2C_EN_REG		0xe0ee
67*4882a593Smuzhiyun #define I2C_ENABLE		0x1
68*4882a593Smuzhiyun #define I2C_DISABLE		0x0
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define HTOTAL_H		0xe088
71*4882a593Smuzhiyun #define HTOTAL_L		0xe089
72*4882a593Smuzhiyun #define HACT_H			0xe08c
73*4882a593Smuzhiyun #define HACT_L			0xe08d
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define VTOTAL_H		0xe08a
76*4882a593Smuzhiyun #define VTOTAL_L		0xe08b
77*4882a593Smuzhiyun #define VACT_H			0xe08e
78*4882a593Smuzhiyun #define VACT_L			0xe08f
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun #define HS_HALF			0xe080
81*4882a593Smuzhiyun #define HFP_HALF_H		0xe081
82*4882a593Smuzhiyun #define HFP_HALF_L		0xe082
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define VS			0xe083
85*4882a593Smuzhiyun #define VFP_H			0xe097
86*4882a593Smuzhiyun #define VFP_L			0xe098
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun #define PCLK_H			0xe085
89*4882a593Smuzhiyun #define PCLK_M			0xe086
90*4882a593Smuzhiyun #define PCLK_L			0xe087
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define BYTE_PCLK_H		0xe092
93*4882a593Smuzhiyun #define BYTE_PCLK_M		0xe093
94*4882a593Smuzhiyun #define BYTE_PCLK_L		0xe094
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun #define AUDIO_FS_VALUE_H	0xe090
97*4882a593Smuzhiyun #define AUDIO_FS_VALUE_L	0xe091
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #define LNAE_NUM		0xe095
100*4882a593Smuzhiyun #define BUS_FMT			0xe096
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #define STREAM_CTL		0xe0b0
103*4882a593Smuzhiyun #define ENABLE_STREAM		0x01
104*4882a593Smuzhiyun #define DISABLE_STREAM		0x00
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun //mipi phy timing
107*4882a593Smuzhiyun #define CLK_ZERO_REG		0xeaa7
108*4882a593Smuzhiyun #define CLK_PRE_REG		0xeaa8
109*4882a593Smuzhiyun #define CLK_POST_REG		0xeaa9
110*4882a593Smuzhiyun #define HS_LPX_REG		0xeaa4
111*4882a593Smuzhiyun #define HS_PREPARE_REG		0xeaa5
112*4882a593Smuzhiyun #define HS_TRAIL		0xeaa6
113*4882a593Smuzhiyun #define HS_RQST_PRE_REG		0xea8a
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun //bit[2:0] mipi hs delay
116*4882a593Smuzhiyun #define MIPI_TX_PT0_TX0_DLY	0xe23a
117*4882a593Smuzhiyun #define MIPI_TX_PT0_TX1_DLY	0xe23b
118*4882a593Smuzhiyun #define MIPI_TX_PT0_TXC_DLY	0xe23c
119*4882a593Smuzhiyun #define MIPI_TX_PT0_TX2_DLY	0xe23d
120*4882a593Smuzhiyun #define MIPI_TX_PT0_TX3_DLY	0xe23e
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun #define MIPI_TX_PT1_TX0_DLY	0xe24a
123*4882a593Smuzhiyun #define MIPI_TX_PT1_TX1_DLY	0xe24b
124*4882a593Smuzhiyun #define MIPI_TX_PT1_TXC_DLY	0xe24c
125*4882a593Smuzhiyun #define MIPI_TX_PT1_TX2_DLY	0xe24d
126*4882a593Smuzhiyun #define MIPI_TX_PT1_TX3_DLY	0xe24e
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun #define MIPI_TIMING_MASK	0x7
129*4882a593Smuzhiyun //LP driver level
130*4882a593Smuzhiyun #define MIPI_TX_PT0_LPTX	0xe234
131*4882a593Smuzhiyun #define MIPI_TX_PT1_LPTX	0xe244
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun // #define LT6911UXE_OUT_RGB
134*4882a593Smuzhiyun #ifdef LT6911UXE_OUT_RGB
135*4882a593Smuzhiyun #define LT6911UXE_MEDIA_BUS_FMT		MEDIA_BUS_FMT_BGR888_1X24
136*4882a593Smuzhiyun #else
137*4882a593Smuzhiyun #define LT6911UXE_MEDIA_BUS_FMT		MEDIA_BUS_FMT_UYVY8_2X8
138*4882a593Smuzhiyun #endif
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun #define LT6911UXE_NAME			"LT6911UXE"
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #ifdef LT6911UXE_OUT_RGB
143*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
144*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_1250M,
145*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_900M,
146*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_600M,
147*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_450M,
148*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_300M,
149*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_150M,
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun #else
152*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
153*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_1250M,
154*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_600M,
155*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_400M,
156*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_300M,
157*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_200M,
158*4882a593Smuzhiyun 	LT6911UXE_LINK_FREQ_100M,
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun #endif
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun struct lt6911uxe {
163*4882a593Smuzhiyun 	struct v4l2_fwnode_bus_mipi_csi2 bus;
164*4882a593Smuzhiyun 	struct v4l2_subdev sd;
165*4882a593Smuzhiyun 	struct media_pad pad;
166*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
167*4882a593Smuzhiyun 	struct i2c_client *i2c_client;
168*4882a593Smuzhiyun 	struct mutex confctl_mutex;
169*4882a593Smuzhiyun 	struct v4l2_ctrl *detect_tx_5v_ctrl;
170*4882a593Smuzhiyun 	struct v4l2_ctrl *audio_sampling_rate_ctrl;
171*4882a593Smuzhiyun 	struct v4l2_ctrl *audio_present_ctrl;
172*4882a593Smuzhiyun 	struct v4l2_ctrl *link_freq;
173*4882a593Smuzhiyun 	struct v4l2_ctrl *pixel_rate;
174*4882a593Smuzhiyun 	struct delayed_work delayed_work_hotplug;
175*4882a593Smuzhiyun 	struct delayed_work delayed_work_res_change;
176*4882a593Smuzhiyun 	struct v4l2_dv_timings timings;
177*4882a593Smuzhiyun 	struct clk *xvclk;
178*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
179*4882a593Smuzhiyun 	struct gpio_desc *plugin_det_gpio;
180*4882a593Smuzhiyun 	struct gpio_desc *power_gpio;
181*4882a593Smuzhiyun 	struct work_struct work_i2c_poll;
182*4882a593Smuzhiyun 	struct timer_list timer;
183*4882a593Smuzhiyun 	const char *module_facing;
184*4882a593Smuzhiyun 	const char *module_name;
185*4882a593Smuzhiyun 	const char *len_name;
186*4882a593Smuzhiyun 	const struct lt6911uxe_mode *cur_mode;
187*4882a593Smuzhiyun 	const struct lt6911uxe_mode *support_modes;
188*4882a593Smuzhiyun 	u32 cfg_num;
189*4882a593Smuzhiyun 	struct v4l2_fwnode_endpoint bus_cfg;
190*4882a593Smuzhiyun 	bool nosignal;
191*4882a593Smuzhiyun 	bool enable_hdcp;
192*4882a593Smuzhiyun 	bool is_audio_present;
193*4882a593Smuzhiyun 	bool power_on;
194*4882a593Smuzhiyun 	int plugin_irq;
195*4882a593Smuzhiyun 	u32 mbus_fmt_code;
196*4882a593Smuzhiyun 	u32 module_index;
197*4882a593Smuzhiyun 	u32 audio_sampling_rate;
198*4882a593Smuzhiyun 	int lane_in_use;
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun static const struct v4l2_dv_timings_cap lt6911uxe_timings_cap = {
202*4882a593Smuzhiyun 	.type = V4L2_DV_BT_656_1120,
203*4882a593Smuzhiyun 	.reserved = { 0 },
204*4882a593Smuzhiyun 	V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 800000000,
205*4882a593Smuzhiyun 			V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
206*4882a593Smuzhiyun 			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
207*4882a593Smuzhiyun 			V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
208*4882a593Smuzhiyun 			V4L2_DV_BT_CAP_REDUCED_BLANKING |
209*4882a593Smuzhiyun 			V4L2_DV_BT_CAP_CUSTOM)
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun struct lt6911uxe_mode {
213*4882a593Smuzhiyun 	u32 width;
214*4882a593Smuzhiyun 	u32 height;
215*4882a593Smuzhiyun 	struct v4l2_fract max_fps;
216*4882a593Smuzhiyun 	u32 hts_def;
217*4882a593Smuzhiyun 	u32 vts_def;
218*4882a593Smuzhiyun 	u32 exp_def;
219*4882a593Smuzhiyun 	u32 mipi_freq_idx;
220*4882a593Smuzhiyun 	u32 interlace;
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
224*4882a593Smuzhiyun 	.vendor = PHY_VENDOR_SAMSUNG,
225*4882a593Smuzhiyun 	.lp_vol_ref = 3,
226*4882a593Smuzhiyun 	.lp_hys_sw = {3, 0, 3, 0},
227*4882a593Smuzhiyun 	.lp_escclk_pol_sel = {1, 1, 0, 0},
228*4882a593Smuzhiyun 	.skew_data_cal_clk = {0, 13, 0, 13},
229*4882a593Smuzhiyun 	.clk_hs_term_sel = 2,
230*4882a593Smuzhiyun 	.data_hs_term_sel = {2, 2, 2, 2},
231*4882a593Smuzhiyun 	.reserved = {0},
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun static const struct lt6911uxe_mode supported_modes_dphy[] = {
235*4882a593Smuzhiyun 	{
236*4882a593Smuzhiyun 		.width = 5120,
237*4882a593Smuzhiyun 		.height = 2160,
238*4882a593Smuzhiyun 		.max_fps = {
239*4882a593Smuzhiyun 			.numerator = 10000,
240*4882a593Smuzhiyun 			.denominator = 480000,
241*4882a593Smuzhiyun 		},
242*4882a593Smuzhiyun 		.hts_def = 5500,
243*4882a593Smuzhiyun 		.vts_def = 2250,
244*4882a593Smuzhiyun 		.mipi_freq_idx = 0,
245*4882a593Smuzhiyun 		.interlace = 0,
246*4882a593Smuzhiyun 	}, {
247*4882a593Smuzhiyun 		.width = 4096,
248*4882a593Smuzhiyun 		.height = 2160,
249*4882a593Smuzhiyun 		.max_fps = {
250*4882a593Smuzhiyun 			.numerator = 10000,
251*4882a593Smuzhiyun 			.denominator = 600000,
252*4882a593Smuzhiyun 		},
253*4882a593Smuzhiyun 		.hts_def = 4400,
254*4882a593Smuzhiyun 		.vts_def = 2250,
255*4882a593Smuzhiyun 		.mipi_freq_idx = 0,
256*4882a593Smuzhiyun 		.interlace = 0,
257*4882a593Smuzhiyun 	}, {
258*4882a593Smuzhiyun 		.width = 4096,
259*4882a593Smuzhiyun 		.height = 2160,
260*4882a593Smuzhiyun 		.max_fps = {
261*4882a593Smuzhiyun 			.numerator = 10000,
262*4882a593Smuzhiyun 			.denominator = 300000,
263*4882a593Smuzhiyun 		},
264*4882a593Smuzhiyun 		.hts_def = 4400,
265*4882a593Smuzhiyun 		.vts_def = 2250,
266*4882a593Smuzhiyun 		.mipi_freq_idx = 1,
267*4882a593Smuzhiyun 		.interlace = 0,
268*4882a593Smuzhiyun 	}, {
269*4882a593Smuzhiyun 		.width = 3840,
270*4882a593Smuzhiyun 		.height = 2160,
271*4882a593Smuzhiyun 		.max_fps = {
272*4882a593Smuzhiyun 			.numerator = 10000,
273*4882a593Smuzhiyun 			.denominator = 600000,
274*4882a593Smuzhiyun 		},
275*4882a593Smuzhiyun 		.hts_def = 4400,
276*4882a593Smuzhiyun 		.vts_def = 2250,
277*4882a593Smuzhiyun 		.mipi_freq_idx = 0,
278*4882a593Smuzhiyun 		.interlace = 0,
279*4882a593Smuzhiyun 	}, {
280*4882a593Smuzhiyun 		.width = 3840,
281*4882a593Smuzhiyun 		.height = 2160,
282*4882a593Smuzhiyun 		.max_fps = {
283*4882a593Smuzhiyun 			.numerator = 10000,
284*4882a593Smuzhiyun 			.denominator = 300000,
285*4882a593Smuzhiyun 		},
286*4882a593Smuzhiyun 		.hts_def = 4400,
287*4882a593Smuzhiyun 		.vts_def = 2250,
288*4882a593Smuzhiyun 		.mipi_freq_idx = 1,
289*4882a593Smuzhiyun 		.interlace = 0,
290*4882a593Smuzhiyun 	}, {
291*4882a593Smuzhiyun 		.width = 1920,
292*4882a593Smuzhiyun 		.height = 1080,
293*4882a593Smuzhiyun 		.max_fps = {
294*4882a593Smuzhiyun 			.numerator = 10000,
295*4882a593Smuzhiyun 			.denominator = 600000,
296*4882a593Smuzhiyun 		},
297*4882a593Smuzhiyun 		.hts_def = 2200,
298*4882a593Smuzhiyun 		.vts_def = 1125,
299*4882a593Smuzhiyun 		.mipi_freq_idx = 3,
300*4882a593Smuzhiyun 		.interlace = 0,
301*4882a593Smuzhiyun 	}, {
302*4882a593Smuzhiyun 		.width = 1920,
303*4882a593Smuzhiyun 		.height = 1200,
304*4882a593Smuzhiyun 		.max_fps = {
305*4882a593Smuzhiyun 			.numerator = 10000,
306*4882a593Smuzhiyun 			.denominator = 600000,
307*4882a593Smuzhiyun 		},
308*4882a593Smuzhiyun 		.hts_def = 2592,
309*4882a593Smuzhiyun 		.vts_def = 1245,
310*4882a593Smuzhiyun 		.mipi_freq_idx = 3,
311*4882a593Smuzhiyun 		.interlace = 0,
312*4882a593Smuzhiyun 	}, {
313*4882a593Smuzhiyun 		.width = 1920,
314*4882a593Smuzhiyun 		.height = 1080,
315*4882a593Smuzhiyun 		.max_fps = {
316*4882a593Smuzhiyun 			.numerator = 10000,
317*4882a593Smuzhiyun 			.denominator = 300000,
318*4882a593Smuzhiyun 		},
319*4882a593Smuzhiyun 		.hts_def = 2200,
320*4882a593Smuzhiyun 		.vts_def = 1125,
321*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
322*4882a593Smuzhiyun 		.interlace = 0,
323*4882a593Smuzhiyun 	}, {
324*4882a593Smuzhiyun 		.width = 1920,
325*4882a593Smuzhiyun 		.height = 1080,
326*4882a593Smuzhiyun 		.max_fps = {
327*4882a593Smuzhiyun 			.numerator = 10000,
328*4882a593Smuzhiyun 			.denominator = 600000,
329*4882a593Smuzhiyun 		},
330*4882a593Smuzhiyun 		.hts_def = 2200,
331*4882a593Smuzhiyun 		.vts_def = 1125,
332*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
333*4882a593Smuzhiyun 		.interlace = 1,
334*4882a593Smuzhiyun 	}, {
335*4882a593Smuzhiyun 		.width = 1680,
336*4882a593Smuzhiyun 		.height = 1050,
337*4882a593Smuzhiyun 		.max_fps = {
338*4882a593Smuzhiyun 			.numerator = 10000,
339*4882a593Smuzhiyun 			.denominator = 600000,
340*4882a593Smuzhiyun 		},
341*4882a593Smuzhiyun 		.hts_def = 2240,
342*4882a593Smuzhiyun 		.vts_def = 1089,
343*4882a593Smuzhiyun 		.mipi_freq_idx = 3,
344*4882a593Smuzhiyun 		.interlace = 0,
345*4882a593Smuzhiyun 	}, {
346*4882a593Smuzhiyun 		.width = 1600,
347*4882a593Smuzhiyun 		.height = 1200,
348*4882a593Smuzhiyun 		.max_fps = {
349*4882a593Smuzhiyun 			.numerator = 10000,
350*4882a593Smuzhiyun 			.denominator = 600000,
351*4882a593Smuzhiyun 		},
352*4882a593Smuzhiyun 		.hts_def = 2160,
353*4882a593Smuzhiyun 		.vts_def = 1250,
354*4882a593Smuzhiyun 		.mipi_freq_idx = 3,
355*4882a593Smuzhiyun 		.interlace = 0,
356*4882a593Smuzhiyun 	}, {
357*4882a593Smuzhiyun 		.width = 1600,
358*4882a593Smuzhiyun 		.height = 900,
359*4882a593Smuzhiyun 		.max_fps = {
360*4882a593Smuzhiyun 			.numerator = 10000,
361*4882a593Smuzhiyun 			.denominator = 600000,
362*4882a593Smuzhiyun 		},
363*4882a593Smuzhiyun 		.hts_def = 1800,
364*4882a593Smuzhiyun 		.vts_def = 1000,
365*4882a593Smuzhiyun 		.mipi_freq_idx = 3,
366*4882a593Smuzhiyun 		.interlace = 0,
367*4882a593Smuzhiyun 	}, {
368*4882a593Smuzhiyun 		.width = 1440,
369*4882a593Smuzhiyun 		.height = 900,
370*4882a593Smuzhiyun 		.max_fps = {
371*4882a593Smuzhiyun 			.numerator = 10000,
372*4882a593Smuzhiyun 			.denominator = 600000,
373*4882a593Smuzhiyun 		},
374*4882a593Smuzhiyun 		.hts_def = 1904,
375*4882a593Smuzhiyun 		.vts_def = 934,
376*4882a593Smuzhiyun 		.mipi_freq_idx = 3,
377*4882a593Smuzhiyun 		.interlace = 0,
378*4882a593Smuzhiyun 	}, {
379*4882a593Smuzhiyun 		.width = 1440,
380*4882a593Smuzhiyun 		.height = 240,
381*4882a593Smuzhiyun 		.max_fps = {
382*4882a593Smuzhiyun 			.numerator = 10000,
383*4882a593Smuzhiyun 			.denominator = 600000,
384*4882a593Smuzhiyun 		},
385*4882a593Smuzhiyun 		.hts_def = 1716,
386*4882a593Smuzhiyun 		.vts_def = 262,
387*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
388*4882a593Smuzhiyun 		.interlace = 0,
389*4882a593Smuzhiyun 	}, {
390*4882a593Smuzhiyun 		.width = 1360,
391*4882a593Smuzhiyun 		.height = 768,
392*4882a593Smuzhiyun 		.max_fps = {
393*4882a593Smuzhiyun 			.numerator = 10000,
394*4882a593Smuzhiyun 			.denominator = 600000,
395*4882a593Smuzhiyun 		},
396*4882a593Smuzhiyun 		.hts_def = 1792,
397*4882a593Smuzhiyun 		.vts_def = 795,
398*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
399*4882a593Smuzhiyun 		.interlace = 0,
400*4882a593Smuzhiyun 	}, {
401*4882a593Smuzhiyun 		.width = 1280,
402*4882a593Smuzhiyun 		.height = 1024,
403*4882a593Smuzhiyun 		.max_fps = {
404*4882a593Smuzhiyun 			.numerator = 10000,
405*4882a593Smuzhiyun 			.denominator = 600000,
406*4882a593Smuzhiyun 		},
407*4882a593Smuzhiyun 		.hts_def = 1688,
408*4882a593Smuzhiyun 		.vts_def = 1066,
409*4882a593Smuzhiyun 		.mipi_freq_idx = 3,
410*4882a593Smuzhiyun 		.interlace = 0,
411*4882a593Smuzhiyun 	}, {
412*4882a593Smuzhiyun 		.width = 1280,
413*4882a593Smuzhiyun 		.height = 960,
414*4882a593Smuzhiyun 		.max_fps = {
415*4882a593Smuzhiyun 			.numerator = 10000,
416*4882a593Smuzhiyun 			.denominator = 600000,
417*4882a593Smuzhiyun 		},
418*4882a593Smuzhiyun 		.hts_def = 1712,
419*4882a593Smuzhiyun 		.vts_def = 994,
420*4882a593Smuzhiyun 		.mipi_freq_idx = 3,
421*4882a593Smuzhiyun 		.interlace = 0,
422*4882a593Smuzhiyun 	}, {
423*4882a593Smuzhiyun 		.width = 1280,
424*4882a593Smuzhiyun 		.height = 800,
425*4882a593Smuzhiyun 		.max_fps = {
426*4882a593Smuzhiyun 			.numerator = 10000,
427*4882a593Smuzhiyun 			.denominator = 600000,
428*4882a593Smuzhiyun 		},
429*4882a593Smuzhiyun 		.hts_def = 1680,
430*4882a593Smuzhiyun 		.vts_def = 828,
431*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
432*4882a593Smuzhiyun 		.interlace = 0,
433*4882a593Smuzhiyun 	}, {
434*4882a593Smuzhiyun 		.width = 1280,
435*4882a593Smuzhiyun 		.height = 768,
436*4882a593Smuzhiyun 		.max_fps = {
437*4882a593Smuzhiyun 			.numerator = 10000,
438*4882a593Smuzhiyun 			.denominator = 600000,
439*4882a593Smuzhiyun 		},
440*4882a593Smuzhiyun 		.hts_def = 1664,
441*4882a593Smuzhiyun 		.vts_def = 798,
442*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
443*4882a593Smuzhiyun 		.interlace = 0,
444*4882a593Smuzhiyun 	}, {
445*4882a593Smuzhiyun 		.width = 1280,
446*4882a593Smuzhiyun 		.height = 720,
447*4882a593Smuzhiyun 		.max_fps = {
448*4882a593Smuzhiyun 			.numerator = 10000,
449*4882a593Smuzhiyun 			.denominator = 600000,
450*4882a593Smuzhiyun 		},
451*4882a593Smuzhiyun 		.hts_def = 1650,
452*4882a593Smuzhiyun 		.vts_def = 750,
453*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
454*4882a593Smuzhiyun 		.interlace = 0,
455*4882a593Smuzhiyun 	}, {
456*4882a593Smuzhiyun 		.width = 1152,
457*4882a593Smuzhiyun 		.height = 864,
458*4882a593Smuzhiyun 		.max_fps = {
459*4882a593Smuzhiyun 			.numerator = 10000,
460*4882a593Smuzhiyun 			.denominator = 750000,
461*4882a593Smuzhiyun 		},
462*4882a593Smuzhiyun 		.hts_def = 1600,
463*4882a593Smuzhiyun 		.vts_def = 900,
464*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
465*4882a593Smuzhiyun 		.interlace = 0,
466*4882a593Smuzhiyun 	}, {
467*4882a593Smuzhiyun 		.width = 1024,
468*4882a593Smuzhiyun 		.height = 768,
469*4882a593Smuzhiyun 		.max_fps = {
470*4882a593Smuzhiyun 			.numerator = 10000,
471*4882a593Smuzhiyun 			.denominator = 600000,
472*4882a593Smuzhiyun 		},
473*4882a593Smuzhiyun 		.hts_def = 1344,
474*4882a593Smuzhiyun 		.vts_def = 806,
475*4882a593Smuzhiyun 		.mipi_freq_idx = 4,
476*4882a593Smuzhiyun 		.interlace = 0,
477*4882a593Smuzhiyun 	}, {
478*4882a593Smuzhiyun 		.width = 800,
479*4882a593Smuzhiyun 		.height = 600,
480*4882a593Smuzhiyun 		.max_fps = {
481*4882a593Smuzhiyun 			.numerator = 10000,
482*4882a593Smuzhiyun 			.denominator = 600000,
483*4882a593Smuzhiyun 		},
484*4882a593Smuzhiyun 		.hts_def = 1056,
485*4882a593Smuzhiyun 		.vts_def = 628,
486*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
487*4882a593Smuzhiyun 		.interlace = 0,
488*4882a593Smuzhiyun 	}, {
489*4882a593Smuzhiyun 		.width = 720,
490*4882a593Smuzhiyun 		.height = 576,
491*4882a593Smuzhiyun 		.max_fps = {
492*4882a593Smuzhiyun 			.numerator = 10000,
493*4882a593Smuzhiyun 			.denominator = 500000,
494*4882a593Smuzhiyun 		},
495*4882a593Smuzhiyun 		.hts_def = 864,
496*4882a593Smuzhiyun 		.vts_def = 625,
497*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
498*4882a593Smuzhiyun 		.interlace = 0,
499*4882a593Smuzhiyun 	}, {
500*4882a593Smuzhiyun 		.width = 720,
501*4882a593Smuzhiyun 		.height = 480,
502*4882a593Smuzhiyun 		.max_fps = {
503*4882a593Smuzhiyun 			.numerator = 10000,
504*4882a593Smuzhiyun 			.denominator = 600000,
505*4882a593Smuzhiyun 		},
506*4882a593Smuzhiyun 		.hts_def = 858,
507*4882a593Smuzhiyun 		.vts_def = 525,
508*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
509*4882a593Smuzhiyun 		.interlace = 0,
510*4882a593Smuzhiyun 	}, {
511*4882a593Smuzhiyun 		.width = 720,
512*4882a593Smuzhiyun 		.height = 400,
513*4882a593Smuzhiyun 		.max_fps = {
514*4882a593Smuzhiyun 			.numerator = 10000,
515*4882a593Smuzhiyun 			.denominator = 850000,
516*4882a593Smuzhiyun 		},
517*4882a593Smuzhiyun 		.hts_def = 936,
518*4882a593Smuzhiyun 		.vts_def = 446,
519*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
520*4882a593Smuzhiyun 		.interlace = 0,
521*4882a593Smuzhiyun 	}, {
522*4882a593Smuzhiyun 		.width = 720,
523*4882a593Smuzhiyun 		.height = 240,
524*4882a593Smuzhiyun 		.max_fps = {
525*4882a593Smuzhiyun 			.numerator = 10000,
526*4882a593Smuzhiyun 			.denominator = 600000,
527*4882a593Smuzhiyun 		},
528*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
529*4882a593Smuzhiyun 		.interlace = 0,
530*4882a593Smuzhiyun 	}, {
531*4882a593Smuzhiyun 		.width = 640,
532*4882a593Smuzhiyun 		.height = 480,
533*4882a593Smuzhiyun 		.max_fps = {
534*4882a593Smuzhiyun 			.numerator = 10000,
535*4882a593Smuzhiyun 			.denominator = 600000,
536*4882a593Smuzhiyun 		},
537*4882a593Smuzhiyun 		.hts_def = 800,
538*4882a593Smuzhiyun 		.vts_def = 525,
539*4882a593Smuzhiyun 		.mipi_freq_idx = 5,
540*4882a593Smuzhiyun 		.interlace = 0,
541*4882a593Smuzhiyun 	},
542*4882a593Smuzhiyun };
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun static void lt6911uxe_format_change(struct v4l2_subdev *sd);
545*4882a593Smuzhiyun static int lt6911uxe_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
546*4882a593Smuzhiyun static int lt6911uxe_s_dv_timings(struct v4l2_subdev *sd,
547*4882a593Smuzhiyun 				struct v4l2_dv_timings *timings);
548*4882a593Smuzhiyun 
to_lt6911uxe(struct v4l2_subdev * sd)549*4882a593Smuzhiyun static inline struct lt6911uxe *to_lt6911uxe(struct v4l2_subdev *sd)
550*4882a593Smuzhiyun {
551*4882a593Smuzhiyun 	return container_of(sd, struct lt6911uxe, sd);
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun 
i2c_rd(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)554*4882a593Smuzhiyun static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
557*4882a593Smuzhiyun 	struct i2c_client *client = lt6911uxe->i2c_client;
558*4882a593Smuzhiyun 	int err;
559*4882a593Smuzhiyun 	u8 buf[2] = { 0xFF, reg >> 8};
560*4882a593Smuzhiyun 	u8 reg_addr = reg & 0xFF;
561*4882a593Smuzhiyun 	struct i2c_msg msgs[3];
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
564*4882a593Smuzhiyun 	msgs[0].flags = 0;
565*4882a593Smuzhiyun 	msgs[0].len = 2;
566*4882a593Smuzhiyun 	msgs[0].buf = buf;
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
569*4882a593Smuzhiyun 	msgs[1].flags = 0;
570*4882a593Smuzhiyun 	msgs[1].len = 1;
571*4882a593Smuzhiyun 	msgs[1].buf = &reg_addr;
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	msgs[2].addr = client->addr;
574*4882a593Smuzhiyun 	msgs[2].flags = I2C_M_RD;
575*4882a593Smuzhiyun 	msgs[2].len = n;
576*4882a593Smuzhiyun 	msgs[2].buf = values;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
579*4882a593Smuzhiyun 	if (err != ARRAY_SIZE(msgs)) {
580*4882a593Smuzhiyun 		v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
581*4882a593Smuzhiyun 				__func__, reg, client->addr);
582*4882a593Smuzhiyun 	}
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	if (!debug)
585*4882a593Smuzhiyun 		return;
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	switch (n) {
588*4882a593Smuzhiyun 	case 1:
589*4882a593Smuzhiyun 		v4l2_info(sd, "I2C read 0x%04x = 0x%02x\n",
590*4882a593Smuzhiyun 			reg, values[0]);
591*4882a593Smuzhiyun 		break;
592*4882a593Smuzhiyun 	case 2:
593*4882a593Smuzhiyun 		v4l2_info(sd, "I2C read 0x%04x = 0x%02x%02x\n",
594*4882a593Smuzhiyun 			reg, values[1], values[0]);
595*4882a593Smuzhiyun 		break;
596*4882a593Smuzhiyun 	case 4:
597*4882a593Smuzhiyun 		v4l2_info(sd, "I2C read 0x%04x = 0x%02x%02x%02x%02x\n",
598*4882a593Smuzhiyun 			reg, values[3], values[2], values[1], values[0]);
599*4882a593Smuzhiyun 		break;
600*4882a593Smuzhiyun 	default:
601*4882a593Smuzhiyun 		v4l2_info(sd, "I2C read %d bytes from address 0x%04x\n",
602*4882a593Smuzhiyun 			n, reg);
603*4882a593Smuzhiyun 	}
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun 
i2c_wr(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)606*4882a593Smuzhiyun static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
607*4882a593Smuzhiyun {
608*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
609*4882a593Smuzhiyun 	struct i2c_client *client = lt6911uxe->i2c_client;
610*4882a593Smuzhiyun 	int err, i;
611*4882a593Smuzhiyun 	struct i2c_msg msgs[2];
612*4882a593Smuzhiyun 	u8 data[I2C_MAX_XFER_SIZE];
613*4882a593Smuzhiyun 	u8 buf[2] = { 0xFF, reg >> 8};
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	if ((1 + n) > I2C_MAX_XFER_SIZE) {
616*4882a593Smuzhiyun 		n = I2C_MAX_XFER_SIZE - 1;
617*4882a593Smuzhiyun 		v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
618*4882a593Smuzhiyun 			  reg, 1 + n);
619*4882a593Smuzhiyun 	}
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
622*4882a593Smuzhiyun 	msgs[0].flags = 0;
623*4882a593Smuzhiyun 	msgs[0].len = 2;
624*4882a593Smuzhiyun 	msgs[0].buf = buf;
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
627*4882a593Smuzhiyun 	msgs[1].flags = 0;
628*4882a593Smuzhiyun 	msgs[1].len = 1 + n;
629*4882a593Smuzhiyun 	msgs[1].buf = data;
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	data[0] = reg & 0xff;
632*4882a593Smuzhiyun 	for (i = 0; i < n; i++)
633*4882a593Smuzhiyun 		data[1 + i] = values[i];
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
636*4882a593Smuzhiyun 	if (err < 0) {
637*4882a593Smuzhiyun 		v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
638*4882a593Smuzhiyun 				__func__, reg, client->addr);
639*4882a593Smuzhiyun 		return;
640*4882a593Smuzhiyun 	}
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun 	if (!debug)
643*4882a593Smuzhiyun 		return;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	switch (n) {
646*4882a593Smuzhiyun 	case 1:
647*4882a593Smuzhiyun 		v4l2_info(sd, "I2C write 0x%04x = 0x%02x\n",
648*4882a593Smuzhiyun 				reg, data[1]);
649*4882a593Smuzhiyun 		break;
650*4882a593Smuzhiyun 	case 2:
651*4882a593Smuzhiyun 		v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x\n",
652*4882a593Smuzhiyun 				reg, data[2], data[1]);
653*4882a593Smuzhiyun 		break;
654*4882a593Smuzhiyun 	case 4:
655*4882a593Smuzhiyun 		v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x\n",
656*4882a593Smuzhiyun 				reg, data[4], data[3], data[2], data[1]);
657*4882a593Smuzhiyun 		break;
658*4882a593Smuzhiyun 	default:
659*4882a593Smuzhiyun 		v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
660*4882a593Smuzhiyun 				n, reg);
661*4882a593Smuzhiyun 	}
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun 
i2c_rd8(struct v4l2_subdev * sd,u16 reg)664*4882a593Smuzhiyun static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
665*4882a593Smuzhiyun {
666*4882a593Smuzhiyun 	u32 val;
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun 	i2c_rd(sd, reg, (u8 __force *)&val, 1);
669*4882a593Smuzhiyun 	return val;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun 
i2c_wr8(struct v4l2_subdev * sd,u16 reg,u8 val)672*4882a593Smuzhiyun static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun 	i2c_wr(sd, reg, &val, 1);
675*4882a593Smuzhiyun }
676*4882a593Smuzhiyun 
i2c_wr8_and_or(struct v4l2_subdev * sd,u16 reg,u32 mask,u8 val)677*4882a593Smuzhiyun static __maybe_unused void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg, u32 mask,
678*4882a593Smuzhiyun 			   u8 val)
679*4882a593Smuzhiyun {
680*4882a593Smuzhiyun 	u8 val_p;
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	val_p = i2c_rd8(sd, reg);
683*4882a593Smuzhiyun 	i2c_wr8(sd, reg, (val_p & mask) | val);
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun 
lt6911uxe_i2c_enable(struct v4l2_subdev * sd)686*4882a593Smuzhiyun static void lt6911uxe_i2c_enable(struct v4l2_subdev *sd)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun 	i2c_wr8(sd, I2C_EN_REG, I2C_ENABLE);
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun 
lt6911uxe_i2c_disable(struct v4l2_subdev * sd)691*4882a593Smuzhiyun static void lt6911uxe_i2c_disable(struct v4l2_subdev *sd)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun 	i2c_wr8(sd, I2C_EN_REG, I2C_DISABLE);
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun 
tx_5v_power_present(struct v4l2_subdev * sd)696*4882a593Smuzhiyun static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun 	bool ret;
699*4882a593Smuzhiyun 	int val, i, cnt;
700*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun 	/* if not use plugin det gpio */
703*4882a593Smuzhiyun 	if (!lt6911uxe->plugin_det_gpio)
704*4882a593Smuzhiyun 		return true;
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	cnt = 0;
707*4882a593Smuzhiyun 	for (i = 0; i < 5; i++) {
708*4882a593Smuzhiyun 		val = gpiod_get_value(lt6911uxe->plugin_det_gpio);
709*4882a593Smuzhiyun 		if (val > 0)
710*4882a593Smuzhiyun 			cnt++;
711*4882a593Smuzhiyun 		usleep_range(500, 600);
712*4882a593Smuzhiyun 	}
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	ret = (cnt >= 4) ? true : false;
715*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: %d\n", __func__, ret);
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	return ret;
718*4882a593Smuzhiyun }
719*4882a593Smuzhiyun 
no_signal(struct v4l2_subdev * sd)720*4882a593Smuzhiyun static inline bool no_signal(struct v4l2_subdev *sd)
721*4882a593Smuzhiyun {
722*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s no signal:%d\n", __func__,
725*4882a593Smuzhiyun 			lt6911uxe->nosignal);
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	return lt6911uxe->nosignal;
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun 
audio_present(struct v4l2_subdev * sd)730*4882a593Smuzhiyun static inline bool audio_present(struct v4l2_subdev *sd)
731*4882a593Smuzhiyun {
732*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun 	return lt6911uxe->is_audio_present;
735*4882a593Smuzhiyun }
736*4882a593Smuzhiyun 
get_audio_sampling_rate(struct v4l2_subdev * sd)737*4882a593Smuzhiyun static int get_audio_sampling_rate(struct v4l2_subdev *sd)
738*4882a593Smuzhiyun {
739*4882a593Smuzhiyun 	static const int code_to_rate[] = {
740*4882a593Smuzhiyun 		44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
741*4882a593Smuzhiyun 		88200, 768000, 96000, 705600, 176400, 0, 192000, 0
742*4882a593Smuzhiyun 	};
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	if (no_signal(sd))
745*4882a593Smuzhiyun 		return 0;
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun 	return code_to_rate[2];
748*4882a593Smuzhiyun }
749*4882a593Smuzhiyun 
fps_calc(const struct v4l2_bt_timings * t)750*4882a593Smuzhiyun static inline unsigned int fps_calc(const struct v4l2_bt_timings *t)
751*4882a593Smuzhiyun {
752*4882a593Smuzhiyun 	if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
753*4882a593Smuzhiyun 		return 0;
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	return DIV_ROUND_CLOSEST((unsigned int)t->pixelclock,
756*4882a593Smuzhiyun 			V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun 
lt6911uxe_rcv_supported_res(struct v4l2_subdev * sd,u32 width,u32 height)759*4882a593Smuzhiyun static bool lt6911uxe_rcv_supported_res(struct v4l2_subdev *sd, u32 width,
760*4882a593Smuzhiyun 		u32 height)
761*4882a593Smuzhiyun {
762*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
763*4882a593Smuzhiyun 	u32 i;
764*4882a593Smuzhiyun 
765*4882a593Smuzhiyun 	for (i = 0; i < lt6911uxe->cfg_num; i++) {
766*4882a593Smuzhiyun 		if ((lt6911uxe->support_modes[i].width == width) &&
767*4882a593Smuzhiyun 		    (lt6911uxe->support_modes[i].height == height)) {
768*4882a593Smuzhiyun 			break;
769*4882a593Smuzhiyun 		}
770*4882a593Smuzhiyun 	}
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun 	if (i == lt6911uxe->cfg_num) {
773*4882a593Smuzhiyun 		v4l2_err(sd, "%s do not support res wxh: %dx%d\n", __func__,
774*4882a593Smuzhiyun 				width, height);
775*4882a593Smuzhiyun 		return false;
776*4882a593Smuzhiyun 	} else {
777*4882a593Smuzhiyun 		return true;
778*4882a593Smuzhiyun 	}
779*4882a593Smuzhiyun }
780*4882a593Smuzhiyun 
lt6911uxe_get_detected_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)781*4882a593Smuzhiyun static int lt6911uxe_get_detected_timings(struct v4l2_subdev *sd,
782*4882a593Smuzhiyun 				     struct v4l2_dv_timings *timings)
783*4882a593Smuzhiyun {
784*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
785*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &timings->bt;
786*4882a593Smuzhiyun 	u32 hact, vact, htotal, vtotal, hs, vs, hbp, vbp, hfp, vfp;
787*4882a593Smuzhiyun 	u32 pixel_clock, fps, halt_pix_clk;
788*4882a593Smuzhiyun 	u8 clk_h, clk_m, clk_l;
789*4882a593Smuzhiyun 	u8 val_h, val_l;
790*4882a593Smuzhiyun 	u32 byte_clk, mipi_clk, mipi_data_rate;
791*4882a593Smuzhiyun 
792*4882a593Smuzhiyun 	memset(timings, 0, sizeof(struct v4l2_dv_timings));
793*4882a593Smuzhiyun 	lt6911uxe_i2c_enable(sd);
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 	clk_h = i2c_rd8(sd, PCLK_H);
796*4882a593Smuzhiyun 	clk_m = i2c_rd8(sd, PCLK_M);
797*4882a593Smuzhiyun 	clk_l = i2c_rd8(sd, PCLK_L);
798*4882a593Smuzhiyun 	halt_pix_clk = ((clk_h << 16) | (clk_m << 8) | clk_l);
799*4882a593Smuzhiyun 	pixel_clock = halt_pix_clk * 1000 * 2;
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	clk_h = i2c_rd8(sd, BYTE_PCLK_H);
802*4882a593Smuzhiyun 	clk_m = i2c_rd8(sd, BYTE_PCLK_M);
803*4882a593Smuzhiyun 	clk_l = i2c_rd8(sd, BYTE_PCLK_L);
804*4882a593Smuzhiyun 	byte_clk = ((clk_h << 16) | (clk_m << 8) | clk_l) * 1000;
805*4882a593Smuzhiyun 	mipi_clk = byte_clk * 4;
806*4882a593Smuzhiyun 	mipi_data_rate = byte_clk * 8;
807*4882a593Smuzhiyun 
808*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, HTOTAL_H);
809*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, HTOTAL_L);
810*4882a593Smuzhiyun 	htotal = ((val_h << 8) | val_l) * 2;
811*4882a593Smuzhiyun 
812*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, VTOTAL_H);
813*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, VTOTAL_L);
814*4882a593Smuzhiyun 	vtotal = (val_h << 8) | val_l;
815*4882a593Smuzhiyun 
816*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, HACT_H);
817*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, HACT_L);
818*4882a593Smuzhiyun 	hact = ((val_h << 8) | val_l) * 2;
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, VACT_H);
821*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, VACT_L);
822*4882a593Smuzhiyun 	vact = (val_h << 8) | val_l;
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun 	hs = i2c_rd8(sd, HS_HALF) * 2;
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, HFP_HALF_H);
827*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, HFP_HALF_L);
828*4882a593Smuzhiyun 	hfp = ((val_h << 8) | val_l) * 2;
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 	hbp = htotal - hact - hs - hfp;
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun 	vs = i2c_rd8(sd, VS);
833*4882a593Smuzhiyun 	val_h = i2c_rd8(sd, VFP_H);
834*4882a593Smuzhiyun 	val_l = i2c_rd8(sd, VFP_L);
835*4882a593Smuzhiyun 	vfp = (val_h << 8) | val_l;
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun 	vbp = vtotal - vact - vs - vfp;
838*4882a593Smuzhiyun 	lt6911uxe_i2c_disable(sd);
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun 	lt6911uxe->nosignal = false;
841*4882a593Smuzhiyun 	lt6911uxe->is_audio_present = true;
842*4882a593Smuzhiyun 	timings->type = V4L2_DV_BT_656_1120;
843*4882a593Smuzhiyun 	bt->interlaced = V4L2_DV_PROGRESSIVE;
844*4882a593Smuzhiyun 	bt->width = hact;
845*4882a593Smuzhiyun 	bt->height = vact;
846*4882a593Smuzhiyun 	bt->vsync = vs;
847*4882a593Smuzhiyun 	bt->hsync = hs;
848*4882a593Smuzhiyun 	bt->hfrontporch = hfp;
849*4882a593Smuzhiyun 	bt->vfrontporch = vfp;
850*4882a593Smuzhiyun 	bt->hbackporch = hbp;
851*4882a593Smuzhiyun 	bt->vbackporch = vbp;
852*4882a593Smuzhiyun 	bt->pixelclock = pixel_clock;
853*4882a593Smuzhiyun 	fps = pixel_clock / (htotal * vtotal);
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun 	/* for interlaced res 1080i 576i 480i*/
856*4882a593Smuzhiyun 	if ((hact == 1920 && vact == 540) || (hact == 1440 && vact == 288)
857*4882a593Smuzhiyun 			|| (hact == 1440 && vact == 240)) {
858*4882a593Smuzhiyun 		bt->interlaced = V4L2_DV_INTERLACED;
859*4882a593Smuzhiyun 		bt->height *= 2;
860*4882a593Smuzhiyun 		bt->il_vsync = bt->vsync + 1;
861*4882a593Smuzhiyun 	} else {
862*4882a593Smuzhiyun 		bt->interlaced = V4L2_DV_PROGRESSIVE;
863*4882a593Smuzhiyun 	}
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun 	if (!lt6911uxe_rcv_supported_res(sd, hact, bt->height)) {
866*4882a593Smuzhiyun 		lt6911uxe->nosignal = true;
867*4882a593Smuzhiyun 		v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
868*4882a593Smuzhiyun 		return -EINVAL;
869*4882a593Smuzhiyun 	}
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun 	v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
872*4882a593Smuzhiyun 			hact, vact, htotal, vtotal, pixel_clock, fps);
873*4882a593Smuzhiyun 	v4l2_info(sd, "byte_clk:%u, mipi_clk:%u, mipi_data_rate:%u\n",
874*4882a593Smuzhiyun 			byte_clk, mipi_clk, mipi_data_rate);
875*4882a593Smuzhiyun 	v4l2_info(sd, "hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d, inerlaced:%d\n",
876*4882a593Smuzhiyun 			bt->hfrontporch, bt->hsync, bt->hbackporch, bt->vfrontporch,
877*4882a593Smuzhiyun 			bt->vsync, bt->vbackporch, bt->interlaced);
878*4882a593Smuzhiyun 
879*4882a593Smuzhiyun 	return 0;
880*4882a593Smuzhiyun }
881*4882a593Smuzhiyun 
lt6911uxe_delayed_work_hotplug(struct work_struct * work)882*4882a593Smuzhiyun static void lt6911uxe_delayed_work_hotplug(struct work_struct *work)
883*4882a593Smuzhiyun {
884*4882a593Smuzhiyun 	struct delayed_work *dwork = to_delayed_work(work);
885*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = container_of(dwork,
886*4882a593Smuzhiyun 			struct lt6911uxe, delayed_work_hotplug);
887*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt6911uxe->sd;
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	lt6911uxe_s_ctrl_detect_tx_5v(sd);
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun 
lt6911uxe_delayed_work_res_change(struct work_struct * work)892*4882a593Smuzhiyun static void lt6911uxe_delayed_work_res_change(struct work_struct *work)
893*4882a593Smuzhiyun {
894*4882a593Smuzhiyun 	struct delayed_work *dwork = to_delayed_work(work);
895*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = container_of(dwork,
896*4882a593Smuzhiyun 			struct lt6911uxe, delayed_work_res_change);
897*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt6911uxe->sd;
898*4882a593Smuzhiyun 
899*4882a593Smuzhiyun 	lt6911uxe_format_change(sd);
900*4882a593Smuzhiyun }
901*4882a593Smuzhiyun 
lt6911uxe_s_ctrl_detect_tx_5v(struct v4l2_subdev * sd)902*4882a593Smuzhiyun static int lt6911uxe_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
903*4882a593Smuzhiyun {
904*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun 	return v4l2_ctrl_s_ctrl(lt6911uxe->detect_tx_5v_ctrl,
907*4882a593Smuzhiyun 			tx_5v_power_present(sd));
908*4882a593Smuzhiyun }
909*4882a593Smuzhiyun 
lt6911uxe_s_ctrl_audio_sampling_rate(struct v4l2_subdev * sd)910*4882a593Smuzhiyun static int lt6911uxe_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
911*4882a593Smuzhiyun {
912*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
913*4882a593Smuzhiyun 
914*4882a593Smuzhiyun 	return v4l2_ctrl_s_ctrl(lt6911uxe->audio_sampling_rate_ctrl,
915*4882a593Smuzhiyun 			get_audio_sampling_rate(sd));
916*4882a593Smuzhiyun }
917*4882a593Smuzhiyun 
lt6911uxe_s_ctrl_audio_present(struct v4l2_subdev * sd)918*4882a593Smuzhiyun static int lt6911uxe_s_ctrl_audio_present(struct v4l2_subdev *sd)
919*4882a593Smuzhiyun {
920*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
921*4882a593Smuzhiyun 
922*4882a593Smuzhiyun 	return v4l2_ctrl_s_ctrl(lt6911uxe->audio_present_ctrl,
923*4882a593Smuzhiyun 			audio_present(sd));
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun 
lt6911uxe_update_controls(struct v4l2_subdev * sd)926*4882a593Smuzhiyun static int lt6911uxe_update_controls(struct v4l2_subdev *sd)
927*4882a593Smuzhiyun {
928*4882a593Smuzhiyun 	int ret = 0;
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun 	ret |= lt6911uxe_s_ctrl_detect_tx_5v(sd);
931*4882a593Smuzhiyun 	ret |= lt6911uxe_s_ctrl_audio_sampling_rate(sd);
932*4882a593Smuzhiyun 	ret |= lt6911uxe_s_ctrl_audio_present(sd);
933*4882a593Smuzhiyun 
934*4882a593Smuzhiyun 	return ret;
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun 
lt6911uxe_config_dphy_timing(struct v4l2_subdev * sd)937*4882a593Smuzhiyun static void lt6911uxe_config_dphy_timing(struct v4l2_subdev *sd)
938*4882a593Smuzhiyun {
939*4882a593Smuzhiyun 	u8 val;
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	val = i2c_rd8(sd, CLK_ZERO_REG);
942*4882a593Smuzhiyun 	i2c_wr8(sd, CLK_ZERO_REG, val);
943*4882a593Smuzhiyun 
944*4882a593Smuzhiyun 	val = i2c_rd8(sd, HS_PREPARE_REG);
945*4882a593Smuzhiyun 	i2c_wr8(sd, HS_PREPARE_REG, val);
946*4882a593Smuzhiyun 
947*4882a593Smuzhiyun 	val = i2c_rd8(sd, HS_TRAIL);
948*4882a593Smuzhiyun 	i2c_wr8(sd, HS_TRAIL, val);
949*4882a593Smuzhiyun 	v4l2_info(sd, "%s: dphy timing: hs trail = %x\n", __func__, val);
950*4882a593Smuzhiyun 
951*4882a593Smuzhiyun 	val = i2c_rd8(sd, MIPI_TX_PT0_TX0_DLY);
952*4882a593Smuzhiyun 	i2c_wr8_and_or(sd, MIPI_TX_PT0_TX0_DLY, ~MIPI_TIMING_MASK, val);
953*4882a593Smuzhiyun 	v4l2_info(sd, "%s: dphy timing: port0 tx0 delay = %x\n", __func__, val);
954*4882a593Smuzhiyun 
955*4882a593Smuzhiyun 	val = i2c_rd8(sd, MIPI_TX_PT0_LPTX);
956*4882a593Smuzhiyun 	i2c_wr8(sd, MIPI_TX_PT0_LPTX, val);
957*4882a593Smuzhiyun 	v4l2_info(sd, "%s: dphy timing: port0 lptx = %x\n", __func__, val);
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 	v4l2_info(sd, "%s: dphy timing config done.\n", __func__);
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun 
enable_stream(struct v4l2_subdev * sd,bool enable)962*4882a593Smuzhiyun static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
963*4882a593Smuzhiyun {
964*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 	lt6911uxe_i2c_enable(sd);
967*4882a593Smuzhiyun 	if (enable) {
968*4882a593Smuzhiyun 		lt6911uxe_config_dphy_timing(sd);
969*4882a593Smuzhiyun 		usleep_range(5000, 6000);
970*4882a593Smuzhiyun 		i2c_wr8(&lt6911uxe->sd, STREAM_CTL, ENABLE_STREAM);
971*4882a593Smuzhiyun 	} else {
972*4882a593Smuzhiyun 		i2c_wr8(&lt6911uxe->sd, STREAM_CTL, DISABLE_STREAM);
973*4882a593Smuzhiyun 	}
974*4882a593Smuzhiyun 	lt6911uxe_i2c_disable(sd);
975*4882a593Smuzhiyun 	msleep(20);
976*4882a593Smuzhiyun 
977*4882a593Smuzhiyun 	v4l2_dbg(2, debug, sd, "%s: %sable\n",
978*4882a593Smuzhiyun 			__func__, enable ? "en" : "dis");
979*4882a593Smuzhiyun }
980*4882a593Smuzhiyun 
lt6911uxe_format_change(struct v4l2_subdev * sd)981*4882a593Smuzhiyun static void lt6911uxe_format_change(struct v4l2_subdev *sd)
982*4882a593Smuzhiyun {
983*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
984*4882a593Smuzhiyun 	struct v4l2_dv_timings timings;
985*4882a593Smuzhiyun 	const struct v4l2_event lt6911uxe_ev_fmt = {
986*4882a593Smuzhiyun 		.type = V4L2_EVENT_SOURCE_CHANGE,
987*4882a593Smuzhiyun 		.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
988*4882a593Smuzhiyun 	};
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun 	if (lt6911uxe_get_detected_timings(sd, &timings)) {
991*4882a593Smuzhiyun 		enable_stream(sd, false);
992*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: No signal\n", __func__);
993*4882a593Smuzhiyun 	}
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun 	if (!v4l2_match_dv_timings(&lt6911uxe->timings, &timings, 0, false)) {
996*4882a593Smuzhiyun 		enable_stream(sd, false);
997*4882a593Smuzhiyun 		/* automatically set timing rather than set by user */
998*4882a593Smuzhiyun 		lt6911uxe_s_dv_timings(sd, &timings);
999*4882a593Smuzhiyun 		v4l2_print_dv_timings(sd->name,
1000*4882a593Smuzhiyun 				"Format_change: New format: ",
1001*4882a593Smuzhiyun 				&timings, false);
1002*4882a593Smuzhiyun 		if (sd->devnode && !lt6911uxe->i2c_client->irq)
1003*4882a593Smuzhiyun 			v4l2_subdev_notify_event(sd, &lt6911uxe_ev_fmt);
1004*4882a593Smuzhiyun 	}
1005*4882a593Smuzhiyun 	if (sd->devnode && lt6911uxe->i2c_client->irq)
1006*4882a593Smuzhiyun 		v4l2_subdev_notify_event(sd, &lt6911uxe_ev_fmt);
1007*4882a593Smuzhiyun }
1008*4882a593Smuzhiyun 
lt6911uxe_isr(struct v4l2_subdev * sd,u32 status,bool * handled)1009*4882a593Smuzhiyun static int lt6911uxe_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1010*4882a593Smuzhiyun {
1011*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1012*4882a593Smuzhiyun 
1013*4882a593Smuzhiyun 	schedule_delayed_work(&lt6911uxe->delayed_work_res_change, HZ / 20);
1014*4882a593Smuzhiyun 	*handled = true;
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	return 0;
1017*4882a593Smuzhiyun }
1018*4882a593Smuzhiyun 
lt6911uxe_res_change_irq_handler(int irq,void * dev_id)1019*4882a593Smuzhiyun static irqreturn_t lt6911uxe_res_change_irq_handler(int irq, void *dev_id)
1020*4882a593Smuzhiyun {
1021*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = dev_id;
1022*4882a593Smuzhiyun 	bool handled;
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	lt6911uxe_isr(&lt6911uxe->sd, 0, &handled);
1025*4882a593Smuzhiyun 
1026*4882a593Smuzhiyun 	return handled ? IRQ_HANDLED : IRQ_NONE;
1027*4882a593Smuzhiyun }
1028*4882a593Smuzhiyun 
plugin_detect_irq_handler(int irq,void * dev_id)1029*4882a593Smuzhiyun static irqreturn_t plugin_detect_irq_handler(int irq, void *dev_id)
1030*4882a593Smuzhiyun {
1031*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = dev_id;
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun 	/* control hpd output level after 25ms */
1034*4882a593Smuzhiyun 	schedule_delayed_work(&lt6911uxe->delayed_work_hotplug,
1035*4882a593Smuzhiyun 			HZ / 40);
1036*4882a593Smuzhiyun 
1037*4882a593Smuzhiyun 	return IRQ_HANDLED;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun 
lt6911uxe_irq_poll_timer(struct timer_list * t)1040*4882a593Smuzhiyun static void lt6911uxe_irq_poll_timer(struct timer_list *t)
1041*4882a593Smuzhiyun {
1042*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = from_timer(lt6911uxe, t, timer);
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun 	schedule_work(&lt6911uxe->work_i2c_poll);
1045*4882a593Smuzhiyun 	mod_timer(&lt6911uxe->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS));
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun 
lt6911uxe_work_i2c_poll(struct work_struct * work)1048*4882a593Smuzhiyun static void lt6911uxe_work_i2c_poll(struct work_struct *work)
1049*4882a593Smuzhiyun {
1050*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = container_of(work,
1051*4882a593Smuzhiyun 			struct lt6911uxe, work_i2c_poll);
1052*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt6911uxe->sd;
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun 	lt6911uxe_format_change(sd);
1055*4882a593Smuzhiyun }
1056*4882a593Smuzhiyun 
lt6911uxe_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1057*4882a593Smuzhiyun static int lt6911uxe_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1058*4882a593Smuzhiyun 				    struct v4l2_event_subscription *sub)
1059*4882a593Smuzhiyun {
1060*4882a593Smuzhiyun 	switch (sub->type) {
1061*4882a593Smuzhiyun 	case V4L2_EVENT_SOURCE_CHANGE:
1062*4882a593Smuzhiyun 		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1063*4882a593Smuzhiyun 	case V4L2_EVENT_CTRL:
1064*4882a593Smuzhiyun 		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1065*4882a593Smuzhiyun 	default:
1066*4882a593Smuzhiyun 		return -EINVAL;
1067*4882a593Smuzhiyun 	}
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun 
lt6911uxe_g_input_status(struct v4l2_subdev * sd,u32 * status)1070*4882a593Smuzhiyun static int lt6911uxe_g_input_status(struct v4l2_subdev *sd, u32 *status)
1071*4882a593Smuzhiyun {
1072*4882a593Smuzhiyun 	*status = 0;
1073*4882a593Smuzhiyun 	*status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1076*4882a593Smuzhiyun 
1077*4882a593Smuzhiyun 	return 0;
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun 
lt6911uxe_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1080*4882a593Smuzhiyun static int lt6911uxe_s_dv_timings(struct v4l2_subdev *sd,
1081*4882a593Smuzhiyun 				 struct v4l2_dv_timings *timings)
1082*4882a593Smuzhiyun {
1083*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1084*4882a593Smuzhiyun 
1085*4882a593Smuzhiyun 	if (!timings)
1086*4882a593Smuzhiyun 		return -EINVAL;
1087*4882a593Smuzhiyun 
1088*4882a593Smuzhiyun 	if (debug)
1089*4882a593Smuzhiyun 		v4l2_print_dv_timings(sd->name, "s_dv_timings: ",
1090*4882a593Smuzhiyun 				timings, false);
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	if (v4l2_match_dv_timings(&lt6911uxe->timings, timings, 0, false)) {
1093*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1094*4882a593Smuzhiyun 		return 0;
1095*4882a593Smuzhiyun 	}
1096*4882a593Smuzhiyun 
1097*4882a593Smuzhiyun 	if (!v4l2_valid_dv_timings(timings,
1098*4882a593Smuzhiyun 				&lt6911uxe_timings_cap, NULL, NULL)) {
1099*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1100*4882a593Smuzhiyun 		return -ERANGE;
1101*4882a593Smuzhiyun 	}
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 	lt6911uxe->timings = *timings;
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 	enable_stream(sd, false);
1106*4882a593Smuzhiyun 
1107*4882a593Smuzhiyun 	return 0;
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun 
lt6911uxe_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1110*4882a593Smuzhiyun static int lt6911uxe_g_dv_timings(struct v4l2_subdev *sd,
1111*4882a593Smuzhiyun 				struct v4l2_dv_timings *timings)
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	*timings = lt6911uxe->timings;
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 	return 0;
1118*4882a593Smuzhiyun }
1119*4882a593Smuzhiyun 
lt6911uxe_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1120*4882a593Smuzhiyun static int lt6911uxe_enum_dv_timings(struct v4l2_subdev *sd,
1121*4882a593Smuzhiyun 				struct v4l2_enum_dv_timings *timings)
1122*4882a593Smuzhiyun {
1123*4882a593Smuzhiyun 	if (timings->pad != 0)
1124*4882a593Smuzhiyun 		return -EINVAL;
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun 	return v4l2_enum_dv_timings_cap(timings,
1127*4882a593Smuzhiyun 			&lt6911uxe_timings_cap, NULL, NULL);
1128*4882a593Smuzhiyun }
1129*4882a593Smuzhiyun 
lt6911uxe_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1130*4882a593Smuzhiyun static int lt6911uxe_query_dv_timings(struct v4l2_subdev *sd,
1131*4882a593Smuzhiyun 				struct v4l2_dv_timings *timings)
1132*4882a593Smuzhiyun {
1133*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1134*4882a593Smuzhiyun 
1135*4882a593Smuzhiyun 	*timings = lt6911uxe->timings;
1136*4882a593Smuzhiyun 	if (debug)
1137*4882a593Smuzhiyun 		v4l2_print_dv_timings(sd->name,
1138*4882a593Smuzhiyun 				"query_dv_timings: ", timings, false);
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 	if (!v4l2_valid_dv_timings(timings, &lt6911uxe_timings_cap, NULL,
1141*4882a593Smuzhiyun 				NULL)) {
1142*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "%s: timings out of range\n",
1143*4882a593Smuzhiyun 				__func__);
1144*4882a593Smuzhiyun 
1145*4882a593Smuzhiyun 		return -ERANGE;
1146*4882a593Smuzhiyun 	}
1147*4882a593Smuzhiyun 
1148*4882a593Smuzhiyun 	return 0;
1149*4882a593Smuzhiyun }
1150*4882a593Smuzhiyun 
lt6911uxe_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1151*4882a593Smuzhiyun static int lt6911uxe_dv_timings_cap(struct v4l2_subdev *sd,
1152*4882a593Smuzhiyun 				struct v4l2_dv_timings_cap *cap)
1153*4882a593Smuzhiyun {
1154*4882a593Smuzhiyun 	if (cap->pad != 0)
1155*4882a593Smuzhiyun 		return -EINVAL;
1156*4882a593Smuzhiyun 
1157*4882a593Smuzhiyun 	*cap = lt6911uxe_timings_cap;
1158*4882a593Smuzhiyun 
1159*4882a593Smuzhiyun 	return 0;
1160*4882a593Smuzhiyun }
1161*4882a593Smuzhiyun 
lt6911uxe_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)1162*4882a593Smuzhiyun static int lt6911uxe_g_mbus_config(struct v4l2_subdev *sd,
1163*4882a593Smuzhiyun 			unsigned int pad, struct v4l2_mbus_config *cfg)
1164*4882a593Smuzhiyun {
1165*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1166*4882a593Smuzhiyun 	u32 lane_num = lt6911uxe->bus_cfg.bus.mipi_csi2.num_data_lanes;
1167*4882a593Smuzhiyun 	u32 val = 0;
1168*4882a593Smuzhiyun 
1169*4882a593Smuzhiyun 	val = 1 << (lane_num - 1) |
1170*4882a593Smuzhiyun 		V4L2_MBUS_CSI2_CHANNEL_0 |
1171*4882a593Smuzhiyun 		V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1172*4882a593Smuzhiyun 
1173*4882a593Smuzhiyun 	cfg->type = lt6911uxe->bus_cfg.bus_type;
1174*4882a593Smuzhiyun 	cfg->flags = val;
1175*4882a593Smuzhiyun 
1176*4882a593Smuzhiyun 	return 0;
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun 
lt6911uxe_s_stream(struct v4l2_subdev * sd,int on)1179*4882a593Smuzhiyun static int lt6911uxe_s_stream(struct v4l2_subdev *sd, int on)
1180*4882a593Smuzhiyun {
1181*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1182*4882a593Smuzhiyun 	struct i2c_client *client = lt6911uxe->i2c_client;
1183*4882a593Smuzhiyun 
1184*4882a593Smuzhiyun 	dev_info(&client->dev, "%s: on: %d, %dx%d%s%d\n", __func__, on,
1185*4882a593Smuzhiyun 				lt6911uxe->cur_mode->width,
1186*4882a593Smuzhiyun 				lt6911uxe->cur_mode->height,
1187*4882a593Smuzhiyun 				lt6911uxe->cur_mode->interlace ? "I" : "P",
1188*4882a593Smuzhiyun 		DIV_ROUND_CLOSEST(lt6911uxe->cur_mode->max_fps.denominator,
1189*4882a593Smuzhiyun 				  lt6911uxe->cur_mode->max_fps.numerator));
1190*4882a593Smuzhiyun 	enable_stream(sd, on);
1191*4882a593Smuzhiyun 
1192*4882a593Smuzhiyun 	return 0;
1193*4882a593Smuzhiyun }
1194*4882a593Smuzhiyun 
lt6911uxe_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1195*4882a593Smuzhiyun static int lt6911uxe_enum_mbus_code(struct v4l2_subdev *sd,
1196*4882a593Smuzhiyun 			struct v4l2_subdev_pad_config *cfg,
1197*4882a593Smuzhiyun 			struct v4l2_subdev_mbus_code_enum *code)
1198*4882a593Smuzhiyun {
1199*4882a593Smuzhiyun 	switch (code->index) {
1200*4882a593Smuzhiyun 	case 0:
1201*4882a593Smuzhiyun 		code->code = LT6911UXE_MEDIA_BUS_FMT;
1202*4882a593Smuzhiyun 		break;
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun 	default:
1205*4882a593Smuzhiyun 		return -EINVAL;
1206*4882a593Smuzhiyun 	}
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun 	return 0;
1209*4882a593Smuzhiyun }
1210*4882a593Smuzhiyun 
lt6911uxe_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1211*4882a593Smuzhiyun static int lt6911uxe_enum_frame_sizes(struct v4l2_subdev *sd,
1212*4882a593Smuzhiyun 				   struct v4l2_subdev_pad_config *cfg,
1213*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_size_enum *fse)
1214*4882a593Smuzhiyun {
1215*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun 	if (fse->index >= lt6911uxe->cfg_num)
1218*4882a593Smuzhiyun 		return -EINVAL;
1219*4882a593Smuzhiyun 
1220*4882a593Smuzhiyun 	if (fse->code != LT6911UXE_MEDIA_BUS_FMT)
1221*4882a593Smuzhiyun 		return -EINVAL;
1222*4882a593Smuzhiyun 
1223*4882a593Smuzhiyun 	fse->min_width  = lt6911uxe->support_modes[fse->index].width;
1224*4882a593Smuzhiyun 	fse->max_width  = lt6911uxe->support_modes[fse->index].width;
1225*4882a593Smuzhiyun 	fse->max_height = lt6911uxe->support_modes[fse->index].height;
1226*4882a593Smuzhiyun 	fse->min_height = lt6911uxe->support_modes[fse->index].height;
1227*4882a593Smuzhiyun 
1228*4882a593Smuzhiyun 	return 0;
1229*4882a593Smuzhiyun }
1230*4882a593Smuzhiyun 
lt6911uxe_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1231*4882a593Smuzhiyun static int lt6911uxe_enum_frame_interval(struct v4l2_subdev *sd,
1232*4882a593Smuzhiyun 				struct v4l2_subdev_pad_config *cfg,
1233*4882a593Smuzhiyun 				struct v4l2_subdev_frame_interval_enum *fie)
1234*4882a593Smuzhiyun {
1235*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	if (fie->index >= lt6911uxe->cfg_num)
1238*4882a593Smuzhiyun 		return -EINVAL;
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 	fie->code = LT6911UXE_MEDIA_BUS_FMT;
1241*4882a593Smuzhiyun 
1242*4882a593Smuzhiyun 	fie->width = lt6911uxe->support_modes[fie->index].width;
1243*4882a593Smuzhiyun 	fie->height = lt6911uxe->support_modes[fie->index].height;
1244*4882a593Smuzhiyun 	fie->interval = lt6911uxe->support_modes[fie->index].max_fps;
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun 	return 0;
1247*4882a593Smuzhiyun }
1248*4882a593Smuzhiyun 
lt6911uxe_get_reso_dist(const struct lt6911uxe_mode * mode,struct v4l2_dv_timings * timings)1249*4882a593Smuzhiyun static int lt6911uxe_get_reso_dist(const struct lt6911uxe_mode *mode,
1250*4882a593Smuzhiyun 				struct v4l2_dv_timings *timings)
1251*4882a593Smuzhiyun {
1252*4882a593Smuzhiyun 	struct v4l2_bt_timings *bt = &timings->bt;
1253*4882a593Smuzhiyun 	u32 cur_fps, dist_fps;
1254*4882a593Smuzhiyun 
1255*4882a593Smuzhiyun 	cur_fps = fps_calc(bt);
1256*4882a593Smuzhiyun 	dist_fps = DIV_ROUND_CLOSEST(mode->max_fps.denominator, mode->max_fps.numerator);
1257*4882a593Smuzhiyun 
1258*4882a593Smuzhiyun 	return abs(mode->width - bt->width) +
1259*4882a593Smuzhiyun 		abs(mode->height - bt->height) + abs(dist_fps - cur_fps);
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun 
1262*4882a593Smuzhiyun static const struct lt6911uxe_mode *
lt6911uxe_find_best_fit(struct lt6911uxe * lt6911uxe)1263*4882a593Smuzhiyun lt6911uxe_find_best_fit(struct lt6911uxe *lt6911uxe)
1264*4882a593Smuzhiyun {
1265*4882a593Smuzhiyun 	int dist;
1266*4882a593Smuzhiyun 	int cur_best_fit = 0;
1267*4882a593Smuzhiyun 	int cur_best_fit_dist = -1;
1268*4882a593Smuzhiyun 	unsigned int i;
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun 	for (i = 0; i < lt6911uxe->cfg_num; i++) {
1271*4882a593Smuzhiyun 		if (lt6911uxe->support_modes[i].interlace == lt6911uxe->timings.bt.interlaced) {
1272*4882a593Smuzhiyun 			dist = lt6911uxe_get_reso_dist(&lt6911uxe->support_modes[i],
1273*4882a593Smuzhiyun 							&lt6911uxe->timings);
1274*4882a593Smuzhiyun 			if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1275*4882a593Smuzhiyun 				cur_best_fit_dist = dist;
1276*4882a593Smuzhiyun 				cur_best_fit = i;
1277*4882a593Smuzhiyun 			}
1278*4882a593Smuzhiyun 		}
1279*4882a593Smuzhiyun 	}
1280*4882a593Smuzhiyun 	dev_info(&lt6911uxe->i2c_client->dev,
1281*4882a593Smuzhiyun 		"find current mode: support_mode[%d], %dx%d%s%dfps\n",
1282*4882a593Smuzhiyun 		cur_best_fit, lt6911uxe->support_modes[cur_best_fit].width,
1283*4882a593Smuzhiyun 		lt6911uxe->support_modes[cur_best_fit].height,
1284*4882a593Smuzhiyun 		lt6911uxe->support_modes[cur_best_fit].interlace ? "I" : "P",
1285*4882a593Smuzhiyun 		DIV_ROUND_CLOSEST(lt6911uxe->support_modes[cur_best_fit].max_fps.denominator,
1286*4882a593Smuzhiyun 		lt6911uxe->support_modes[cur_best_fit].max_fps.numerator));
1287*4882a593Smuzhiyun 
1288*4882a593Smuzhiyun 	return &lt6911uxe->support_modes[cur_best_fit];
1289*4882a593Smuzhiyun }
1290*4882a593Smuzhiyun 
lt6911uxe_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1291*4882a593Smuzhiyun static int lt6911uxe_get_fmt(struct v4l2_subdev *sd,
1292*4882a593Smuzhiyun 			struct v4l2_subdev_pad_config *cfg,
1293*4882a593Smuzhiyun 			struct v4l2_subdev_format *format)
1294*4882a593Smuzhiyun {
1295*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1296*4882a593Smuzhiyun 	const struct lt6911uxe_mode *mode;
1297*4882a593Smuzhiyun 
1298*4882a593Smuzhiyun 	mutex_lock(&lt6911uxe->confctl_mutex);
1299*4882a593Smuzhiyun 	format->format.code = lt6911uxe->mbus_fmt_code;
1300*4882a593Smuzhiyun 	format->format.width = lt6911uxe->timings.bt.width;
1301*4882a593Smuzhiyun 	format->format.height = lt6911uxe->timings.bt.height;
1302*4882a593Smuzhiyun 	format->format.field =
1303*4882a593Smuzhiyun 		lt6911uxe->timings.bt.interlaced ?
1304*4882a593Smuzhiyun 		V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
1305*4882a593Smuzhiyun 	format->format.colorspace = V4L2_COLORSPACE_SRGB;
1306*4882a593Smuzhiyun 	mutex_unlock(&lt6911uxe->confctl_mutex);
1307*4882a593Smuzhiyun 
1308*4882a593Smuzhiyun 	mode = lt6911uxe_find_best_fit(lt6911uxe);
1309*4882a593Smuzhiyun 	lt6911uxe->cur_mode = mode;
1310*4882a593Smuzhiyun 
1311*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl_int64(lt6911uxe->pixel_rate,
1312*4882a593Smuzhiyun 				LT6911UXE_PIXEL_RATE);
1313*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl(lt6911uxe->link_freq,
1314*4882a593Smuzhiyun 				mode->mipi_freq_idx);
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: mode->mipi_freq_idx(%d)", __func__, mode->mipi_freq_idx);
1317*4882a593Smuzhiyun 
1318*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field code:%d\n",
1319*4882a593Smuzhiyun 			__func__, format->format.code, format->format.width,
1320*4882a593Smuzhiyun 			format->format.height, format->format.field);
1321*4882a593Smuzhiyun 
1322*4882a593Smuzhiyun 	return 0;
1323*4882a593Smuzhiyun }
1324*4882a593Smuzhiyun 
lt6911uxe_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1325*4882a593Smuzhiyun static int lt6911uxe_set_fmt(struct v4l2_subdev *sd,
1326*4882a593Smuzhiyun 			struct v4l2_subdev_pad_config *cfg,
1327*4882a593Smuzhiyun 			struct v4l2_subdev_format *format)
1328*4882a593Smuzhiyun {
1329*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1330*4882a593Smuzhiyun 	const struct lt6911uxe_mode *mode;
1331*4882a593Smuzhiyun 
1332*4882a593Smuzhiyun 	/* is overwritten by get_fmt */
1333*4882a593Smuzhiyun 	u32 code = format->format.code;
1334*4882a593Smuzhiyun 	int ret = lt6911uxe_get_fmt(sd, cfg, format);
1335*4882a593Smuzhiyun 
1336*4882a593Smuzhiyun 	format->format.code = code;
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun 	if (ret)
1339*4882a593Smuzhiyun 		return ret;
1340*4882a593Smuzhiyun 
1341*4882a593Smuzhiyun 	switch (code) {
1342*4882a593Smuzhiyun 	case LT6911UXE_MEDIA_BUS_FMT:
1343*4882a593Smuzhiyun 		break;
1344*4882a593Smuzhiyun 
1345*4882a593Smuzhiyun 	default:
1346*4882a593Smuzhiyun 		return -EINVAL;
1347*4882a593Smuzhiyun 	}
1348*4882a593Smuzhiyun 
1349*4882a593Smuzhiyun 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1350*4882a593Smuzhiyun 		return 0;
1351*4882a593Smuzhiyun 
1352*4882a593Smuzhiyun 	lt6911uxe->mbus_fmt_code = format->format.code;
1353*4882a593Smuzhiyun 	mode = lt6911uxe_find_best_fit(lt6911uxe);
1354*4882a593Smuzhiyun 	lt6911uxe->cur_mode = mode;
1355*4882a593Smuzhiyun 
1356*4882a593Smuzhiyun 	enable_stream(sd, false);
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 	return 0;
1359*4882a593Smuzhiyun }
1360*4882a593Smuzhiyun 
lt6911uxe_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1361*4882a593Smuzhiyun static int lt6911uxe_g_frame_interval(struct v4l2_subdev *sd,
1362*4882a593Smuzhiyun 			struct v4l2_subdev_frame_interval *fi)
1363*4882a593Smuzhiyun {
1364*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1365*4882a593Smuzhiyun 	const struct lt6911uxe_mode *mode = lt6911uxe->cur_mode;
1366*4882a593Smuzhiyun 
1367*4882a593Smuzhiyun 	mutex_lock(&lt6911uxe->confctl_mutex);
1368*4882a593Smuzhiyun 	fi->interval = mode->max_fps;
1369*4882a593Smuzhiyun 	mutex_unlock(&lt6911uxe->confctl_mutex);
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 	return 0;
1372*4882a593Smuzhiyun }
1373*4882a593Smuzhiyun 
lt6911uxe_get_module_inf(struct lt6911uxe * lt6911uxe,struct rkmodule_inf * inf)1374*4882a593Smuzhiyun static void lt6911uxe_get_module_inf(struct lt6911uxe *lt6911uxe,
1375*4882a593Smuzhiyun 				  struct rkmodule_inf *inf)
1376*4882a593Smuzhiyun {
1377*4882a593Smuzhiyun 	memset(inf, 0, sizeof(*inf));
1378*4882a593Smuzhiyun 	strscpy(inf->base.sensor, LT6911UXE_NAME, sizeof(inf->base.sensor));
1379*4882a593Smuzhiyun 	strscpy(inf->base.module, lt6911uxe->module_name, sizeof(inf->base.module));
1380*4882a593Smuzhiyun 	strscpy(inf->base.lens, lt6911uxe->len_name, sizeof(inf->base.lens));
1381*4882a593Smuzhiyun }
1382*4882a593Smuzhiyun 
lt6911uxe_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1383*4882a593Smuzhiyun static long lt6911uxe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1384*4882a593Smuzhiyun {
1385*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1386*4882a593Smuzhiyun 	long ret = 0;
1387*4882a593Smuzhiyun 	struct rkmodule_csi_dphy_param *dphy_param;
1388*4882a593Smuzhiyun 
1389*4882a593Smuzhiyun 	switch (cmd) {
1390*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
1391*4882a593Smuzhiyun 		lt6911uxe_get_module_inf(lt6911uxe, (struct rkmodule_inf *)arg);
1392*4882a593Smuzhiyun 		break;
1393*4882a593Smuzhiyun 	case RKMODULE_GET_HDMI_MODE:
1394*4882a593Smuzhiyun 		*(int *)arg = RKMODULE_HDMIIN_MODE;
1395*4882a593Smuzhiyun 		break;
1396*4882a593Smuzhiyun 	case RKMODULE_SET_CSI_DPHY_PARAM:
1397*4882a593Smuzhiyun 		dphy_param = (struct rkmodule_csi_dphy_param *)arg;
1398*4882a593Smuzhiyun 		if (dphy_param->vendor == rk3588_dcphy_param.vendor)
1399*4882a593Smuzhiyun 			rk3588_dcphy_param = *dphy_param;
1400*4882a593Smuzhiyun 		dev_dbg(&lt6911uxe->i2c_client->dev,
1401*4882a593Smuzhiyun 			"sensor set dphy param\n");
1402*4882a593Smuzhiyun 		break;
1403*4882a593Smuzhiyun 	case RKMODULE_GET_CSI_DPHY_PARAM:
1404*4882a593Smuzhiyun 		dphy_param = (struct rkmodule_csi_dphy_param *)arg;
1405*4882a593Smuzhiyun 		if (dphy_param->vendor == rk3588_dcphy_param.vendor)
1406*4882a593Smuzhiyun 			*dphy_param = rk3588_dcphy_param;
1407*4882a593Smuzhiyun 		dev_dbg(&lt6911uxe->i2c_client->dev,
1408*4882a593Smuzhiyun 			"sensor get dphy param\n");
1409*4882a593Smuzhiyun 		break;
1410*4882a593Smuzhiyun 	default:
1411*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
1412*4882a593Smuzhiyun 		break;
1413*4882a593Smuzhiyun 	}
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun 	return ret;
1416*4882a593Smuzhiyun }
1417*4882a593Smuzhiyun 
lt6911uxe_s_power(struct v4l2_subdev * sd,int on)1418*4882a593Smuzhiyun static int lt6911uxe_s_power(struct v4l2_subdev *sd, int on)
1419*4882a593Smuzhiyun {
1420*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1421*4882a593Smuzhiyun 	int ret = 0;
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun 	mutex_lock(&lt6911uxe->confctl_mutex);
1424*4882a593Smuzhiyun 
1425*4882a593Smuzhiyun 	if (lt6911uxe->power_on == !!on)
1426*4882a593Smuzhiyun 		goto unlock_and_return;
1427*4882a593Smuzhiyun 
1428*4882a593Smuzhiyun 	if (on)
1429*4882a593Smuzhiyun 		lt6911uxe->power_on = true;
1430*4882a593Smuzhiyun 	else
1431*4882a593Smuzhiyun 		lt6911uxe->power_on = false;
1432*4882a593Smuzhiyun 
1433*4882a593Smuzhiyun unlock_and_return:
1434*4882a593Smuzhiyun 	mutex_unlock(&lt6911uxe->confctl_mutex);
1435*4882a593Smuzhiyun 
1436*4882a593Smuzhiyun 	return ret;
1437*4882a593Smuzhiyun }
1438*4882a593Smuzhiyun 
1439*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
lt6911uxe_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1440*4882a593Smuzhiyun static long lt6911uxe_compat_ioctl32(struct v4l2_subdev *sd,
1441*4882a593Smuzhiyun 				  unsigned int cmd, unsigned long arg)
1442*4882a593Smuzhiyun {
1443*4882a593Smuzhiyun 	void __user *up = compat_ptr(arg);
1444*4882a593Smuzhiyun 	struct rkmodule_inf *inf;
1445*4882a593Smuzhiyun 	long ret;
1446*4882a593Smuzhiyun 	int *seq;
1447*4882a593Smuzhiyun 	struct rkmodule_csi_dphy_param *dphy_param;
1448*4882a593Smuzhiyun 
1449*4882a593Smuzhiyun 	switch (cmd) {
1450*4882a593Smuzhiyun 	case RKMODULE_GET_MODULE_INFO:
1451*4882a593Smuzhiyun 		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1452*4882a593Smuzhiyun 		if (!inf) {
1453*4882a593Smuzhiyun 			ret = -ENOMEM;
1454*4882a593Smuzhiyun 			return ret;
1455*4882a593Smuzhiyun 		}
1456*4882a593Smuzhiyun 
1457*4882a593Smuzhiyun 		ret = lt6911uxe_ioctl(sd, cmd, inf);
1458*4882a593Smuzhiyun 		if (!ret) {
1459*4882a593Smuzhiyun 			ret = copy_to_user(up, inf, sizeof(*inf));
1460*4882a593Smuzhiyun 			if (ret)
1461*4882a593Smuzhiyun 				ret = -EFAULT;
1462*4882a593Smuzhiyun 		}
1463*4882a593Smuzhiyun 		kfree(inf);
1464*4882a593Smuzhiyun 		break;
1465*4882a593Smuzhiyun 	case RKMODULE_GET_HDMI_MODE:
1466*4882a593Smuzhiyun 		seq = kzalloc(sizeof(*seq), GFP_KERNEL);
1467*4882a593Smuzhiyun 		if (!seq) {
1468*4882a593Smuzhiyun 			ret = -ENOMEM;
1469*4882a593Smuzhiyun 			return ret;
1470*4882a593Smuzhiyun 		}
1471*4882a593Smuzhiyun 
1472*4882a593Smuzhiyun 		ret = lt6911uxe_ioctl(sd, cmd, seq);
1473*4882a593Smuzhiyun 		if (!ret) {
1474*4882a593Smuzhiyun 			ret = copy_to_user(up, seq, sizeof(*seq));
1475*4882a593Smuzhiyun 			if (ret)
1476*4882a593Smuzhiyun 				ret = -EFAULT;
1477*4882a593Smuzhiyun 		}
1478*4882a593Smuzhiyun 		kfree(seq);
1479*4882a593Smuzhiyun 		break;
1480*4882a593Smuzhiyun 	case RKMODULE_SET_CSI_DPHY_PARAM:
1481*4882a593Smuzhiyun 		dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
1482*4882a593Smuzhiyun 		if (!dphy_param) {
1483*4882a593Smuzhiyun 			ret = -ENOMEM;
1484*4882a593Smuzhiyun 			return ret;
1485*4882a593Smuzhiyun 		}
1486*4882a593Smuzhiyun 
1487*4882a593Smuzhiyun 		ret = copy_from_user(dphy_param, up, sizeof(*dphy_param));
1488*4882a593Smuzhiyun 		if (!ret)
1489*4882a593Smuzhiyun 			ret = lt6911uxe_ioctl(sd, cmd, dphy_param);
1490*4882a593Smuzhiyun 		else
1491*4882a593Smuzhiyun 			ret = -EFAULT;
1492*4882a593Smuzhiyun 		kfree(dphy_param);
1493*4882a593Smuzhiyun 		break;
1494*4882a593Smuzhiyun 	case RKMODULE_GET_CSI_DPHY_PARAM:
1495*4882a593Smuzhiyun 		dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
1496*4882a593Smuzhiyun 		if (!dphy_param) {
1497*4882a593Smuzhiyun 			ret = -ENOMEM;
1498*4882a593Smuzhiyun 			return ret;
1499*4882a593Smuzhiyun 		}
1500*4882a593Smuzhiyun 
1501*4882a593Smuzhiyun 		ret = lt6911uxe_ioctl(sd, cmd, dphy_param);
1502*4882a593Smuzhiyun 		if (!ret) {
1503*4882a593Smuzhiyun 			ret = copy_to_user(up, dphy_param, sizeof(*dphy_param));
1504*4882a593Smuzhiyun 			if (ret)
1505*4882a593Smuzhiyun 				ret = -EFAULT;
1506*4882a593Smuzhiyun 		}
1507*4882a593Smuzhiyun 		kfree(dphy_param);
1508*4882a593Smuzhiyun 		break;
1509*4882a593Smuzhiyun 	default:
1510*4882a593Smuzhiyun 		ret = -ENOIOCTLCMD;
1511*4882a593Smuzhiyun 		break;
1512*4882a593Smuzhiyun 	}
1513*4882a593Smuzhiyun 
1514*4882a593Smuzhiyun 	return ret;
1515*4882a593Smuzhiyun }
1516*4882a593Smuzhiyun #endif
1517*4882a593Smuzhiyun 
1518*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
lt6911uxe_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1519*4882a593Smuzhiyun static int lt6911uxe_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1520*4882a593Smuzhiyun {
1521*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1522*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *try_fmt =
1523*4882a593Smuzhiyun 				v4l2_subdev_get_try_format(sd, fh->pad, 0);
1524*4882a593Smuzhiyun 	const struct lt6911uxe_mode *def_mode = &lt6911uxe->support_modes[0];
1525*4882a593Smuzhiyun 
1526*4882a593Smuzhiyun 	mutex_lock(&lt6911uxe->confctl_mutex);
1527*4882a593Smuzhiyun 	/* Initialize try_fmt */
1528*4882a593Smuzhiyun 	try_fmt->width = def_mode->width;
1529*4882a593Smuzhiyun 	try_fmt->height = def_mode->height;
1530*4882a593Smuzhiyun 	try_fmt->code = LT6911UXE_MEDIA_BUS_FMT;
1531*4882a593Smuzhiyun 	try_fmt->field = V4L2_FIELD_NONE;
1532*4882a593Smuzhiyun 	mutex_unlock(&lt6911uxe->confctl_mutex);
1533*4882a593Smuzhiyun 
1534*4882a593Smuzhiyun 	return 0;
1535*4882a593Smuzhiyun }
1536*4882a593Smuzhiyun #endif
1537*4882a593Smuzhiyun 
1538*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1539*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops lt6911uxe_internal_ops = {
1540*4882a593Smuzhiyun 	.open = lt6911uxe_open,
1541*4882a593Smuzhiyun };
1542*4882a593Smuzhiyun #endif
1543*4882a593Smuzhiyun 
1544*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops lt6911uxe_core_ops = {
1545*4882a593Smuzhiyun 	.s_power = lt6911uxe_s_power,
1546*4882a593Smuzhiyun 	.interrupt_service_routine = lt6911uxe_isr,
1547*4882a593Smuzhiyun 	.subscribe_event = lt6911uxe_subscribe_event,
1548*4882a593Smuzhiyun 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
1549*4882a593Smuzhiyun 	.ioctl = lt6911uxe_ioctl,
1550*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1551*4882a593Smuzhiyun 	.compat_ioctl32 = lt6911uxe_compat_ioctl32,
1552*4882a593Smuzhiyun #endif
1553*4882a593Smuzhiyun };
1554*4882a593Smuzhiyun 
1555*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops lt6911uxe_video_ops = {
1556*4882a593Smuzhiyun 	.g_input_status = lt6911uxe_g_input_status,
1557*4882a593Smuzhiyun 	.s_dv_timings = lt6911uxe_s_dv_timings,
1558*4882a593Smuzhiyun 	.g_dv_timings = lt6911uxe_g_dv_timings,
1559*4882a593Smuzhiyun 	.query_dv_timings = lt6911uxe_query_dv_timings,
1560*4882a593Smuzhiyun 	.s_stream = lt6911uxe_s_stream,
1561*4882a593Smuzhiyun 	.g_frame_interval = lt6911uxe_g_frame_interval,
1562*4882a593Smuzhiyun };
1563*4882a593Smuzhiyun 
1564*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops lt6911uxe_pad_ops = {
1565*4882a593Smuzhiyun 	.enum_mbus_code = lt6911uxe_enum_mbus_code,
1566*4882a593Smuzhiyun 	.enum_frame_size = lt6911uxe_enum_frame_sizes,
1567*4882a593Smuzhiyun 	.enum_frame_interval = lt6911uxe_enum_frame_interval,
1568*4882a593Smuzhiyun 	.set_fmt = lt6911uxe_set_fmt,
1569*4882a593Smuzhiyun 	.get_fmt = lt6911uxe_get_fmt,
1570*4882a593Smuzhiyun 	.enum_dv_timings = lt6911uxe_enum_dv_timings,
1571*4882a593Smuzhiyun 	.dv_timings_cap = lt6911uxe_dv_timings_cap,
1572*4882a593Smuzhiyun 	.get_mbus_config = lt6911uxe_g_mbus_config,
1573*4882a593Smuzhiyun };
1574*4882a593Smuzhiyun 
1575*4882a593Smuzhiyun static const struct v4l2_subdev_ops lt6911uxe_ops = {
1576*4882a593Smuzhiyun 	.core = &lt6911uxe_core_ops,
1577*4882a593Smuzhiyun 	.video = &lt6911uxe_video_ops,
1578*4882a593Smuzhiyun 	.pad = &lt6911uxe_pad_ops,
1579*4882a593Smuzhiyun };
1580*4882a593Smuzhiyun 
1581*4882a593Smuzhiyun static const struct v4l2_ctrl_config lt6911uxe_ctrl_audio_sampling_rate = {
1582*4882a593Smuzhiyun 	.id = RK_V4L2_CID_AUDIO_SAMPLING_RATE,
1583*4882a593Smuzhiyun 	.name = "Audio sampling rate",
1584*4882a593Smuzhiyun 	.type = V4L2_CTRL_TYPE_INTEGER,
1585*4882a593Smuzhiyun 	.min = 0,
1586*4882a593Smuzhiyun 	.max = 768000,
1587*4882a593Smuzhiyun 	.step = 1,
1588*4882a593Smuzhiyun 	.def = 0,
1589*4882a593Smuzhiyun 	.flags = V4L2_CTRL_FLAG_READ_ONLY,
1590*4882a593Smuzhiyun };
1591*4882a593Smuzhiyun 
1592*4882a593Smuzhiyun static const struct v4l2_ctrl_config lt6911uxe_ctrl_audio_present = {
1593*4882a593Smuzhiyun 	.id = RK_V4L2_CID_AUDIO_PRESENT,
1594*4882a593Smuzhiyun 	.name = "Audio present",
1595*4882a593Smuzhiyun 	.type = V4L2_CTRL_TYPE_BOOLEAN,
1596*4882a593Smuzhiyun 	.min = 0,
1597*4882a593Smuzhiyun 	.max = 1,
1598*4882a593Smuzhiyun 	.step = 1,
1599*4882a593Smuzhiyun 	.def = 0,
1600*4882a593Smuzhiyun 	.flags = V4L2_CTRL_FLAG_READ_ONLY,
1601*4882a593Smuzhiyun };
1602*4882a593Smuzhiyun 
lt6911uxe_reset(struct lt6911uxe * lt6911uxe)1603*4882a593Smuzhiyun static void lt6911uxe_reset(struct lt6911uxe *lt6911uxe)
1604*4882a593Smuzhiyun {
1605*4882a593Smuzhiyun 	gpiod_set_value(lt6911uxe->reset_gpio, 0);
1606*4882a593Smuzhiyun 	usleep_range(2000, 2100);
1607*4882a593Smuzhiyun 	gpiod_set_value(lt6911uxe->reset_gpio, 1);
1608*4882a593Smuzhiyun 	usleep_range(120*1000, 121*1000);
1609*4882a593Smuzhiyun 	gpiod_set_value(lt6911uxe->reset_gpio, 0);
1610*4882a593Smuzhiyun 	usleep_range(300*1000, 310*1000);
1611*4882a593Smuzhiyun }
1612*4882a593Smuzhiyun 
lt6911uxe_init_v4l2_ctrls(struct lt6911uxe * lt6911uxe)1613*4882a593Smuzhiyun static int lt6911uxe_init_v4l2_ctrls(struct lt6911uxe *lt6911uxe)
1614*4882a593Smuzhiyun {
1615*4882a593Smuzhiyun 	const struct lt6911uxe_mode *mode;
1616*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1617*4882a593Smuzhiyun 	int ret;
1618*4882a593Smuzhiyun 
1619*4882a593Smuzhiyun 	mode = lt6911uxe->cur_mode;
1620*4882a593Smuzhiyun 	sd = &lt6911uxe->sd;
1621*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(&lt6911uxe->hdl, 5);
1622*4882a593Smuzhiyun 	if (ret)
1623*4882a593Smuzhiyun 		return ret;
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun 	lt6911uxe->link_freq = v4l2_ctrl_new_int_menu(&lt6911uxe->hdl, NULL,
1626*4882a593Smuzhiyun 			V4L2_CID_LINK_FREQ,
1627*4882a593Smuzhiyun 			ARRAY_SIZE(link_freq_menu_items) - 1, 0,
1628*4882a593Smuzhiyun 			link_freq_menu_items);
1629*4882a593Smuzhiyun 	lt6911uxe->pixel_rate = v4l2_ctrl_new_std(&lt6911uxe->hdl, NULL,
1630*4882a593Smuzhiyun 			V4L2_CID_PIXEL_RATE,
1631*4882a593Smuzhiyun 			0, LT6911UXE_PIXEL_RATE, 1, LT6911UXE_PIXEL_RATE);
1632*4882a593Smuzhiyun 
1633*4882a593Smuzhiyun 	lt6911uxe->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&lt6911uxe->hdl,
1634*4882a593Smuzhiyun 			NULL, V4L2_CID_DV_RX_POWER_PRESENT,
1635*4882a593Smuzhiyun 			0, 1, 0, 0);
1636*4882a593Smuzhiyun 
1637*4882a593Smuzhiyun 	lt6911uxe->audio_sampling_rate_ctrl =
1638*4882a593Smuzhiyun 		v4l2_ctrl_new_custom(&lt6911uxe->hdl,
1639*4882a593Smuzhiyun 				&lt6911uxe_ctrl_audio_sampling_rate, NULL);
1640*4882a593Smuzhiyun 	lt6911uxe->audio_present_ctrl = v4l2_ctrl_new_custom(&lt6911uxe->hdl,
1641*4882a593Smuzhiyun 			&lt6911uxe_ctrl_audio_present, NULL);
1642*4882a593Smuzhiyun 
1643*4882a593Smuzhiyun 	sd->ctrl_handler = &lt6911uxe->hdl;
1644*4882a593Smuzhiyun 	if (lt6911uxe->hdl.error) {
1645*4882a593Smuzhiyun 		ret = lt6911uxe->hdl.error;
1646*4882a593Smuzhiyun 		v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret);
1647*4882a593Smuzhiyun 		return ret;
1648*4882a593Smuzhiyun 	}
1649*4882a593Smuzhiyun 
1650*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl(lt6911uxe->link_freq, mode->mipi_freq_idx);
1651*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl_int64(lt6911uxe->pixel_rate, LT6911UXE_PIXEL_RATE);
1652*4882a593Smuzhiyun 
1653*4882a593Smuzhiyun 	if (lt6911uxe_update_controls(sd)) {
1654*4882a593Smuzhiyun 		ret = -ENODEV;
1655*4882a593Smuzhiyun 		v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret);
1656*4882a593Smuzhiyun 		return ret;
1657*4882a593Smuzhiyun 	}
1658*4882a593Smuzhiyun 
1659*4882a593Smuzhiyun 	return 0;
1660*4882a593Smuzhiyun }
1661*4882a593Smuzhiyun 
1662*4882a593Smuzhiyun #ifdef CONFIG_OF
lt6911uxe_probe_of(struct lt6911uxe * lt6911uxe)1663*4882a593Smuzhiyun static int lt6911uxe_probe_of(struct lt6911uxe *lt6911uxe)
1664*4882a593Smuzhiyun {
1665*4882a593Smuzhiyun 	struct device *dev = &lt6911uxe->i2c_client->dev;
1666*4882a593Smuzhiyun 	struct device_node *node = dev->of_node;
1667*4882a593Smuzhiyun 	struct device_node *ep;
1668*4882a593Smuzhiyun 	int ret;
1669*4882a593Smuzhiyun 
1670*4882a593Smuzhiyun 	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1671*4882a593Smuzhiyun 			&lt6911uxe->module_index);
1672*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1673*4882a593Smuzhiyun 			&lt6911uxe->module_facing);
1674*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1675*4882a593Smuzhiyun 			&lt6911uxe->module_name);
1676*4882a593Smuzhiyun 	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1677*4882a593Smuzhiyun 			&lt6911uxe->len_name);
1678*4882a593Smuzhiyun 	if (ret) {
1679*4882a593Smuzhiyun 		dev_err(dev, "could not get module information!\n");
1680*4882a593Smuzhiyun 		return -EINVAL;
1681*4882a593Smuzhiyun 	}
1682*4882a593Smuzhiyun 
1683*4882a593Smuzhiyun 	lt6911uxe->power_gpio = devm_gpiod_get_optional(dev, "power",
1684*4882a593Smuzhiyun 			GPIOD_OUT_LOW);
1685*4882a593Smuzhiyun 	if (IS_ERR(lt6911uxe->power_gpio)) {
1686*4882a593Smuzhiyun 		dev_err(dev, "failed to get power gpio\n");
1687*4882a593Smuzhiyun 		ret = PTR_ERR(lt6911uxe->power_gpio);
1688*4882a593Smuzhiyun 		return ret;
1689*4882a593Smuzhiyun 	}
1690*4882a593Smuzhiyun 
1691*4882a593Smuzhiyun 	lt6911uxe->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1692*4882a593Smuzhiyun 			GPIOD_OUT_HIGH);
1693*4882a593Smuzhiyun 	if (IS_ERR(lt6911uxe->reset_gpio)) {
1694*4882a593Smuzhiyun 		dev_err(dev, "failed to get reset gpio\n");
1695*4882a593Smuzhiyun 		ret = PTR_ERR(lt6911uxe->reset_gpio);
1696*4882a593Smuzhiyun 		return ret;
1697*4882a593Smuzhiyun 	}
1698*4882a593Smuzhiyun 
1699*4882a593Smuzhiyun 	lt6911uxe->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
1700*4882a593Smuzhiyun 			GPIOD_IN);
1701*4882a593Smuzhiyun 	if (IS_ERR(lt6911uxe->plugin_det_gpio)) {
1702*4882a593Smuzhiyun 		dev_err(dev, "failed to get plugin det gpio\n");
1703*4882a593Smuzhiyun 		ret = PTR_ERR(lt6911uxe->plugin_det_gpio);
1704*4882a593Smuzhiyun 		return ret;
1705*4882a593Smuzhiyun 	}
1706*4882a593Smuzhiyun 
1707*4882a593Smuzhiyun 	ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1708*4882a593Smuzhiyun 	if (!ep) {
1709*4882a593Smuzhiyun 		dev_err(dev, "missing endpoint node\n");
1710*4882a593Smuzhiyun 		return -EINVAL;
1711*4882a593Smuzhiyun 	}
1712*4882a593Smuzhiyun 
1713*4882a593Smuzhiyun 	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep),
1714*4882a593Smuzhiyun 					&lt6911uxe->bus_cfg);
1715*4882a593Smuzhiyun 	if (ret) {
1716*4882a593Smuzhiyun 		dev_err(dev, "failed to parse endpoint\n");
1717*4882a593Smuzhiyun 		goto put_node;
1718*4882a593Smuzhiyun 	}
1719*4882a593Smuzhiyun 
1720*4882a593Smuzhiyun 	lt6911uxe->support_modes = supported_modes_dphy;
1721*4882a593Smuzhiyun 	lt6911uxe->cfg_num = ARRAY_SIZE(supported_modes_dphy);
1722*4882a593Smuzhiyun 
1723*4882a593Smuzhiyun 	lt6911uxe->xvclk = devm_clk_get(dev, "xvclk");
1724*4882a593Smuzhiyun 	if (IS_ERR(lt6911uxe->xvclk)) {
1725*4882a593Smuzhiyun 		dev_err(dev, "failed to get xvclk\n");
1726*4882a593Smuzhiyun 		ret = -EINVAL;
1727*4882a593Smuzhiyun 		goto put_node;
1728*4882a593Smuzhiyun 	}
1729*4882a593Smuzhiyun 
1730*4882a593Smuzhiyun 	ret = clk_prepare_enable(lt6911uxe->xvclk);
1731*4882a593Smuzhiyun 	if (ret) {
1732*4882a593Smuzhiyun 		dev_err(dev, "Failed! to enable xvclk\n");
1733*4882a593Smuzhiyun 		goto put_node;
1734*4882a593Smuzhiyun 	}
1735*4882a593Smuzhiyun 
1736*4882a593Smuzhiyun 	lt6911uxe->enable_hdcp = false;
1737*4882a593Smuzhiyun 
1738*4882a593Smuzhiyun 	gpiod_set_value(lt6911uxe->power_gpio, 1);
1739*4882a593Smuzhiyun 	lt6911uxe_reset(lt6911uxe);
1740*4882a593Smuzhiyun 
1741*4882a593Smuzhiyun 	ret = 0;
1742*4882a593Smuzhiyun 
1743*4882a593Smuzhiyun put_node:
1744*4882a593Smuzhiyun 	of_node_put(ep);
1745*4882a593Smuzhiyun 	return ret;
1746*4882a593Smuzhiyun }
1747*4882a593Smuzhiyun #else
lt6911uxe_probe_of(struct lt6911uxe * state)1748*4882a593Smuzhiyun static inline int lt6911uxe_probe_of(struct lt6911uxe *state)
1749*4882a593Smuzhiyun {
1750*4882a593Smuzhiyun 	return -ENODEV;
1751*4882a593Smuzhiyun }
1752*4882a593Smuzhiyun #endif
lt6911uxe_check_chip_id(struct lt6911uxe * lt6911uxe)1753*4882a593Smuzhiyun static int lt6911uxe_check_chip_id(struct lt6911uxe *lt6911uxe)
1754*4882a593Smuzhiyun {
1755*4882a593Smuzhiyun 	struct device *dev = &lt6911uxe->i2c_client->dev;
1756*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &lt6911uxe->sd;
1757*4882a593Smuzhiyun 	u8 id_h, id_l;
1758*4882a593Smuzhiyun 	u32 chipid;
1759*4882a593Smuzhiyun 	int ret = 0;
1760*4882a593Smuzhiyun 
1761*4882a593Smuzhiyun 	lt6911uxe_i2c_enable(sd);
1762*4882a593Smuzhiyun 	id_l  = i2c_rd8(sd, CHIPID_REGL);
1763*4882a593Smuzhiyun 	id_h  = i2c_rd8(sd, CHIPID_REGH);
1764*4882a593Smuzhiyun 	lt6911uxe_i2c_disable(sd);
1765*4882a593Smuzhiyun 
1766*4882a593Smuzhiyun 	chipid = (id_h << 8) | id_l;
1767*4882a593Smuzhiyun 	if (chipid != LT6911UXE_CHIPID) {
1768*4882a593Smuzhiyun 		dev_err(dev, "chipid err, read:%#x, expect:%#x\n",
1769*4882a593Smuzhiyun 				chipid, LT6911UXE_CHIPID);
1770*4882a593Smuzhiyun 		return -EINVAL;
1771*4882a593Smuzhiyun 	}
1772*4882a593Smuzhiyun 	dev_info(dev, "check chipid ok, id:%#x", chipid);
1773*4882a593Smuzhiyun 
1774*4882a593Smuzhiyun 	return ret;
1775*4882a593Smuzhiyun }
1776*4882a593Smuzhiyun 
lt6911uxe_probe(struct i2c_client * client,const struct i2c_device_id * id)1777*4882a593Smuzhiyun static int lt6911uxe_probe(struct i2c_client *client,
1778*4882a593Smuzhiyun 			  const struct i2c_device_id *id)
1779*4882a593Smuzhiyun {
1780*4882a593Smuzhiyun 	struct v4l2_dv_timings default_timing =
1781*4882a593Smuzhiyun 				V4L2_DV_BT_CEA_640X480P59_94;
1782*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe;
1783*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
1784*4882a593Smuzhiyun 	struct device *dev = &client->dev;
1785*4882a593Smuzhiyun 	char facing[2];
1786*4882a593Smuzhiyun 	int err;
1787*4882a593Smuzhiyun 
1788*4882a593Smuzhiyun 	dev_info(dev, "driver version: %02x.%02x.%02x",
1789*4882a593Smuzhiyun 		DRIVER_VERSION >> 16,
1790*4882a593Smuzhiyun 		(DRIVER_VERSION & 0xff00) >> 8,
1791*4882a593Smuzhiyun 		DRIVER_VERSION & 0x00ff);
1792*4882a593Smuzhiyun 
1793*4882a593Smuzhiyun 	lt6911uxe = devm_kzalloc(dev, sizeof(struct lt6911uxe), GFP_KERNEL);
1794*4882a593Smuzhiyun 	if (!lt6911uxe)
1795*4882a593Smuzhiyun 		return -ENOMEM;
1796*4882a593Smuzhiyun 
1797*4882a593Smuzhiyun 	sd = &lt6911uxe->sd;
1798*4882a593Smuzhiyun 	lt6911uxe->i2c_client = client;
1799*4882a593Smuzhiyun 	lt6911uxe->mbus_fmt_code = LT6911UXE_MEDIA_BUS_FMT;
1800*4882a593Smuzhiyun 
1801*4882a593Smuzhiyun 	err = lt6911uxe_probe_of(lt6911uxe);
1802*4882a593Smuzhiyun 	if (err) {
1803*4882a593Smuzhiyun 		v4l2_err(sd, "lt6911uxe_parse_of failed! err:%d\n", err);
1804*4882a593Smuzhiyun 		return err;
1805*4882a593Smuzhiyun 	}
1806*4882a593Smuzhiyun 
1807*4882a593Smuzhiyun 	lt6911uxe->timings = default_timing;
1808*4882a593Smuzhiyun 	lt6911uxe->cur_mode = &lt6911uxe->support_modes[0];
1809*4882a593Smuzhiyun 	err = lt6911uxe_check_chip_id(lt6911uxe);
1810*4882a593Smuzhiyun 	if (err < 0)
1811*4882a593Smuzhiyun 		return err;
1812*4882a593Smuzhiyun 
1813*4882a593Smuzhiyun 	mutex_init(&lt6911uxe->confctl_mutex);
1814*4882a593Smuzhiyun 	err = lt6911uxe_init_v4l2_ctrls(lt6911uxe);
1815*4882a593Smuzhiyun 	if (err)
1816*4882a593Smuzhiyun 		goto err_free_hdl;
1817*4882a593Smuzhiyun 
1818*4882a593Smuzhiyun 	client->flags |= I2C_CLIENT_SCCB;
1819*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1820*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &lt6911uxe_ops);
1821*4882a593Smuzhiyun 	sd->internal_ops = &lt6911uxe_internal_ops;
1822*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1823*4882a593Smuzhiyun #endif
1824*4882a593Smuzhiyun 
1825*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1826*4882a593Smuzhiyun 	lt6911uxe->pad.flags = MEDIA_PAD_FL_SOURCE;
1827*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1828*4882a593Smuzhiyun 	err = media_entity_pads_init(&sd->entity, 1, &lt6911uxe->pad);
1829*4882a593Smuzhiyun 	if (err < 0) {
1830*4882a593Smuzhiyun 		v4l2_err(sd, "media entity init failed! err:%d\n", err);
1831*4882a593Smuzhiyun 		goto err_free_hdl;
1832*4882a593Smuzhiyun 	}
1833*4882a593Smuzhiyun #endif
1834*4882a593Smuzhiyun 	memset(facing, 0, sizeof(facing));
1835*4882a593Smuzhiyun 	if (strcmp(lt6911uxe->module_facing, "back") == 0)
1836*4882a593Smuzhiyun 		facing[0] = 'b';
1837*4882a593Smuzhiyun 	else
1838*4882a593Smuzhiyun 		facing[0] = 'f';
1839*4882a593Smuzhiyun 
1840*4882a593Smuzhiyun 	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1841*4882a593Smuzhiyun 		 lt6911uxe->module_index, facing,
1842*4882a593Smuzhiyun 		 LT6911UXE_NAME, dev_name(sd->dev));
1843*4882a593Smuzhiyun 	err = v4l2_async_register_subdev_sensor_common(sd);
1844*4882a593Smuzhiyun 	if (err < 0) {
1845*4882a593Smuzhiyun 		v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
1846*4882a593Smuzhiyun 		goto err_clean_entity;
1847*4882a593Smuzhiyun 	}
1848*4882a593Smuzhiyun 
1849*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&lt6911uxe->delayed_work_hotplug,
1850*4882a593Smuzhiyun 			lt6911uxe_delayed_work_hotplug);
1851*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&lt6911uxe->delayed_work_res_change,
1852*4882a593Smuzhiyun 			lt6911uxe_delayed_work_res_change);
1853*4882a593Smuzhiyun 
1854*4882a593Smuzhiyun 	if (lt6911uxe->i2c_client->irq) {
1855*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "cfg lt6911uxe irq!\n");
1856*4882a593Smuzhiyun 		err = devm_request_threaded_irq(dev,
1857*4882a593Smuzhiyun 				lt6911uxe->i2c_client->irq,
1858*4882a593Smuzhiyun 				NULL, lt6911uxe_res_change_irq_handler,
1859*4882a593Smuzhiyun 				IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1860*4882a593Smuzhiyun 				"lt6911uxe", lt6911uxe);
1861*4882a593Smuzhiyun 		if (err) {
1862*4882a593Smuzhiyun 			v4l2_err(sd, "request irq failed! err:%d\n", err);
1863*4882a593Smuzhiyun 			goto err_work_queues;
1864*4882a593Smuzhiyun 		}
1865*4882a593Smuzhiyun 	} else {
1866*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "no irq, cfg poll!\n");
1867*4882a593Smuzhiyun 		INIT_WORK(&lt6911uxe->work_i2c_poll, lt6911uxe_work_i2c_poll);
1868*4882a593Smuzhiyun 		timer_setup(&lt6911uxe->timer, lt6911uxe_irq_poll_timer, 0);
1869*4882a593Smuzhiyun 		lt6911uxe->timer.expires = jiffies +
1870*4882a593Smuzhiyun 				       msecs_to_jiffies(POLL_INTERVAL_MS);
1871*4882a593Smuzhiyun 		add_timer(&lt6911uxe->timer);
1872*4882a593Smuzhiyun 	}
1873*4882a593Smuzhiyun 
1874*4882a593Smuzhiyun 	lt6911uxe->plugin_irq = gpiod_to_irq(lt6911uxe->plugin_det_gpio);
1875*4882a593Smuzhiyun 	if (lt6911uxe->plugin_irq < 0)
1876*4882a593Smuzhiyun 		dev_err(dev, "failed to get plugin det irq, maybe no use\n");
1877*4882a593Smuzhiyun 
1878*4882a593Smuzhiyun 	err = devm_request_threaded_irq(dev, lt6911uxe->plugin_irq, NULL,
1879*4882a593Smuzhiyun 			plugin_detect_irq_handler, IRQF_TRIGGER_FALLING |
1880*4882a593Smuzhiyun 			IRQF_TRIGGER_RISING | IRQF_ONESHOT, "lt6911uxe",
1881*4882a593Smuzhiyun 			lt6911uxe);
1882*4882a593Smuzhiyun 	if (err)
1883*4882a593Smuzhiyun 		dev_err(dev, "failed to register plugin det irq (%d), maybe no use\n", err);
1884*4882a593Smuzhiyun 
1885*4882a593Smuzhiyun 	err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1886*4882a593Smuzhiyun 	if (err) {
1887*4882a593Smuzhiyun 		v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
1888*4882a593Smuzhiyun 		goto err_work_queues;
1889*4882a593Smuzhiyun 	}
1890*4882a593Smuzhiyun 	enable_stream(sd, false);
1891*4882a593Smuzhiyun 	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1892*4882a593Smuzhiyun 			client->addr << 1, client->adapter->name);
1893*4882a593Smuzhiyun 
1894*4882a593Smuzhiyun 	return 0;
1895*4882a593Smuzhiyun 
1896*4882a593Smuzhiyun err_work_queues:
1897*4882a593Smuzhiyun 	if (!lt6911uxe->i2c_client->irq)
1898*4882a593Smuzhiyun 		flush_work(&lt6911uxe->work_i2c_poll);
1899*4882a593Smuzhiyun 	cancel_delayed_work(&lt6911uxe->delayed_work_hotplug);
1900*4882a593Smuzhiyun 	cancel_delayed_work(&lt6911uxe->delayed_work_res_change);
1901*4882a593Smuzhiyun err_clean_entity:
1902*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1903*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1904*4882a593Smuzhiyun #endif
1905*4882a593Smuzhiyun err_free_hdl:
1906*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&lt6911uxe->hdl);
1907*4882a593Smuzhiyun 	mutex_destroy(&lt6911uxe->confctl_mutex);
1908*4882a593Smuzhiyun 	return err;
1909*4882a593Smuzhiyun }
1910*4882a593Smuzhiyun 
lt6911uxe_remove(struct i2c_client * client)1911*4882a593Smuzhiyun static int lt6911uxe_remove(struct i2c_client *client)
1912*4882a593Smuzhiyun {
1913*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1914*4882a593Smuzhiyun 	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
1915*4882a593Smuzhiyun 
1916*4882a593Smuzhiyun 	if (!lt6911uxe->i2c_client->irq) {
1917*4882a593Smuzhiyun 		del_timer_sync(&lt6911uxe->timer);
1918*4882a593Smuzhiyun 		flush_work(&lt6911uxe->work_i2c_poll);
1919*4882a593Smuzhiyun 	}
1920*4882a593Smuzhiyun 	cancel_delayed_work_sync(&lt6911uxe->delayed_work_hotplug);
1921*4882a593Smuzhiyun 	cancel_delayed_work_sync(&lt6911uxe->delayed_work_res_change);
1922*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1923*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
1924*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1925*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1926*4882a593Smuzhiyun #endif
1927*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&lt6911uxe->hdl);
1928*4882a593Smuzhiyun 	mutex_destroy(&lt6911uxe->confctl_mutex);
1929*4882a593Smuzhiyun 	clk_disable_unprepare(lt6911uxe->xvclk);
1930*4882a593Smuzhiyun 
1931*4882a593Smuzhiyun 	return 0;
1932*4882a593Smuzhiyun }
1933*4882a593Smuzhiyun 
1934*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1935*4882a593Smuzhiyun static const struct of_device_id lt6911uxe_of_match[] = {
1936*4882a593Smuzhiyun 	{ .compatible = "lontium,lt6911uxe" },
1937*4882a593Smuzhiyun 	{},
1938*4882a593Smuzhiyun };
1939*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lt6911uxe_of_match);
1940*4882a593Smuzhiyun #endif
1941*4882a593Smuzhiyun 
1942*4882a593Smuzhiyun static struct i2c_driver lt6911uxe_driver = {
1943*4882a593Smuzhiyun 	.driver = {
1944*4882a593Smuzhiyun 		.name = LT6911UXE_NAME,
1945*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(lt6911uxe_of_match),
1946*4882a593Smuzhiyun 	},
1947*4882a593Smuzhiyun 	.probe = lt6911uxe_probe,
1948*4882a593Smuzhiyun 	.remove = lt6911uxe_remove,
1949*4882a593Smuzhiyun };
1950*4882a593Smuzhiyun 
lt6911uxe_driver_init(void)1951*4882a593Smuzhiyun static int __init lt6911uxe_driver_init(void)
1952*4882a593Smuzhiyun {
1953*4882a593Smuzhiyun 	return i2c_add_driver(&lt6911uxe_driver);
1954*4882a593Smuzhiyun }
1955*4882a593Smuzhiyun 
lt6911uxe_driver_exit(void)1956*4882a593Smuzhiyun static void __exit lt6911uxe_driver_exit(void)
1957*4882a593Smuzhiyun {
1958*4882a593Smuzhiyun 	i2c_del_driver(&lt6911uxe_driver);
1959*4882a593Smuzhiyun }
1960*4882a593Smuzhiyun 
1961*4882a593Smuzhiyun device_initcall_sync(lt6911uxe_driver_init);
1962*4882a593Smuzhiyun module_exit(lt6911uxe_driver_exit);
1963*4882a593Smuzhiyun 
1964*4882a593Smuzhiyun MODULE_DESCRIPTION("Lontium lt6911uxe HDMI to CSI-2 bridge driver");
1965*4882a593Smuzhiyun MODULE_AUTHOR("Jianwei Fan <jianwei.fan@rock-chips.com>");
1966*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1967