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/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Ddw_apb_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Support for the Synopsys DesignWare APB Timers.
51 return readl(timer->base + offs); in apbt_readl()
57 writel(val, timer->base + offs); in apbt_writel()
62 return readl_relaxed(timer->base + offs); in apbt_readl_relaxed()
68 writel_relaxed(val, timer->base + offs); in apbt_writel_relaxed()
80 * dw_apb_clockevent_pause() - stop the clock_event_device from running
82 * @dw_ced: The APB clock to stop generating events.
86 disable_irq(dw_ced->timer.irq); in dw_apb_clockevent_pause()
87 apbt_disable_int(&dw_ced->timer); in dw_apb_clockevent_pause()
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H A Ddw_apb_timer_of.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Modified from mach-picoxcell/time.c
18 void __iomem **base, u32 *rate) in timer_get_base_and_rate() argument
24 *base = of_iomap(np, 0); in timer_get_base_and_rate()
26 if (!*base) in timer_get_base_and_rate()
59 if (of_property_read_u32(np, "clock-freq", rate) && in timer_get_base_and_rate()
60 of_property_read_u32(np, "clock-frequency", rate)) in timer_get_base_and_rate()
61 panic("No clock nor clock-frequency property for %pOFn", np); in timer_get_base_and_rate()
76 ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq, in add_clockevent()
95 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate); in add_clocksource()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
31 - enum:
32 - mediatek,mt2701-smi-common
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/OK3568_Linux_fs/kernel/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dlpc1850-cgu.txt5 a base clock and itself is one of the inputs to the two Clock
13 corresponds to one of the base clocks for the LPC18xx.
15 - Above text taken from NXP LPC1850 User Manual.
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - compatible:
23 Should be "nxp,lpc1850-cgu"
24 - reg:
25 Shall define the base and range of the address space
27 - #clock-cells:
28 Shall have value <1>. The permitted clock-specifier values
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/OK3568_Linux_fs/kernel/drivers/clk/mmp/
H A Dclk-apbc.c2 * mmp APB clock operation source file
20 /* Common APB clock register bit definitions */
21 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
29 void __iomem *base; member
45 if (apbc->lock) in clk_apbc_prepare()
46 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
48 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
49 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
52 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
54 if (apbc->lock) in clk_apbc_prepare()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
16 - interrupts: interrupt reference to primary interrupt controller
20 - 0 maps to bit 0 of low interrupts,
21 - 1 maps to bit 1 of low interrupts,
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/OK3568_Linux_fs/kernel/arch/x86/kernel/
H A Dapb_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * apb_timer.c: Driver for Langwell APB timers
17 * - timer 0 - NR_CPUs for per cpu timer
18 * - one timer for clocksource
19 * - one timer for watchdog driver.
20 * It is also worth notice that APB timer does not support true one-shot mode,
21 * free-running mode will be used here to emulate one-shot mode.
22 * APB timer can also be used as broadcast timer along with per cpu local APIC
23 * timer, but by default APB timer has higher rating than local APIC timers.
39 #include <asm/intel-mid.h>
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/OK3568_Linux_fs/kernel/arch/arc/boot/dts/
H A Daxc001.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
28 clock-frequency = <750000000>;
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-inno-usb3.txt4 - compatible: should be one of the listed compatibles:
5 * "rockchip,rk3328-u3phy"
6 * "rockchip,rk322xh-u3phy"
7 - reg : the base address of USB 3.0 PHY.
8 - rockchip,u3phygrf : phandle to the syscon managing the
10 - interrupts : specify an interrupt for each entry in interrupt-names.
11 - interrupt-names : a list which shall be the following entries:
13 - clocks : phandle + clock specifier for the phy clocks.
14 - clock-names :
15 * "u3phy-otg" for USB 3.0 PHY utmi
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/imx/
H A Dnxp,imx8mq-dcss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
23 const: nxp,imx8mq-dcss
27 - description: DCSS base address and size, up to IRQ steer start
28 - description: DCSS BLKCTL base address and size
32 - description: Context loader completion and error interrupt
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/OK3568_Linux_fs/kernel/arch/arc/plat-axs10x/
H A Daxs10x.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
12 #include <asm/asm-offsets.h>
32 * intermediate DW APB GPIO blocks (mainly for debouncing) in axs10x_enable_gpio_intc_wire()
34 * --------------------- in axs10x_enable_gpio_intc_wire()
35 * | snps,arc700-intc | in axs10x_enable_gpio_intc_wire()
36 * --------------------- in axs10x_enable_gpio_intc_wire()
38 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
39 * | snps,dw-apb-gpio | | snps,dw-apb-gpio | in axs10x_enable_gpio_intc_wire()
40 * ------------------- ------------------- in axs10x_enable_gpio_intc_wire()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Drockchip-pcie-ep.txt4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
13 - "aclk-perf"
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H A Drcar-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
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H A Drockchip-pcie.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
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/OK3568_Linux_fs/u-boot/drivers/gpio/
H A Ddwapb_gpio.c4 * DesignWare APB GPIO driver
6 * SPDX-License-Identifier: GPL-2.0+
15 #include <dm/device-internal.h>
37 fdt_addr_t base; member
44 clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); in dwapb_gpio_direction_input()
53 setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
56 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
58 clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_direction_output()
66 return !!(readl(plat->base + GPIO_EXT_PORT(plat->bank)) & (1 << pin)); in dwapb_gpio_get_value()
75 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); in dwapb_gpio_set_value()
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/OK3568_Linux_fs/u-boot/drivers/phy/
H A Dphy-rockchip-inno-usb3.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on phy-rockchip-inno-usb3.c in Linux Kernel.
12 #include <generic-phy.h>
89 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
90 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
91 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
92 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
110 void __iomem *base; member
128 static inline int param_write(void __iomem *base, in param_write() argument
132 unsigned int tmp = desired ? reg->dvalue : reg->rvalue; in param_write()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dzx2967-thermal.txt4 - compatible: should be one of the following.
5 * zte,zx296718-thermal
6 - reg: physical base address of the controller and length of memory mapped
8 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
9 - clock-names: "topcrm" for the topcrm clock.
10 "apb" for the apb clock.
11 - #thermal-sensor-cells: must be 0.
13 Please note: slope coefficient defined in thermal-zones section need to be
19 compatible = "zte,zx296718-thermal";
22 clock-names = "topcrm", "apb";
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/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-suniv-f1c100s.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
24 #include "ccu-suniv-f1c100s.h"
38 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
46 * the base (2x, 4x and 8x), and one variable divider (the one true
54 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
62 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
74 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
86 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
102 .hw.init = CLK_HW_INIT("pll-periph", "osc24M",
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/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-gemini.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "clk-gemini: " fmt
15 #include <linux/clk-provider.h>
21 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/cortina,gemini-reset.h>
23 #include <dt-bindings/clock/cortina,gemini-clock.h>
53 * struct gemini_data_data - Gemini gated clocks
67 * struct clk_gemini_pci - Gemini PCI clock
79 * struct gemini_reset - gemini reset controller
92 { 1, "security-gate", "secdiv", 0 },
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/can/
H A Drockchip_canfd.txt2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "rockchip,canfd-1.0" for CANFD controllers 1.0
7 - "rockchip,can-2.0" for RK3588 CAN controllers 2.0
8 - "rockchip,rk3568-can-2.0" for RK3568 CAN controllers 2.0
9 - reg : Physical base address and size of the controller
11 - interrupts : Property with a value describing the interrupt
13 - clock-names : List of input clock names
14 - "can_clk", "pclk",
16 - clocks : Clock phandles (see clock bindings for details).
[all …]
H A Drockchip_can.txt2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "rockchip,can-1.0" for CAN controllers 1.0
7 - reg : Physical base address and size of the controller
9 - interrupts : Property with a value describing the interrupt
11 - clock-names : List of input clock names
12 - "can_clk", "pclk",
14 - clocks : Clock phandles (see clock bindings for details).
15 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : List of input reset names
[all …]
/OK3568_Linux_fs/kernel/drivers/nvmem/
H A Drockchip-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
108 * +----------+------------------+--------------------------+
110 * +----------+------------------+--------------------------+
112 * +----------+------------------+--------------------------+
114 * +----------+------------------+--------------------------+
116 * +----------+------------------+--------------------------+
118 * +----------+------------------+--------------------------+
120 * +-----+ +------------------+
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-armada100/
H A Darmada100.h4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 /* Common APB clock register bit definitions */
16 #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
38 /* Register Base Addresses */
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dimx8m-ddrc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
18 switching is implemented by TF-A code which runs from a SRAM area.
27 - enum:
28 - fsl,imx8mn-ddrc
29 - fsl,imx8mm-ddrc
30 - fsl,imx8mq-ddrc
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