1* Rockchip AXI PCIe Root Port Bridge DT description 2 3Required properties: 4- #address-cells: Address representation for root ports, set to <3> 5- #size-cells: Size representation for root ports, set to <2> 6- #interrupt-cells: specifies the number of cells needed to encode an 7 interrupt source. The value must be 1. 8- compatible: Should contain "rockchip,rk3399-pcie" 9- reg: Two register ranges as listed in the reg-names property 10- reg-names: Must include the following names 11 - "axi-base" 12 - "apb-base" 13- clocks: Must contain an entry for each entry in clock-names. 14 See ../clocks/clock-bindings.txt for details. 15- clock-names: Must include the following entries: 16 - "aclk" 17 - "aclk-perf" 18 - "hclk" 19 - "pm" 20- msi-map: Maps a Requester ID to an MSI controller and associated 21 msi-specifier data. See ./pci-msi.txt 22- phys: From PHY bindings: Phandle for the Generic PHY for PCIe. 23- phy-names: MUST be "pcie-phy". 24- interrupts: Three interrupt entries must be specified. 25- interrupt-names: Must include the following names 26 - "sys" 27 - "legacy" 28 - "client" 29- resets: Must contain seven entries for each entry in reset-names. 30 See ../reset/reset.txt for details. 31- reset-names: Must include the following names 32 - "core" 33 - "mgmt" 34 - "mgmt-sticky" 35 - "pipe" 36 - "pm" 37 - "aclk" 38 - "pclk" 39- pinctrl-names : The pin control state names 40- pinctrl-0: The "default" pinctrl state 41- #interrupt-cells: specifies the number of cells needed to encode an 42 interrupt source. The value must be 1. 43- interrupt-map-mask and interrupt-map: standard PCI properties 44 45Optional Property: 46- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if 47 using 24MHz OSC for RC's PHY. 48- ep-gpios: contain the entry for pre-reset gpio 49- num-lanes: number of lanes to use 50- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe. 51- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe. 52- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe. 53 54*Interrupt controller child node* 55The core controller provides a single interrupt for legacy INTx. The PCIe node 56should contain an interrupt controller node as a target for the PCI 57'interrupt-map' property. This node represents the domain at which the four 58INTx interrupts are decoded and routed. 59 60 61Required properties for Interrupt controller child node: 62- interrupt-controller: identifies the node as an interrupt controller 63- #address-cells: specifies the number of cells needed to encode an 64 address. The value must be 0. 65- #interrupt-cells: specifies the number of cells needed to encode an 66 interrupt source. The value must be 1. 67 68Example: 69 70pcie0: pcie@f8000000 { 71 compatible = "rockchip,rk3399-pcie"; 72 #address-cells = <3>; 73 #size-cells = <2>; 74 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 75 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 76 clock-names = "aclk", "aclk-perf", 77 "hclk", "pm"; 78 bus-range = <0x0 0x1>; 79 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 80 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 81 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 82 interrupt-names = "sys", "legacy", "client"; 83 assigned-clocks = <&cru SCLK_PCIEPHY_REF>; 84 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; 85 assigned-clock-rates = <100000000>; 86 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 87 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 88 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 89 num-lanes = <4>; 90 msi-map = <0x0 &its 0x0 0x1000>; 91 reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>; 92 reg-names = "axi-base", "apb-base"; 93 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 94 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , 95 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; 96 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 97 "pm", "pclk", "aclk"; 98 phys = <&pcie_phy>; 99 phy-names = "pcie-phy"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pcie_clkreq>; 102 #interrupt-cells = <1>; 103 interrupt-map-mask = <0 0 0 7>; 104 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 105 <0 0 0 2 &pcie0_intc 1>, 106 <0 0 0 3 &pcie0_intc 2>, 107 <0 0 0 4 &pcie0_intc 3>; 108 pcie0_intc: interrupt-controller { 109 interrupt-controller; 110 #address-cells = <0>; 111 #interrupt-cells = <1>; 112 }; 113}; 114