1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip OTP Driver
4 *
5 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-provider.h>
16 #include <linux/reset.h>
17 #include <linux/rockchip/cpu.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22
23 /* OTP Register Offsets */
24 #define OTPC_SBPI_CTRL 0x0020
25 #define OTPC_SBPI_CMD_VALID_PRE 0x0024
26 #define OTPC_SBPI_CS_VALID_PRE 0x0028
27 #define OTPC_SBPI_STATUS 0x002C
28 #define OTPC_USER_CTRL 0x0100
29 #define OTPC_USER_ADDR 0x0104
30 #define OTPC_USER_ENABLE 0x0108
31 #define OTPC_USER_QP 0x0120
32 #define OTPC_USER_Q 0x0124
33 #define OTPC_INT_STATUS 0x0304
34 #define OTPC_SBPI_CMD0_OFFSET 0x1000
35 #define OTPC_SBPI_CMD1_OFFSET 0x1004
36
37 #define OTPC_MODE_CTRL 0x2000
38 #define OTPC_IRQ_ST 0x2008
39 #define OTPC_ACCESS_ADDR 0x200c
40 #define OTPC_RD_DATA 0x2010
41 #define OTPC_REPR_RD_TRANS_NUM 0x2020
42
43 #define OTPC_DEEP_STANDBY 0x0
44 #define OTPC_STANDBY 0x1
45 #define OTPC_ACTIVE 0x2
46 #define OTPC_READ_ACCESS 0x3
47 #define OTPC_TRANS_NUM 0x1
48 #define OTPC_RDM_IRQ_ST BIT(0)
49 #define OTPC_STB2ACT_IRQ_ST BIT(7)
50 #define OTPC_DP2STB_IRQ_ST BIT(8)
51 #define OTPC_ACT2STB_IRQ_ST BIT(9)
52 #define OTPC_STB2DP_IRQ_ST BIT(10)
53 #define PX30S_NBYTES 4
54 #define PX30S_NO_SECURE_OFFSET 224
55
56 /* OTP Register bits and masks */
57 #define OTPC_USER_ADDR_MASK GENMASK(31, 16)
58 #define OTPC_USE_USER BIT(0)
59 #define OTPC_USE_USER_MASK GENMASK(16, 16)
60 #define OTPC_USER_FSM_ENABLE BIT(0)
61 #define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16)
62 #define OTPC_SBPI_DONE BIT(1)
63 #define OTPC_USER_DONE BIT(2)
64
65 #define SBPI_DAP_ADDR 0x02
66 #define SBPI_DAP_ADDR_SHIFT 8
67 #define SBPI_DAP_ADDR_MASK GENMASK(31, 24)
68 #define SBPI_CMD_VALID_MASK GENMASK(31, 16)
69 #define SBPI_DAP_CMD_WRF 0xC0
70 #define SBPI_DAP_REG_ECC 0x3A
71 #define SBPI_ECC_ENABLE 0x00
72 #define SBPI_ECC_DISABLE 0x09
73 #define SBPI_ENABLE BIT(0)
74 #define SBPI_ENABLE_MASK GENMASK(16, 16)
75
76 #define OTPC_TIMEOUT 10000
77 #define OTPC_TIMEOUT_PROG 100000
78 #define RK3568_NBYTES 2
79
80 #define RK3588_OTPC_AUTO_CTRL 0x04
81 #define RK3588_OTPC_AUTO_EN 0x08
82 #define RK3588_OTPC_INT_ST 0x84
83 #define RK3588_OTPC_DOUT0 0x20
84 #define RK3588_NO_SECURE_OFFSET 0x300
85 #define RK3588_NBYTES 4
86 #define RK3588_BURST_NUM 1
87 #define RK3588_BURST_SHIFT 8
88 #define RK3588_ADDR_SHIFT 16
89 #define RK3588_AUTO_EN BIT(0)
90 #define RK3588_RD_DONE BIT(1)
91
92 #define RV1126_OTP_NVM_CEB 0x00
93 #define RV1126_OTP_NVM_RSTB 0x04
94 #define RV1126_OTP_NVM_ST 0x18
95 #define RV1126_OTP_NVM_RADDR 0x1C
96 #define RV1126_OTP_NVM_RSTART 0x20
97 #define RV1126_OTP_NVM_RDATA 0x24
98 #define RV1126_OTP_NVM_TRWH 0x28
99 #define RV1126_OTP_READ_ST 0x30
100 #define RV1126_OTP_NVM_PRADDR 0x34
101 #define RV1126_OTP_NVM_PRLEN 0x38
102 #define RV1126_OTP_NVM_PRDATA 0x3c
103 #define RV1126_OTP_NVM_FAILTIME 0x40
104 #define RV1126_OTP_NVM_PRSTART 0x44
105 #define RV1126_OTP_NVM_PRSTATE 0x48
106
107 /*
108 * +----------+------------------+--------------------------+
109 * | TYPE | RANGE(byte) | NOTE |
110 * +----------+------------------+--------------------------+
111 * | system | 0x000 ~ 0x0ff | system info, read only |
112 * +----------+------------------+--------------------------+
113 * | oem | 0x100 ~ 0x1ef | for customized |
114 * +----------+------------------+--------------------------+
115 * | reserved | 0x1f0 ~ 0x1f7 | future extension |
116 * +----------+------------------+--------------------------+
117 * | wp | 0x1f8 ~ 0x1ff | write protection for oem |
118 * +----------+------------------+--------------------------+
119 *
120 * +-----+ +------------------+
121 * | wp | -- | wp for oem range |
122 * +-----+ +------------------+
123 * | 1f8 | | 0x100 ~ 0x11f |
124 * +-----+ +------------------+
125 * | 1f9 | | 0x120 ~ 0x13f |
126 * +-----+ +------------------+
127 * | 1fa | | 0x140 ~ 0x15f |
128 * +-----+ +------------------+
129 * | 1fb | | 0x160 ~ 0x17f |
130 * +-----+ +------------------+
131 * | 1fc | | 0x180 ~ 0x19f |
132 * +-----+ +------------------+
133 * | 1fd | | 0x1a0 ~ 0x1bf |
134 * +-----+ +------------------+
135 * | 1fe | | 0x1c0 ~ 0x1df |
136 * +-----+ +------------------+
137 * | 1ff | | 0x1e0 ~ 0x1ef |
138 * +-----+ +------------------+
139 */
140 #define RV1126_OTP_OEM_OFFSET 0x100
141 #define RV1126_OTP_OEM_SIZE 0xf0
142 #define RV1126_OTP_WP_OFFSET 0x1f8
143 #define RV1126_OTP_WP_SIZE 0x8
144
145 /* magic for enable otp write func */
146 #define ROCKCHIP_OTP_WR_MAGIC 0x524F434B
147 /* each bit mask 32 bits in OTP NVM */
148 #define ROCKCHIP_OTP_WP_MASK_NBITS 64
149
150 static unsigned int rockchip_otp_wr_magic;
151 module_param(rockchip_otp_wr_magic, uint, 0644);
152 MODULE_PARM_DESC(rockchip_otp_wr_magic, "magic for enable otp write func.");
153
154 struct rockchip_data;
155
156 struct rockchip_otp {
157 struct device *dev;
158 void __iomem *base;
159 struct clk_bulk_data *clks;
160 int num_clks;
161 struct reset_control *rst;
162 struct nvmem_config *config;
163 const struct rockchip_data *data;
164 struct mutex mutex;
165 DECLARE_BITMAP(wp_mask, ROCKCHIP_OTP_WP_MASK_NBITS);
166 };
167
168 struct rockchip_data {
169 int size;
170 const char * const *clocks;
171 int num_clks;
172 nvmem_reg_read_t reg_read;
173 nvmem_reg_write_t reg_write;
174 int (*init)(struct rockchip_otp *otp);
175 };
176
rockchip_otp_reset(struct rockchip_otp * otp)177 static int rockchip_otp_reset(struct rockchip_otp *otp)
178 {
179 int ret;
180
181 ret = reset_control_assert(otp->rst);
182 if (ret) {
183 dev_err(otp->dev, "failed to assert otp phy %d\n", ret);
184 return ret;
185 }
186
187 udelay(2);
188
189 ret = reset_control_deassert(otp->rst);
190 if (ret) {
191 dev_err(otp->dev, "failed to deassert otp phy %d\n", ret);
192 return ret;
193 }
194
195 return 0;
196 }
197
px30_otp_wait_status(struct rockchip_otp * otp,u32 flag)198 static int px30_otp_wait_status(struct rockchip_otp *otp, u32 flag)
199 {
200 u32 status = 0;
201 int ret;
202
203 ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status,
204 (status & flag), 1, OTPC_TIMEOUT);
205 if (ret)
206 return ret;
207
208 /* clean int status */
209 writel(flag, otp->base + OTPC_INT_STATUS);
210
211 return 0;
212 }
213
px30_otp_ecc_enable(struct rockchip_otp * otp,bool enable)214 static int px30_otp_ecc_enable(struct rockchip_otp *otp, bool enable)
215 {
216 int ret = 0;
217
218 writel(SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT),
219 otp->base + OTPC_SBPI_CTRL);
220
221 writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE);
222 writel(SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC,
223 otp->base + OTPC_SBPI_CMD0_OFFSET);
224 if (enable)
225 writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
226 else
227 writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
228
229 writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
230
231 ret = px30_otp_wait_status(otp, OTPC_SBPI_DONE);
232 if (ret < 0)
233 dev_err(otp->dev, "timeout during ecc_enable\n");
234
235 return ret;
236 }
237
px30_otp_read(void * context,unsigned int offset,void * val,size_t bytes)238 static int px30_otp_read(void *context, unsigned int offset, void *val,
239 size_t bytes)
240 {
241 struct rockchip_otp *otp = context;
242 u8 *buf = val;
243 int ret = 0;
244
245 ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
246 if (ret < 0) {
247 dev_err(otp->dev, "failed to prepare/enable clks\n");
248 return ret;
249 }
250
251 ret = rockchip_otp_reset(otp);
252 if (ret) {
253 dev_err(otp->dev, "failed to reset otp phy\n");
254 goto disable_clks;
255 }
256
257 ret = px30_otp_ecc_enable(otp, false);
258 if (ret < 0) {
259 dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
260 goto disable_clks;
261 }
262
263 writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
264 udelay(5);
265 while (bytes--) {
266 writel(offset++ | OTPC_USER_ADDR_MASK,
267 otp->base + OTPC_USER_ADDR);
268 writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
269 otp->base + OTPC_USER_ENABLE);
270 ret = px30_otp_wait_status(otp, OTPC_USER_DONE);
271 if (ret < 0) {
272 dev_err(otp->dev, "timeout during read setup\n");
273 goto read_end;
274 }
275 *buf++ = readb(otp->base + OTPC_USER_Q);
276 }
277
278 read_end:
279 writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
280 disable_clks:
281 clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
282
283 return ret;
284 }
285
px30s_otp_wait_status(struct rockchip_otp * otp,u32 flag)286 static int px30s_otp_wait_status(struct rockchip_otp *otp, u32 flag)
287 {
288 u32 status = 0;
289 int ret;
290
291 ret = readl_poll_timeout_atomic(otp->base + OTPC_IRQ_ST, status,
292 (status & flag), 1, OTPC_TIMEOUT);
293 if (ret)
294 return ret;
295
296 /* clean int status */
297 writel(flag, otp->base + OTPC_IRQ_ST);
298
299 return 0;
300 }
301
px30s_otp_active(struct rockchip_otp * otp)302 static int px30s_otp_active(struct rockchip_otp *otp)
303 {
304 int ret = 0;
305 u32 mode;
306
307 mode = readl(otp->base + OTPC_MODE_CTRL);
308
309 switch (mode) {
310 case OTPC_DEEP_STANDBY:
311 writel(OTPC_STANDBY, otp->base + OTPC_MODE_CTRL);
312 ret = px30s_otp_wait_status(otp, OTPC_DP2STB_IRQ_ST);
313 if (ret < 0) {
314 dev_err(otp->dev, "timeout during wait dp2stb\n");
315 return ret;
316 }
317 fallthrough;
318 case OTPC_STANDBY:
319 writel(OTPC_ACTIVE, otp->base + OTPC_MODE_CTRL);
320 ret = px30s_otp_wait_status(otp, OTPC_STB2ACT_IRQ_ST);
321 if (ret < 0) {
322 dev_err(otp->dev, "timeout during wait stb2act\n");
323 return ret;
324 }
325 break;
326 default:
327 break;
328 }
329
330 return ret;
331 }
332
px30s_otp_standby(struct rockchip_otp * otp)333 static int px30s_otp_standby(struct rockchip_otp *otp)
334 {
335 int ret = 0;
336 u32 mode;
337
338 mode = readl(otp->base + OTPC_MODE_CTRL);
339
340 switch (mode) {
341 case OTPC_ACTIVE:
342 writel(OTPC_STANDBY, otp->base + OTPC_MODE_CTRL);
343 ret = px30s_otp_wait_status(otp, OTPC_ACT2STB_IRQ_ST);
344 if (ret < 0) {
345 dev_err(otp->dev, "timeout during wait act2stb\n");
346 return ret;
347 }
348 fallthrough;
349 case OTPC_STANDBY:
350 writel(OTPC_DEEP_STANDBY, otp->base + OTPC_MODE_CTRL);
351 ret = px30s_otp_wait_status(otp, OTPC_STB2DP_IRQ_ST);
352 if (ret < 0) {
353 dev_err(otp->dev, "timeout during wait stb2dp\n");
354 return ret;
355 }
356 break;
357 default:
358 break;
359 }
360
361 return ret;
362 }
363
px30s_otp_read(void * context,unsigned int offset,void * val,size_t bytes)364 static int px30s_otp_read(void *context, unsigned int offset, void *val,
365 size_t bytes)
366 {
367 struct rockchip_otp *otp = context;
368 unsigned int addr_start, addr_end, addr_offset, addr_len;
369 int ret, i = 0;
370 u32 out_value;
371 u8 *buf;
372
373 if (offset >= otp->data->size)
374 return -ENOMEM;
375 if (offset + bytes > otp->data->size)
376 bytes = otp->data->size - offset;
377
378 ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
379 if (ret < 0) {
380 dev_err(otp->dev, "failed to prepare/enable clks\n");
381 return ret;
382 }
383
384 ret = rockchip_otp_reset(otp);
385 if (ret) {
386 dev_err(otp->dev, "failed to reset otp phy\n");
387 goto disable_clks;
388 }
389
390 ret = px30s_otp_active(otp);
391 if (ret)
392 goto disable_clks;
393
394 addr_start = rounddown(offset, PX30S_NBYTES) / PX30S_NBYTES;
395 addr_end = roundup(offset + bytes, PX30S_NBYTES) / PX30S_NBYTES;
396 addr_offset = offset % PX30S_NBYTES;
397 addr_len = addr_end - addr_start;
398 addr_start += PX30S_NO_SECURE_OFFSET;
399
400 buf = kzalloc(sizeof(*buf) * addr_len * PX30S_NBYTES, GFP_KERNEL);
401 if (!buf) {
402 ret = -ENOMEM;
403 goto read_end;
404 }
405
406 while (addr_len--) {
407 writel(OTPC_TRANS_NUM, otp->base + OTPC_REPR_RD_TRANS_NUM);
408 writel(addr_start++, otp->base + OTPC_ACCESS_ADDR);
409 writel(OTPC_READ_ACCESS, otp->base + OTPC_MODE_CTRL);
410 ret = px30s_otp_wait_status(otp, OTPC_RDM_IRQ_ST);
411 if (ret < 0) {
412 dev_err(otp->dev, "timeout during wait rd\n");
413 goto read_end;
414 }
415 out_value = readl(otp->base + OTPC_RD_DATA);
416 memcpy(&buf[i], &out_value, PX30S_NBYTES);
417 i += PX30S_NBYTES;
418 }
419 memcpy(val, buf + addr_offset, (unsigned int)bytes);
420
421 read_end:
422 kfree(buf);
423 px30s_otp_standby(otp);
424 disable_clks:
425 clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
426
427 return ret;
428 }
429
rk3568_otp_read(void * context,unsigned int offset,void * val,size_t bytes)430 static int rk3568_otp_read(void *context, unsigned int offset, void *val,
431 size_t bytes)
432 {
433 struct rockchip_otp *otp = context;
434 unsigned int addr_start, addr_end, addr_offset, addr_len;
435 unsigned int otp_qp;
436 u32 out_value;
437 u8 *buf;
438 int ret = 0, i = 0;
439
440 addr_start = rounddown(offset, RK3568_NBYTES) / RK3568_NBYTES;
441 addr_end = roundup(offset + bytes, RK3568_NBYTES) / RK3568_NBYTES;
442 addr_offset = offset % RK3568_NBYTES;
443 addr_len = addr_end - addr_start;
444
445 buf = kzalloc(array3_size(addr_len, RK3568_NBYTES, sizeof(*buf)),
446 GFP_KERNEL);
447 if (!buf)
448 return -ENOMEM;
449
450 ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
451 if (ret < 0) {
452 dev_err(otp->dev, "failed to prepare/enable clks\n");
453 goto out;
454 }
455
456 ret = rockchip_otp_reset(otp);
457 if (ret) {
458 dev_err(otp->dev, "failed to reset otp phy\n");
459 goto disable_clks;
460 }
461
462 ret = px30_otp_ecc_enable(otp, true);
463 if (ret < 0) {
464 dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
465 goto disable_clks;
466 }
467
468 writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
469 udelay(5);
470 while (addr_len--) {
471 writel(addr_start++ | OTPC_USER_ADDR_MASK,
472 otp->base + OTPC_USER_ADDR);
473 writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
474 otp->base + OTPC_USER_ENABLE);
475 ret = px30_otp_wait_status(otp, OTPC_USER_DONE);
476 if (ret < 0) {
477 dev_err(otp->dev, "timeout during read setup\n");
478 goto read_end;
479 }
480 otp_qp = readl(otp->base + OTPC_USER_QP);
481 if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) {
482 ret = -EIO;
483 dev_err(otp->dev, "ecc check error during read setup\n");
484 goto read_end;
485 }
486 out_value = readl(otp->base + OTPC_USER_Q);
487 memcpy(&buf[i], &out_value, RK3568_NBYTES);
488 i += RK3568_NBYTES;
489 }
490
491 memcpy(val, buf + addr_offset, bytes);
492
493 read_end:
494 writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
495 disable_clks:
496 clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
497 out:
498 kfree(buf);
499
500 return ret;
501 }
502
rk3588_otp_wait_status(struct rockchip_otp * otp,u32 flag)503 static int rk3588_otp_wait_status(struct rockchip_otp *otp, u32 flag)
504 {
505 u32 status = 0;
506 int ret;
507
508 ret = readl_poll_timeout_atomic(otp->base + RK3588_OTPC_INT_ST, status,
509 (status & flag), 1, OTPC_TIMEOUT);
510 if (ret)
511 return ret;
512
513 /* clean int status */
514 writel(flag, otp->base + RK3588_OTPC_INT_ST);
515
516 return 0;
517 }
518
rk3588_otp_read(void * context,unsigned int offset,void * val,size_t bytes)519 static int rk3588_otp_read(void *context, unsigned int offset, void *val,
520 size_t bytes)
521 {
522 struct rockchip_otp *otp = context;
523 unsigned int addr_start, addr_end, addr_offset, addr_len;
524 int ret = 0, i = 0;
525 u32 out_value;
526 u8 *buf;
527
528 if (offset >= otp->data->size)
529 return -ENOMEM;
530 if (offset + bytes > otp->data->size)
531 bytes = otp->data->size - offset;
532
533 addr_start = rounddown(offset, RK3588_NBYTES) / RK3588_NBYTES;
534 addr_end = roundup(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES;
535 addr_offset = offset % RK3588_NBYTES;
536 addr_len = addr_end - addr_start;
537 addr_start += RK3588_NO_SECURE_OFFSET;
538
539 buf = kzalloc(array3_size(addr_len, RK3588_NBYTES, sizeof(*buf)),
540 GFP_KERNEL);
541 if (!buf)
542 return -ENOMEM;
543
544 ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
545 if (ret < 0) {
546 dev_err(otp->dev, "failed to prepare/enable clks\n");
547 goto out;
548 }
549
550 while (addr_len--) {
551 writel((addr_start << RK3588_ADDR_SHIFT) |
552 (RK3588_BURST_NUM << RK3588_BURST_SHIFT),
553 otp->base + RK3588_OTPC_AUTO_CTRL);
554 writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
555 ret = rk3588_otp_wait_status(otp, RK3588_RD_DONE);
556 if (ret < 0) {
557 dev_err(otp->dev, "timeout during read setup\n");
558 goto read_end;
559 }
560
561 out_value = readl(otp->base + RK3588_OTPC_DOUT0);
562 memcpy(&buf[i], &out_value, RK3588_NBYTES);
563 i += RK3588_NBYTES;
564 addr_start++;
565 }
566
567 memcpy(val, buf + addr_offset, bytes);
568
569 read_end:
570 clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
571 out:
572 kfree(buf);
573
574 return ret;
575 }
576
rv1126_otp_init(struct rockchip_otp * otp)577 static int rv1126_otp_init(struct rockchip_otp *otp)
578 {
579 u32 status = 0;
580 int ret;
581
582 writel(0x0, otp->base + RV1126_OTP_NVM_CEB);
583 ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_NVM_ST, status,
584 status & 0x1, 1, OTPC_TIMEOUT);
585 if (ret < 0) {
586 dev_err(otp->dev, "timeout during set ceb\n");
587 return ret;
588 }
589
590 writel(0x1, otp->base + RV1126_OTP_NVM_RSTB);
591 ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_NVM_ST, status,
592 status & 0x4, 1, OTPC_TIMEOUT);
593 if (ret < 0) {
594 dev_err(otp->dev, "timeout during set rstb\n");
595 return ret;
596 }
597
598 otp->config->read_only = false;
599
600 return 0;
601 }
602
rv1126_otp_read(void * context,unsigned int offset,void * val,size_t bytes)603 static int rv1126_otp_read(void *context, unsigned int offset, void *val,
604 size_t bytes)
605 {
606 struct rockchip_otp *otp = context;
607 u32 status = 0;
608 u8 *buf = val;
609 int ret = 0;
610
611 while (bytes--) {
612 writel(offset++, otp->base + RV1126_OTP_NVM_RADDR);
613 writel(0x1, otp->base + RV1126_OTP_NVM_RSTART);
614 ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_READ_ST,
615 status, status == 0, 1,
616 OTPC_TIMEOUT);
617 if (ret < 0) {
618 dev_err(otp->dev, "timeout during read setup\n");
619 return ret;
620 }
621
622 *buf++ = readb(otp->base + RV1126_OTP_NVM_RDATA);
623 }
624
625 return 0;
626 }
627
rv1126_otp_prog(struct rockchip_otp * otp,u32 bit_offset,u32 data,u32 bit_len)628 static int rv1126_otp_prog(struct rockchip_otp *otp, u32 bit_offset, u32 data,
629 u32 bit_len)
630 {
631 u32 status = 0;
632 int ret = 0;
633
634 if (!data)
635 return 0;
636
637 writel(bit_offset, otp->base + RV1126_OTP_NVM_PRADDR);
638 writel(bit_len - 1, otp->base + RV1126_OTP_NVM_PRLEN);
639 writel(data, otp->base + RV1126_OTP_NVM_PRDATA);
640 writel(1, otp->base + RV1126_OTP_NVM_PRSTART);
641 /* Wait max 100 ms */
642 ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_NVM_PRSTATE,
643 status, status == 0, 1,
644 OTPC_TIMEOUT_PROG);
645 if (ret < 0)
646 dev_err(otp->dev, "timeout during prog\n");
647
648 return ret;
649 }
650
rv1126_otp_write(void * context,unsigned int offset,void * val,size_t bytes)651 static int rv1126_otp_write(void *context, unsigned int offset, void *val,
652 size_t bytes)
653 {
654 struct rockchip_otp *otp = context;
655 u8 *buf = val;
656 u8 val_r, val_w;
657 int ret = 0;
658
659 while (bytes--) {
660 ret = rv1126_otp_read(context, offset, &val_r, 1);
661 if (ret)
662 return ret;
663 val_w = *buf & (~val_r);
664 ret = rv1126_otp_prog(otp, offset * 8, val_w, 8);
665 if (ret)
666 return ret;
667 buf++;
668 offset++;
669 }
670
671 return 0;
672 }
673
rv1126_otp_wp(void * context,unsigned int offset,size_t bytes)674 static int rv1126_otp_wp(void *context, unsigned int offset, size_t bytes)
675 {
676 struct rockchip_otp *otp = context;
677
678 bitmap_set(otp->wp_mask, (offset - RV1126_OTP_OEM_OFFSET) / 4, bytes / 4);
679
680 return rv1126_otp_write(context, RV1126_OTP_WP_OFFSET, otp->wp_mask,
681 RV1126_OTP_WP_SIZE);
682 }
683
rv1126_otp_oem_write(void * context,unsigned int offset,void * val,size_t bytes)684 static int rv1126_otp_oem_write(void *context, unsigned int offset, void *val,
685 size_t bytes)
686 {
687 int ret = 0;
688
689 if (offset < RV1126_OTP_OEM_OFFSET ||
690 offset > (RV1126_OTP_OEM_OFFSET + RV1126_OTP_OEM_SIZE - 1) ||
691 bytes > RV1126_OTP_OEM_SIZE ||
692 (offset + bytes) > (RV1126_OTP_OEM_OFFSET + RV1126_OTP_OEM_SIZE))
693 return -EINVAL;
694
695 if (!IS_ALIGNED(offset, 4) || !IS_ALIGNED(bytes, 4))
696 return -EINVAL;
697
698 ret = rv1126_otp_write(context, offset, val, bytes);
699 if (!ret)
700 ret = rv1126_otp_wp(context, offset, bytes);
701
702 return ret;
703 }
704
rockchip_otp_read(void * context,unsigned int offset,void * val,size_t bytes)705 static int rockchip_otp_read(void *context, unsigned int offset, void *val,
706 size_t bytes)
707 {
708 struct rockchip_otp *otp = context;
709 int ret = -EINVAL;
710
711 mutex_lock(&otp->mutex);
712 if (otp->data && otp->data->reg_read)
713 ret = otp->data->reg_read(context, offset, val, bytes);
714 mutex_unlock(&otp->mutex);
715
716 return ret;
717 }
718
rockchip_otp_write(void * context,unsigned int offset,void * val,size_t bytes)719 static int rockchip_otp_write(void *context, unsigned int offset, void *val,
720 size_t bytes)
721 {
722 struct rockchip_otp *otp = context;
723 int ret = -EINVAL;
724
725 mutex_lock(&otp->mutex);
726 if (rockchip_otp_wr_magic == ROCKCHIP_OTP_WR_MAGIC &&
727 otp->data && otp->data->reg_write) {
728 ret = otp->data->reg_write(context, offset, val, bytes);
729 rockchip_otp_wr_magic = 0;
730 }
731 mutex_unlock(&otp->mutex);
732
733 return ret;
734 }
735
736 static struct nvmem_config otp_config = {
737 .name = "rockchip-otp",
738 .owner = THIS_MODULE,
739 .read_only = true,
740 .reg_read = rockchip_otp_read,
741 .reg_write = rockchip_otp_write,
742 .stride = 1,
743 .word_size = 1,
744 };
745
746 static const char * const px30_otp_clocks[] = {
747 "otp", "apb_pclk", "phy",
748 };
749
750 static const struct rockchip_data px30_data = {
751 .size = 0x40,
752 .clocks = px30_otp_clocks,
753 .num_clks = ARRAY_SIZE(px30_otp_clocks),
754 .reg_read = px30_otp_read,
755 };
756
757 static const struct rockchip_data px30s_data = {
758 .size = 0x80,
759 .clocks = px30_otp_clocks,
760 .num_clks = ARRAY_SIZE(px30_otp_clocks),
761 .reg_read = px30s_otp_read,
762 };
763
764 static const char * const rk3528_otp_clocks[] = {
765 "usr", "sbpi", "apb",
766 };
767
768 static const struct rockchip_data rk3528_data = {
769 .size = 0x80,
770 .clocks = rk3528_otp_clocks,
771 .num_clks = ARRAY_SIZE(rk3528_otp_clocks),
772 .reg_read = rk3568_otp_read,
773 };
774
775 static const char * const rk3562_otp_clocks[] = {
776 "usr", "sbpi", "apb", "arb", "phy",
777 };
778
779 static const struct rockchip_data rk3562_data = {
780 .size = 0x80,
781 .clocks = rk3562_otp_clocks,
782 .num_clks = ARRAY_SIZE(rk3562_otp_clocks),
783 .reg_read = rk3568_otp_read,
784 };
785
786 static const char * const rk3568_otp_clocks[] = {
787 "usr", "sbpi", "apb", "phy",
788 };
789
790 static const struct rockchip_data rk3568_data = {
791 .size = 0x80,
792 .clocks = rk3568_otp_clocks,
793 .num_clks = ARRAY_SIZE(rk3568_otp_clocks),
794 .reg_read = rk3568_otp_read,
795 };
796
797 static const char * const rk3588_otp_clocks[] = {
798 "otpc", "apb", "arb", "phy",
799 };
800
801 static const struct rockchip_data rk3588_data = {
802 .size = 0x400,
803 .clocks = rk3588_otp_clocks,
804 .num_clks = ARRAY_SIZE(rk3588_otp_clocks),
805 .reg_read = rk3588_otp_read,
806 };
807
808 static const char * const rv1106_otp_clocks[] = {
809 "usr", "sbpi", "apb", "phy", "arb", "pmc",
810 };
811
812 static const struct rockchip_data rv1106_data = {
813 .size = 0x80,
814 .clocks = rv1106_otp_clocks,
815 .num_clks = ARRAY_SIZE(rv1106_otp_clocks),
816 .reg_read = rk3568_otp_read,
817 };
818
819 static const char * const rv1126_otp_clocks[] = {
820 "otp", "apb_pclk",
821 };
822
823 static const struct rockchip_data rv1126_data = {
824 .size = 0x200,
825 .clocks = rv1126_otp_clocks,
826 .num_clks = ARRAY_SIZE(rv1126_otp_clocks),
827 .init = rv1126_otp_init,
828 .reg_read = rv1126_otp_read,
829 .reg_write = rv1126_otp_oem_write,
830 };
831
832 static const struct of_device_id rockchip_otp_match[] = {
833 #ifdef CONFIG_CPU_PX30
834 {
835 .compatible = "rockchip,px30-otp",
836 .data = (void *)&px30_data,
837 },
838 {
839 .compatible = "rockchip,px30s-otp",
840 .data = (void *)&px30s_data,
841 },
842 #endif
843 #ifdef CONFIG_CPU_RK3308
844 {
845 .compatible = "rockchip,rk3308-otp",
846 .data = (void *)&px30_data,
847 },
848 {
849 .compatible = "rockchip,rk3308bs-otp",
850 .data = (void *)&px30s_data,
851 },
852 #endif
853 #ifdef CONFIG_CPU_RK3528
854 {
855 .compatible = "rockchip,rk3528-otp",
856 .data = (void *)&rk3528_data,
857 },
858 #endif
859 #ifdef CONFIG_CPU_RK3562
860 {
861 .compatible = "rockchip,rk3562-otp",
862 .data = (void *)&rk3562_data,
863 },
864 #endif
865 #ifdef CONFIG_CPU_RK3568
866 {
867 .compatible = "rockchip,rk3568-otp",
868 .data = (void *)&rk3568_data,
869 },
870 #endif
871 #ifdef CONFIG_CPU_RK3588
872 {
873 .compatible = "rockchip,rk3588-otp",
874 .data = (void *)&rk3588_data,
875 },
876 #endif
877 #ifdef CONFIG_CPU_RV1106
878 {
879 .compatible = "rockchip,rv1106-otp",
880 .data = (void *)&rv1106_data,
881 },
882 #endif
883 #ifdef CONFIG_CPU_RV1126
884 {
885 .compatible = "rockchip,rv1126-otp",
886 .data = (void *)&rv1126_data,
887 },
888 #endif
889 { /* sentinel */ },
890 };
891 MODULE_DEVICE_TABLE(of, rockchip_otp_match);
892
rockchip_otp_probe(struct platform_device * pdev)893 static int rockchip_otp_probe(struct platform_device *pdev)
894 {
895 struct device *dev = &pdev->dev;
896 struct rockchip_otp *otp;
897 const struct rockchip_data *data;
898 struct nvmem_device *nvmem;
899 int ret, i;
900
901 data = of_device_get_match_data(dev);
902 if (!data) {
903 dev_err(dev, "failed to get match data\n");
904 return -EINVAL;
905 }
906 if (soc_is_px30s() || soc_is_rk3308bs())
907 data = &px30s_data;
908
909 otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp),
910 GFP_KERNEL);
911 if (!otp)
912 return -ENOMEM;
913
914 mutex_init(&otp->mutex);
915 otp->data = data;
916 otp->dev = dev;
917 otp->base = devm_platform_ioremap_resource(pdev, 0);
918 if (IS_ERR(otp->base))
919 return PTR_ERR(otp->base);
920
921 otp->num_clks = data->num_clks;
922 otp->clks = devm_kcalloc(dev, otp->num_clks,
923 sizeof(*otp->clks), GFP_KERNEL);
924 if (!otp->clks)
925 return -ENOMEM;
926
927 for (i = 0; i < otp->num_clks; ++i)
928 otp->clks[i].id = data->clocks[i];
929
930 ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks);
931 if (ret)
932 return ret;
933
934 otp->rst = devm_reset_control_array_get_optional_exclusive(dev);
935 if (IS_ERR(otp->rst))
936 return PTR_ERR(otp->rst);
937
938 otp->config = &otp_config;
939 otp->config->size = data->size;
940 otp->config->priv = otp;
941 otp->config->dev = dev;
942
943 if (data->init) {
944 ret = data->init(otp);
945 if (ret)
946 return ret;
947 }
948
949 nvmem = devm_nvmem_register(dev, otp->config);
950
951 return PTR_ERR_OR_ZERO(nvmem);
952 }
953
954 static struct platform_driver rockchip_otp_driver = {
955 .probe = rockchip_otp_probe,
956 .driver = {
957 .name = "rockchip-otp",
958 .of_match_table = rockchip_otp_match,
959 },
960 };
961
rockchip_otp_init(void)962 static int __init rockchip_otp_init(void)
963 {
964 int ret;
965
966 ret = platform_driver_register(&rockchip_otp_driver);
967 if (ret) {
968 pr_err("failed to register otp driver\n");
969 return ret;
970 }
971
972 return 0;
973 }
974
rockchip_otp_exit(void)975 static void __exit rockchip_otp_exit(void)
976 {
977 return platform_driver_unregister(&rockchip_otp_driver);
978 }
979
980 subsys_initcall(rockchip_otp_init);
981 module_exit(rockchip_otp_exit);
982
983 MODULE_DESCRIPTION("Rockchip OTP driver");
984 MODULE_LICENSE("GPL v2");
985