Lines Matching +full:apb +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
5 * Based on phy-rockchip-inno-usb3.c in Linux Kernel.
12 #include <generic-phy.h>
89 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
90 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
91 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
92 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
110 void __iomem *base; member
128 static inline int param_write(void __iomem *base, in param_write() argument
132 unsigned int tmp = desired ? reg->dvalue : reg->rvalue; in param_write()
135 mask = GENMASK(reg->bitend, reg->bitstart); in param_write()
136 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
137 ret = regmap_write(base, reg->offset, val); in param_write()
142 static inline bool param_exped(void __iomem *base, in param_exped() argument
148 unsigned int mask = GENMASK(reg->bitend, reg->bitstart); in param_exped()
150 ret = regmap_read(base, reg->offset, &orig); in param_exped()
154 tmp = (orig & mask) >> reg->bitstart; in param_exped()
163 ret = uclass_get_device_by_name(UCLASS_PHY, "usb3-phy", &udev); in rockchip_u3phy_uboot_init()
165 pr_err("%s: get usb3-phy node failed: %d\n", __func__, ret); in rockchip_u3phy_uboot_init()
184 struct udevice *parent = dev_get_parent(phy->dev); in rockchip_u3phy_power_on()
189 if (!u3phy->vbus_supply) { in rockchip_u3phy_power_on()
190 ret = device_get_supply_regulator(parent, "vbus-supply", in rockchip_u3phy_power_on()
191 &u3phy->vbus_supply); in rockchip_u3phy_power_on()
192 if (ret == -ENOENT) { in rockchip_u3phy_power_on()
197 ret = regulator_set_enable(u3phy->vbus_supply, true); in rockchip_u3phy_power_on()
209 struct udevice *parent = dev_get_parent(phy->dev); in rockchip_u3phy_power_off()
214 if (u3phy->vbus_supply) { in rockchip_u3phy_power_off()
215 ret = regulator_set_enable(u3phy->vbus_supply, false); in rockchip_u3phy_power_off()
221 u3phy->vbus_supply = NULL; in rockchip_u3phy_power_off()
236 debug("%s: %s subnode not found", __func__, parent->name); in rockchip_u3phy_bind()
237 return -ENXIO; in rockchip_u3phy_bind()
259 return "u3phy-u2-por"; in get_rest_name()
261 return "u3phy-u3-por"; in get_rest_name()
263 return "u3phy-pipe-mac"; in get_rest_name()
265 return "u3phy-utmi-mac"; in get_rest_name()
267 return "u3phy-utmi-apb"; in get_rest_name()
269 return "u3phy-pipe-apb"; in get_rest_name()
281 dev_dbg(u3phy->dev, "deassert APB bus interface reset\n"); in rockchip_u3phy_rest_deassert()
283 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_deassert()
284 reset_deassert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
290 dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n"); in rockchip_u3phy_rest_deassert()
292 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_deassert()
293 reset_deassert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
299 dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n"); in rockchip_u3phy_rest_deassert()
301 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_deassert()
302 reset_deassert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_deassert()
310 dev_dbg(u3phy->dev, "assert u3phy reset\n"); in rockchip_u3phy_rest_assert()
312 if (u3phy->rsts[rst].dev) in rockchip_u3phy_rest_assert()
313 reset_assert(&u3phy->rsts[rst]); in rockchip_u3phy_rest_assert()
324 &u3phy->rsts[i]); in rockchip_u3phy_parse_dt()
340 dev_dbg(u3phy->dev, "u3phy port initialize\n"); in rockchip_u3phy_port_init()
342 mutex_init(&u3phy_port->mutex); in rockchip_u3phy_port_init()
344 u3phy_port->base = (void __iomem *)ofnode_get_addr(np_to_ofnode(child_np)); in rockchip_u3phy_port_init()
345 if (IS_ERR(u3phy_port->base)) { in rockchip_u3phy_port_init()
346 dev_err(u3phy->dev, "failed to remap phy regs\n"); in rockchip_u3phy_port_init()
347 return PTR_ERR(u3phy_port->base); in rockchip_u3phy_port_init()
350 if (!of_node_cmp(child_np->name, "pipe")) { in rockchip_u3phy_port_init()
351 u3phy_port->type = U3PHY_TYPE_PIPE; in rockchip_u3phy_port_init()
352 u3phy_port->refclk_25m_quirk = in rockchip_u3phy_port_init()
354 "rockchip,refclk-25m-quirk"); in rockchip_u3phy_port_init()
356 u3phy_port->type = U3PHY_TYPE_UTMI; in rockchip_u3phy_port_init()
359 if (u3phy->cfgs->phy_tuning) { in rockchip_u3phy_port_init()
360 dev_dbg(u3phy->dev, "do u3phy tuning\n"); in rockchip_u3phy_port_init()
361 ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np); in rockchip_u3phy_port_init()
371 const struct udevice_id *of_match = udev->driver->of_match; in rockchip_u3phy_probe()
378 while (of_match->compatible) { in rockchip_u3phy_probe()
379 if (device_is_compatible(udev, of_match->compatible)) in rockchip_u3phy_probe()
384 if (!of_match || !of_match->data) { in rockchip_u3phy_probe()
385 dev_err(udev, "phy-cfgs are not assigned!\n"); in rockchip_u3phy_probe()
386 return -EINVAL; in rockchip_u3phy_probe()
391 return -EINVAL; in rockchip_u3phy_probe()
394 u3phy->dev = udev; in rockchip_u3phy_probe()
395 phy_cfgs = (const struct rockchip_u3phy_cfg *)of_match->data; in rockchip_u3phy_probe()
401 u3phy->cfgs = &phy_cfgs[index]; in rockchip_u3phy_probe()
407 if (!u3phy->cfgs) { in rockchip_u3phy_probe()
408 dev_err(udev, "no phy-cfgs can be matched\n"); in rockchip_u3phy_probe()
409 return -EINVAL; in rockchip_u3phy_probe()
422 ofnode_for_each_subnode(child_np, udev->node) { in rockchip_u3phy_probe()
423 struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index]; in rockchip_u3phy_probe()
425 u3phy_port->index = index; in rockchip_u3phy_probe()
452 if (u3phy_port->type == U3PHY_TYPE_UTMI) { in rk3328_u3phy_tuning()
454 * For rk3328 SoC, pre-emphasis and pre-emphasis strength must in rk3328_u3phy_tuning()
462 /* {bits[2:0]=111}: always enable pre-emphasis */ in rk3328_u3phy_tuning()
463 u3phy->apbcfg.u2_pre_emp = 0x0f; in rk3328_u3phy_tuning()
465 /* {bits[5:3]=000}: pre-emphasis strength as the weakest */ in rk3328_u3phy_tuning()
466 u3phy->apbcfg.u2_pre_emp_sth = 0x41; in rk3328_u3phy_tuning()
469 u3phy->apbcfg.u2_odt_tuning = 0xb5; in rk3328_u3phy_tuning()
473 "rockchip,odt-val-tuning", in rk3328_u3phy_tuning()
474 &u3phy->apbcfg.u2_odt_tuning); in rk3328_u3phy_tuning()
476 writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030); in rk3328_u3phy_tuning()
477 writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040); in rk3328_u3phy_tuning()
478 writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
479 } else if (u3phy_port->type == U3PHY_TYPE_PIPE) { in rk3328_u3phy_tuning()
480 if (u3phy_port->refclk_25m_quirk) { in rk3328_u3phy_tuning()
481 dev_dbg(u3phy->dev, "switch to 25m refclk\n"); in rk3328_u3phy_tuning()
483 writel(0x64, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
484 writel(0x64, u3phy_port->base + 0x028); in rk3328_u3phy_tuning()
485 writel(0x01, u3phy_port->base + 0x020); in rk3328_u3phy_tuning()
486 writel(0x21, u3phy_port->base + 0x030); in rk3328_u3phy_tuning()
487 writel(0x06, u3phy_port->base + 0x108); in rk3328_u3phy_tuning()
488 writel(0x00, u3phy_port->base + 0x118); in rk3328_u3phy_tuning()
491 writel(0x80, u3phy_port->base + 0x10c); in rk3328_u3phy_tuning()
492 writel(0x01, u3phy_port->base + 0x118); in rk3328_u3phy_tuning()
493 writel(0x38, u3phy_port->base + 0x11c); in rk3328_u3phy_tuning()
494 writel(0x83, u3phy_port->base + 0x020); in rk3328_u3phy_tuning()
495 writel(0x02, u3phy_port->base + 0x108); in rk3328_u3phy_tuning()
500 writel(0x08, u3phy_port->base + 0x000); in rk3328_u3phy_tuning()
501 writel(0x0c, u3phy_port->base + 0x120); in rk3328_u3phy_tuning()
504 writel(0x70, u3phy_port->base + 0x150); in rk3328_u3phy_tuning()
505 writel(0x12, u3phy_port->base + 0x0c8); in rk3328_u3phy_tuning()
506 writel(0x05, u3phy_port->base + 0x148); in rk3328_u3phy_tuning()
507 writel(0x08, u3phy_port->base + 0x068); in rk3328_u3phy_tuning()
508 writel(0xf0, u3phy_port->base + 0x1c4); in rk3328_u3phy_tuning()
509 writel(0xff, u3phy_port->base + 0x070); in rk3328_u3phy_tuning()
510 writel(0x0f, u3phy_port->base + 0x06c); in rk3328_u3phy_tuning()
511 writel(0xe0, u3phy_port->base + 0x060); in rk3328_u3phy_tuning()
518 writel(0x08, u3phy_port->base + 0x180); in rk3328_u3phy_tuning()
520 dev_err(u3phy->dev, "invalid u3phy port type\n"); in rk3328_u3phy_tuning()
521 return -EINVAL; in rk3328_u3phy_tuning()
557 { .compatible = "rockchip,rk3328-u3phy", .data = (ulong)&rk3328_u3phy_cfgs },