1*4882a593Smuzhiyun* Rockchip AXI PCIe Endpoint Controller DT description 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should contain "rockchip,rk3399-pcie-ep" 5*4882a593Smuzhiyun- reg: Two register ranges as listed in the reg-names property 6*4882a593Smuzhiyun- reg-names: Must include the following names 7*4882a593Smuzhiyun - "apb-base" 8*4882a593Smuzhiyun - "mem-base" 9*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 10*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 11*4882a593Smuzhiyun- clock-names: Must include the following entries: 12*4882a593Smuzhiyun - "aclk" 13*4882a593Smuzhiyun - "aclk-perf" 14*4882a593Smuzhiyun - "hclk" 15*4882a593Smuzhiyun - "pm" 16*4882a593Smuzhiyun- resets: Must contain seven entries for each entry in reset-names. 17*4882a593Smuzhiyun See ../reset/reset.txt for details. 18*4882a593Smuzhiyun- reset-names: Must include the following names 19*4882a593Smuzhiyun - "core" 20*4882a593Smuzhiyun - "mgmt" 21*4882a593Smuzhiyun - "mgmt-sticky" 22*4882a593Smuzhiyun - "pipe" 23*4882a593Smuzhiyun - "pm" 24*4882a593Smuzhiyun - "aclk" 25*4882a593Smuzhiyun - "pclk" 26*4882a593Smuzhiyun- pinctrl-names : The pin control state names 27*4882a593Smuzhiyun- pinctrl-0: The "default" pinctrl state 28*4882a593Smuzhiyun- phys: Must contain an phandle to a PHY for each entry in phy-names. 29*4882a593Smuzhiyun- phy-names: Must include 4 entries for all 4 lanes even if some of 30*4882a593Smuzhiyun them won't be used for your cases. Entries are of the form "pcie-phy-N": 31*4882a593Smuzhiyun where N ranges from 0 to 3. 32*4882a593Smuzhiyun (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt 33*4882a593Smuzhiyun for changing the #phy-cells of phy node to support it) 34*4882a593Smuzhiyun- rockchip,max-outbound-regions: Maximum number of outbound regions 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunOptional Property: 37*4882a593Smuzhiyun- num-lanes: number of lanes to use 38*4882a593Smuzhiyun- max-functions: Maximum number of functions that can be configured (default 1). 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunpcie0-ep: pcie@f8000000 { 41*4882a593Smuzhiyun compatible = "rockchip,rk3399-pcie-ep"; 42*4882a593Smuzhiyun #address-cells = <3>; 43*4882a593Smuzhiyun #size-cells = <2>; 44*4882a593Smuzhiyun rockchip,max-outbound-regions = <16>; 45*4882a593Smuzhiyun clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 46*4882a593Smuzhiyun <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 47*4882a593Smuzhiyun clock-names = "aclk", "aclk-perf", 48*4882a593Smuzhiyun "hclk", "pm"; 49*4882a593Smuzhiyun max-functions = /bits/ 8 <8>; 50*4882a593Smuzhiyun num-lanes = <4>; 51*4882a593Smuzhiyun reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>; 52*4882a593Smuzhiyun reg-names = "apb-base", "mem-base"; 53*4882a593Smuzhiyun resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 54*4882a593Smuzhiyun <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , 55*4882a593Smuzhiyun <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; 56*4882a593Smuzhiyun reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 57*4882a593Smuzhiyun "pm", "pclk", "aclk"; 58*4882a593Smuzhiyun phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; 59*4882a593Smuzhiyun phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; 60*4882a593Smuzhiyun pinctrl-names = "default"; 61*4882a593Smuzhiyun pinctrl-0 = <&pcie_clkreq>; 62*4882a593Smuzhiyun}; 63