xref: /OK3568_Linux_fs/kernel/arch/arc/boot/dts/axc001.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/*
7*4882a593Smuzhiyun * Device tree for AXC001 770D/EM6/AS221 CPU card
8*4882a593Smuzhiyun * Note that this file only supports the 770D CPU
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/include/ "skeleton.dtsi"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	compatible = "snps,arc";
15*4882a593Smuzhiyun	#address-cells = <2>;
16*4882a593Smuzhiyun	#size-cells = <2>;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	cpu_card {
19*4882a593Smuzhiyun		compatible = "simple-bus";
20*4882a593Smuzhiyun		#address-cells = <1>;
21*4882a593Smuzhiyun		#size-cells = <1>;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun		core_clk: core_clk {
26*4882a593Smuzhiyun			#clock-cells = <0>;
27*4882a593Smuzhiyun			compatible = "fixed-clock";
28*4882a593Smuzhiyun			clock-frequency = <750000000>;
29*4882a593Smuzhiyun		};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun		input_clk: input-clk {
32*4882a593Smuzhiyun			#clock-cells = <0>;
33*4882a593Smuzhiyun			compatible = "fixed-clock";
34*4882a593Smuzhiyun			clock-frequency = <33333333>;
35*4882a593Smuzhiyun		};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun		core_intc: arc700-intc@cpu {
38*4882a593Smuzhiyun			compatible = "snps,arc700-intc";
39*4882a593Smuzhiyun			interrupt-controller;
40*4882a593Smuzhiyun			#interrupt-cells = <1>;
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		/*
44*4882a593Smuzhiyun		 * this GPIO block ORs all interrupts on CPU card (creg,..)
45*4882a593Smuzhiyun		 * to uplink only 1 IRQ to ARC core intc
46*4882a593Smuzhiyun		 */
47*4882a593Smuzhiyun		dw-apb-gpio@2000 {
48*4882a593Smuzhiyun			compatible = "snps,dw-apb-gpio";
49*4882a593Smuzhiyun			reg = < 0x2000 0x80 >;
50*4882a593Smuzhiyun			#address-cells = <1>;
51*4882a593Smuzhiyun			#size-cells = <0>;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun			ictl_intc: gpio-controller@0 {
54*4882a593Smuzhiyun				compatible = "snps,dw-apb-gpio-port";
55*4882a593Smuzhiyun				gpio-controller;
56*4882a593Smuzhiyun				#gpio-cells = <2>;
57*4882a593Smuzhiyun				snps,nr-gpios = <30>;
58*4882a593Smuzhiyun				reg = <0>;
59*4882a593Smuzhiyun				interrupt-controller;
60*4882a593Smuzhiyun				#interrupt-cells = <2>;
61*4882a593Smuzhiyun				interrupt-parent = <&core_intc>;
62*4882a593Smuzhiyun				interrupts = <15>;
63*4882a593Smuzhiyun			};
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		debug_uart: dw-apb-uart@5000 {
67*4882a593Smuzhiyun			compatible = "snps,dw-apb-uart";
68*4882a593Smuzhiyun			reg = <0x5000 0x100>;
69*4882a593Smuzhiyun			clock-frequency = <33333000>;
70*4882a593Smuzhiyun			interrupt-parent = <&ictl_intc>;
71*4882a593Smuzhiyun			interrupts = <19 4>;
72*4882a593Smuzhiyun			baud = <115200>;
73*4882a593Smuzhiyun			reg-shift = <2>;
74*4882a593Smuzhiyun			reg-io-width = <4>;
75*4882a593Smuzhiyun		};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun		arcpct0: pct {
78*4882a593Smuzhiyun			compatible = "snps,arc700-pct";
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	/*
83*4882a593Smuzhiyun	 * This INTC is actually connected to DW APB GPIO
84*4882a593Smuzhiyun	 * which acts as a wire between MB INTC and CPU INTC.
85*4882a593Smuzhiyun	 * GPIO INTC is configured in platform init code
86*4882a593Smuzhiyun	 * and here we mimic direct connection from MB INTC to
87*4882a593Smuzhiyun	 * CPU INTC, thus we set "interrupts = <7>" instead of
88*4882a593Smuzhiyun	 * "interrupts = <12>"
89*4882a593Smuzhiyun	 *
90*4882a593Smuzhiyun	 * This intc actually resides on MB, but we move it here to
91*4882a593Smuzhiyun	 * avoid duplicating the MB dtsi file given that IRQ from
92*4882a593Smuzhiyun	 * this intc to cpu intc are different for axs101 and axs103
93*4882a593Smuzhiyun	 */
94*4882a593Smuzhiyun	mb_intc: interrupt-controller@e0012000 {
95*4882a593Smuzhiyun		#interrupt-cells = <1>;
96*4882a593Smuzhiyun		compatible = "snps,dw-apb-ictl";
97*4882a593Smuzhiyun		reg = < 0x0 0xe0012000 0x0 0x200 >;
98*4882a593Smuzhiyun		interrupt-controller;
99*4882a593Smuzhiyun		interrupt-parent = <&core_intc>;
100*4882a593Smuzhiyun		interrupts = < 7 >;
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	memory {
104*4882a593Smuzhiyun		device_type = "memory";
105*4882a593Smuzhiyun		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
106*4882a593Smuzhiyun		reg = <0x0 0x80000000 0x0 0x1b000000>;	/* (512 - 32) MiB */
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun	reserved-memory {
110*4882a593Smuzhiyun		#address-cells = <2>;
111*4882a593Smuzhiyun		#size-cells = <2>;
112*4882a593Smuzhiyun		ranges;
113*4882a593Smuzhiyun		/*
114*4882a593Smuzhiyun		 * We just move frame buffer area to the very end of
115*4882a593Smuzhiyun		 * available DDR. And even though in case of ARC770 there's
116*4882a593Smuzhiyun		 * no strict requirement for a frame-buffer to be in any
117*4882a593Smuzhiyun		 * particular location it allows us to use the same
118*4882a593Smuzhiyun		 * base board's DT node for ARC PGU as for ARc HS38.
119*4882a593Smuzhiyun		 */
120*4882a593Smuzhiyun		frame_buffer: frame_buffer@9e000000 {
121*4882a593Smuzhiyun			compatible = "shared-dma-pool";
122*4882a593Smuzhiyun			reg = <0x0 0x9e000000 0x0 0x2000000>;
123*4882a593Smuzhiyun			no-map;
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun	};
126*4882a593Smuzhiyun};
127