1*4882a593SmuzhiyunROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties (phy (parent) node): 4*4882a593Smuzhiyun - compatible: should be one of the listed compatibles: 5*4882a593Smuzhiyun * "rockchip,rk3328-u3phy" 6*4882a593Smuzhiyun * "rockchip,rk322xh-u3phy" 7*4882a593Smuzhiyun - reg : the base address of USB 3.0 PHY. 8*4882a593Smuzhiyun - rockchip,u3phygrf : phandle to the syscon managing the 9*4882a593Smuzhiyun "USB 3.0 PHY general register files". 10*4882a593Smuzhiyun - interrupts : specify an interrupt for each entry in interrupt-names. 11*4882a593Smuzhiyun - interrupt-names : a list which shall be the following entries: 12*4882a593Smuzhiyun * "linestate" : for the host/otg linestate interrupt 13*4882a593Smuzhiyun - clocks : phandle + clock specifier for the phy clocks. 14*4882a593Smuzhiyun - clock-names : 15*4882a593Smuzhiyun * "u3phy-otg" for USB 3.0 PHY utmi 16*4882a593Smuzhiyun * "u3phy-pipe" for USB 3.0 PHY pipe 17*4882a593Smuzhiyun - resets : a list of phandle + reset specifier pairs 18*4882a593Smuzhiyun - reset-names : 19*4882a593Smuzhiyun * "u3phy-u2-por" for the USB 2.0 logic of USB 3.0 PHY 20*4882a593Smuzhiyun * "u3phy-u3-por" for the USB 3.0 logic of USB 3.0 PHY 21*4882a593Smuzhiyun * "u3phy-pipe-mac" for the USB 3.0 PHY pipe MAC 22*4882a593Smuzhiyun * "u3phy-utmi-mac" for the USB 3.0 PHY utmi MAC 23*4882a593Smuzhiyun * "u3phy-utmi-apb" for the USB 3.0 PHY utmi apb 24*4882a593Smuzhiyun * "u3phy-pipe-apb" for the USB 3.0 PHY pipe apb 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunOptional properties: 27*4882a593Smuzhiyun - vbus-supply: regulator phandle for vbus power source. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunRequired nodes : a sub-node is required for USB 3.0 or USB 2.0 the phy provides. 30*4882a593Smuzhiyun The sub-node name is used to identify phy type, and shall be 31*4882a593Smuzhiyun the following entries: 32*4882a593Smuzhiyun * "u3phy_utmi" : USB 2.0 utmi phy. 33*4882a593Smuzhiyun * "u3phy_pipe" : USB 3.0 pipe phy. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunRequired properties (port (child) node): 36*4882a593Smuzhiyun - reg : address and length of the register set for the port. 37*4882a593Smuzhiyun - #phy-cells : must be 0. See ./phy-bindings.txt for details. 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunOptional properties for utmi node: 40*4882a593Smuzhiyun - rockchip,odt-val-tuning : specify 45ohm ODT tuning value. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunOptional properties for pipe node: 43*4882a593Smuzhiyun - rockchip,refclk-25m-quirk : phy reference clock changed to 25m quirk. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunExample: 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunusb3phy_grf: syscon@ff460000 { 48*4882a593Smuzhiyun compatible = "rockchip,usb3phy-grf", "syscon"; 49*4882a593Smuzhiyun reg = <0x0 0xff460000 0x0 0x1000>; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun... 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunu3phy: usb3-phy@ff470000 { 55*4882a593Smuzhiyun compatible = "rockchip,rk3328-u3phy"; 56*4882a593Smuzhiyun reg = <0x0 0xff470000 0x0 0x0>; 57*4882a593Smuzhiyun rockchip,u3phygrf = <&usb3phy_grf>; 58*4882a593Smuzhiyun interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 59*4882a593Smuzhiyun interrupt-names = "linestate"; 60*4882a593Smuzhiyun clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; 61*4882a593Smuzhiyun clock-names = "u3phy-otg", "u3phy-pipe"; 62*4882a593Smuzhiyun resets = <&cru SRST_USB3PHY_U2>, 63*4882a593Smuzhiyun <&cru SRST_USB3PHY_U3>, 64*4882a593Smuzhiyun <&cru SRST_USB3PHY_PIPE>, 65*4882a593Smuzhiyun <&cru SRST_USB3OTG_UTMI>, 66*4882a593Smuzhiyun <&cru SRST_USB3PHY_OTG_P>, 67*4882a593Smuzhiyun <&cru SRST_USB3PHY_PIPE_P>; 68*4882a593Smuzhiyun reset-names = "u3phy-u2-por", "u3phy-u3-por", 69*4882a593Smuzhiyun "u3phy-pipe-mac", "u3phy-utmi-mac", 70*4882a593Smuzhiyun "u3phy-utmi-apb", "u3phy-pipe-apb"; 71*4882a593Smuzhiyun #address-cells = <2>; 72*4882a593Smuzhiyun #size-cells = <2>; 73*4882a593Smuzhiyun ranges; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun u3phy_utmi: utmi@ff470000 { 76*4882a593Smuzhiyun reg = <0x0 0xff470000 0x0 0x8000>; 77*4882a593Smuzhiyun #phy-cells = <0>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun u3phy_pipe: pipe@ff478000 { 81*4882a593Smuzhiyun reg = <0x0 0xff478000 0x0 0x8000>; 82*4882a593Smuzhiyun #phy-cells = <0>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun}; 85