Lines Matching +full:apb +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
108 * +----------+------------------+--------------------------+
110 * +----------+------------------+--------------------------+
112 * +----------+------------------+--------------------------+
114 * +----------+------------------+--------------------------+
116 * +----------+------------------+--------------------------+
118 * +----------+------------------+--------------------------+
120 * +-----+ +------------------+
121 * | wp | -- | wp for oem range |
122 * +-----+ +------------------+
124 * +-----+ +------------------+
126 * +-----+ +------------------+
128 * +-----+ +------------------+
130 * +-----+ +------------------+
132 * +-----+ +------------------+
134 * +-----+ +------------------+
136 * +-----+ +------------------+
138 * +-----+ +------------------+
158 void __iomem *base; member
181 ret = reset_control_assert(otp->rst); in rockchip_otp_reset()
183 dev_err(otp->dev, "failed to assert otp phy %d\n", ret); in rockchip_otp_reset()
189 ret = reset_control_deassert(otp->rst); in rockchip_otp_reset()
191 dev_err(otp->dev, "failed to deassert otp phy %d\n", ret); in rockchip_otp_reset()
203 ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status, in px30_otp_wait_status()
209 writel(flag, otp->base + OTPC_INT_STATUS); in px30_otp_wait_status()
219 otp->base + OTPC_SBPI_CTRL); in px30_otp_ecc_enable()
221 writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE); in px30_otp_ecc_enable()
223 otp->base + OTPC_SBPI_CMD0_OFFSET); in px30_otp_ecc_enable()
225 writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET); in px30_otp_ecc_enable()
227 writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET); in px30_otp_ecc_enable()
229 writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL); in px30_otp_ecc_enable()
233 dev_err(otp->dev, "timeout during ecc_enable\n"); in px30_otp_ecc_enable()
245 ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks); in px30_otp_read()
247 dev_err(otp->dev, "failed to prepare/enable clks\n"); in px30_otp_read()
253 dev_err(otp->dev, "failed to reset otp phy\n"); in px30_otp_read()
259 dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); in px30_otp_read()
263 writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); in px30_otp_read()
265 while (bytes--) { in px30_otp_read()
267 otp->base + OTPC_USER_ADDR); in px30_otp_read()
269 otp->base + OTPC_USER_ENABLE); in px30_otp_read()
272 dev_err(otp->dev, "timeout during read setup\n"); in px30_otp_read()
275 *buf++ = readb(otp->base + OTPC_USER_Q); in px30_otp_read()
279 writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); in px30_otp_read()
281 clk_bulk_disable_unprepare(otp->num_clks, otp->clks); in px30_otp_read()
291 ret = readl_poll_timeout_atomic(otp->base + OTPC_IRQ_ST, status, in px30s_otp_wait_status()
297 writel(flag, otp->base + OTPC_IRQ_ST); in px30s_otp_wait_status()
307 mode = readl(otp->base + OTPC_MODE_CTRL); in px30s_otp_active()
311 writel(OTPC_STANDBY, otp->base + OTPC_MODE_CTRL); in px30s_otp_active()
314 dev_err(otp->dev, "timeout during wait dp2stb\n"); in px30s_otp_active()
319 writel(OTPC_ACTIVE, otp->base + OTPC_MODE_CTRL); in px30s_otp_active()
322 dev_err(otp->dev, "timeout during wait stb2act\n"); in px30s_otp_active()
338 mode = readl(otp->base + OTPC_MODE_CTRL); in px30s_otp_standby()
342 writel(OTPC_STANDBY, otp->base + OTPC_MODE_CTRL); in px30s_otp_standby()
345 dev_err(otp->dev, "timeout during wait act2stb\n"); in px30s_otp_standby()
350 writel(OTPC_DEEP_STANDBY, otp->base + OTPC_MODE_CTRL); in px30s_otp_standby()
353 dev_err(otp->dev, "timeout during wait stb2dp\n"); in px30s_otp_standby()
373 if (offset >= otp->data->size) in px30s_otp_read()
374 return -ENOMEM; in px30s_otp_read()
375 if (offset + bytes > otp->data->size) in px30s_otp_read()
376 bytes = otp->data->size - offset; in px30s_otp_read()
378 ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks); in px30s_otp_read()
380 dev_err(otp->dev, "failed to prepare/enable clks\n"); in px30s_otp_read()
386 dev_err(otp->dev, "failed to reset otp phy\n"); in px30s_otp_read()
397 addr_len = addr_end - addr_start; in px30s_otp_read()
402 ret = -ENOMEM; in px30s_otp_read()
406 while (addr_len--) { in px30s_otp_read()
407 writel(OTPC_TRANS_NUM, otp->base + OTPC_REPR_RD_TRANS_NUM); in px30s_otp_read()
408 writel(addr_start++, otp->base + OTPC_ACCESS_ADDR); in px30s_otp_read()
409 writel(OTPC_READ_ACCESS, otp->base + OTPC_MODE_CTRL); in px30s_otp_read()
412 dev_err(otp->dev, "timeout during wait rd\n"); in px30s_otp_read()
415 out_value = readl(otp->base + OTPC_RD_DATA); in px30s_otp_read()
425 clk_bulk_disable_unprepare(otp->num_clks, otp->clks); in px30s_otp_read()
443 addr_len = addr_end - addr_start; in rk3568_otp_read()
448 return -ENOMEM; in rk3568_otp_read()
450 ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks); in rk3568_otp_read()
452 dev_err(otp->dev, "failed to prepare/enable clks\n"); in rk3568_otp_read()
458 dev_err(otp->dev, "failed to reset otp phy\n"); in rk3568_otp_read()
464 dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); in rk3568_otp_read()
468 writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); in rk3568_otp_read()
470 while (addr_len--) { in rk3568_otp_read()
472 otp->base + OTPC_USER_ADDR); in rk3568_otp_read()
474 otp->base + OTPC_USER_ENABLE); in rk3568_otp_read()
477 dev_err(otp->dev, "timeout during read setup\n"); in rk3568_otp_read()
480 otp_qp = readl(otp->base + OTPC_USER_QP); in rk3568_otp_read()
482 ret = -EIO; in rk3568_otp_read()
483 dev_err(otp->dev, "ecc check error during read setup\n"); in rk3568_otp_read()
486 out_value = readl(otp->base + OTPC_USER_Q); in rk3568_otp_read()
494 writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); in rk3568_otp_read()
496 clk_bulk_disable_unprepare(otp->num_clks, otp->clks); in rk3568_otp_read()
508 ret = readl_poll_timeout_atomic(otp->base + RK3588_OTPC_INT_ST, status, in rk3588_otp_wait_status()
514 writel(flag, otp->base + RK3588_OTPC_INT_ST); in rk3588_otp_wait_status()
528 if (offset >= otp->data->size) in rk3588_otp_read()
529 return -ENOMEM; in rk3588_otp_read()
530 if (offset + bytes > otp->data->size) in rk3588_otp_read()
531 bytes = otp->data->size - offset; in rk3588_otp_read()
536 addr_len = addr_end - addr_start; in rk3588_otp_read()
542 return -ENOMEM; in rk3588_otp_read()
544 ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks); in rk3588_otp_read()
546 dev_err(otp->dev, "failed to prepare/enable clks\n"); in rk3588_otp_read()
550 while (addr_len--) { in rk3588_otp_read()
553 otp->base + RK3588_OTPC_AUTO_CTRL); in rk3588_otp_read()
554 writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN); in rk3588_otp_read()
557 dev_err(otp->dev, "timeout during read setup\n"); in rk3588_otp_read()
561 out_value = readl(otp->base + RK3588_OTPC_DOUT0); in rk3588_otp_read()
570 clk_bulk_disable_unprepare(otp->num_clks, otp->clks); in rk3588_otp_read()
582 writel(0x0, otp->base + RV1126_OTP_NVM_CEB); in rv1126_otp_init()
583 ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_NVM_ST, status, in rv1126_otp_init()
586 dev_err(otp->dev, "timeout during set ceb\n"); in rv1126_otp_init()
590 writel(0x1, otp->base + RV1126_OTP_NVM_RSTB); in rv1126_otp_init()
591 ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_NVM_ST, status, in rv1126_otp_init()
594 dev_err(otp->dev, "timeout during set rstb\n"); in rv1126_otp_init()
598 otp->config->read_only = false; in rv1126_otp_init()
611 while (bytes--) { in rv1126_otp_read()
612 writel(offset++, otp->base + RV1126_OTP_NVM_RADDR); in rv1126_otp_read()
613 writel(0x1, otp->base + RV1126_OTP_NVM_RSTART); in rv1126_otp_read()
614 ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_READ_ST, in rv1126_otp_read()
618 dev_err(otp->dev, "timeout during read setup\n"); in rv1126_otp_read()
622 *buf++ = readb(otp->base + RV1126_OTP_NVM_RDATA); in rv1126_otp_read()
637 writel(bit_offset, otp->base + RV1126_OTP_NVM_PRADDR); in rv1126_otp_prog()
638 writel(bit_len - 1, otp->base + RV1126_OTP_NVM_PRLEN); in rv1126_otp_prog()
639 writel(data, otp->base + RV1126_OTP_NVM_PRDATA); in rv1126_otp_prog()
640 writel(1, otp->base + RV1126_OTP_NVM_PRSTART); in rv1126_otp_prog()
642 ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_NVM_PRSTATE, in rv1126_otp_prog()
646 dev_err(otp->dev, "timeout during prog\n"); in rv1126_otp_prog()
659 while (bytes--) { in rv1126_otp_write()
678 bitmap_set(otp->wp_mask, (offset - RV1126_OTP_OEM_OFFSET) / 4, bytes / 4); in rv1126_otp_wp()
680 return rv1126_otp_write(context, RV1126_OTP_WP_OFFSET, otp->wp_mask, in rv1126_otp_wp()
690 offset > (RV1126_OTP_OEM_OFFSET + RV1126_OTP_OEM_SIZE - 1) || in rv1126_otp_oem_write()
693 return -EINVAL; in rv1126_otp_oem_write()
696 return -EINVAL; in rv1126_otp_oem_write()
709 int ret = -EINVAL; in rockchip_otp_read()
711 mutex_lock(&otp->mutex); in rockchip_otp_read()
712 if (otp->data && otp->data->reg_read) in rockchip_otp_read()
713 ret = otp->data->reg_read(context, offset, val, bytes); in rockchip_otp_read()
714 mutex_unlock(&otp->mutex); in rockchip_otp_read()
723 int ret = -EINVAL; in rockchip_otp_write()
725 mutex_lock(&otp->mutex); in rockchip_otp_write()
727 otp->data && otp->data->reg_write) { in rockchip_otp_write()
728 ret = otp->data->reg_write(context, offset, val, bytes); in rockchip_otp_write()
731 mutex_unlock(&otp->mutex); in rockchip_otp_write()
737 .name = "rockchip-otp",
765 "usr", "sbpi", "apb",
776 "usr", "sbpi", "apb", "arb", "phy",
787 "usr", "sbpi", "apb", "phy",
798 "otpc", "apb", "arb", "phy",
809 "usr", "sbpi", "apb", "phy", "arb", "pmc",
835 .compatible = "rockchip,px30-otp",
839 .compatible = "rockchip,px30s-otp",
845 .compatible = "rockchip,rk3308-otp",
849 .compatible = "rockchip,rk3308bs-otp",
855 .compatible = "rockchip,rk3528-otp",
861 .compatible = "rockchip,rk3562-otp",
867 .compatible = "rockchip,rk3568-otp",
873 .compatible = "rockchip,rk3588-otp",
879 .compatible = "rockchip,rv1106-otp",
885 .compatible = "rockchip,rv1126-otp",
895 struct device *dev = &pdev->dev; in rockchip_otp_probe()
904 return -EINVAL; in rockchip_otp_probe()
909 otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp), in rockchip_otp_probe()
912 return -ENOMEM; in rockchip_otp_probe()
914 mutex_init(&otp->mutex); in rockchip_otp_probe()
915 otp->data = data; in rockchip_otp_probe()
916 otp->dev = dev; in rockchip_otp_probe()
917 otp->base = devm_platform_ioremap_resource(pdev, 0); in rockchip_otp_probe()
918 if (IS_ERR(otp->base)) in rockchip_otp_probe()
919 return PTR_ERR(otp->base); in rockchip_otp_probe()
921 otp->num_clks = data->num_clks; in rockchip_otp_probe()
922 otp->clks = devm_kcalloc(dev, otp->num_clks, in rockchip_otp_probe()
923 sizeof(*otp->clks), GFP_KERNEL); in rockchip_otp_probe()
924 if (!otp->clks) in rockchip_otp_probe()
925 return -ENOMEM; in rockchip_otp_probe()
927 for (i = 0; i < otp->num_clks; ++i) in rockchip_otp_probe()
928 otp->clks[i].id = data->clocks[i]; in rockchip_otp_probe()
930 ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks); in rockchip_otp_probe()
934 otp->rst = devm_reset_control_array_get_optional_exclusive(dev); in rockchip_otp_probe()
935 if (IS_ERR(otp->rst)) in rockchip_otp_probe()
936 return PTR_ERR(otp->rst); in rockchip_otp_probe()
938 otp->config = &otp_config; in rockchip_otp_probe()
939 otp->config->size = data->size; in rockchip_otp_probe()
940 otp->config->priv = otp; in rockchip_otp_probe()
941 otp->config->dev = dev; in rockchip_otp_probe()
943 if (data->init) { in rockchip_otp_probe()
944 ret = data->init(otp); in rockchip_otp_probe()
949 nvmem = devm_nvmem_register(dev, otp->config); in rockchip_otp_probe()
957 .name = "rockchip-otp",