1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5*4882a593Smuzhiyun * Contributor: Mahavir Jain <mjain@marvell.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ASM_ARCH_ARMADA100_H 11*4882a593Smuzhiyun #define _ASM_ARCH_ARMADA100_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #if defined (CONFIG_ARMADA100) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Common APB clock register bit definitions */ 16*4882a593Smuzhiyun #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ 17*4882a593Smuzhiyun #define APBC_FNCLK (1<<1) /* Functional Clock Enable */ 18*4882a593Smuzhiyun #define APBC_RST (1<<2) /* Reset Generation */ 19*4882a593Smuzhiyun /* Functional Clock Selection Mask */ 20*4882a593Smuzhiyun #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Fast Ethernet Controller Clock register definition */ 23*4882a593Smuzhiyun #define FE_CLK_RST 0x1 24*4882a593Smuzhiyun #define FE_CLK_ENA 0x8 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* SSP2 Clock Control */ 27*4882a593Smuzhiyun #define SSP2_APBCLK 0x01 28*4882a593Smuzhiyun #define SSP2_FNCLK 0x02 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* USB Clock/reset control bits */ 31*4882a593Smuzhiyun #define USB_SPH_AXICLK_EN 0x10 32*4882a593Smuzhiyun #define USB_SPH_AXI_RST 0x02 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* MPMU Clocks */ 35*4882a593Smuzhiyun #define APB2_26M_EN (1 << 20) 36*4882a593Smuzhiyun #define AP_26M (1 << 4) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Register Base Addresses */ 39*4882a593Smuzhiyun #define ARMD1_DRAM_BASE 0xB0000000 40*4882a593Smuzhiyun #define ARMD1_FEC_BASE 0xC0800000 41*4882a593Smuzhiyun #define ARMD1_TIMER_BASE 0xD4014000 42*4882a593Smuzhiyun #define ARMD1_APBC1_BASE 0xD4015000 43*4882a593Smuzhiyun #define ARMD1_APBC2_BASE 0xD4015800 44*4882a593Smuzhiyun #define ARMD1_UART1_BASE 0xD4017000 45*4882a593Smuzhiyun #define ARMD1_UART2_BASE 0xD4018000 46*4882a593Smuzhiyun #define ARMD1_GPIO_BASE 0xD4019000 47*4882a593Smuzhiyun #define ARMD1_SSP1_BASE 0xD401B000 48*4882a593Smuzhiyun #define ARMD1_SSP2_BASE 0xD401C000 49*4882a593Smuzhiyun #define ARMD1_MFPR_BASE 0xD401E000 50*4882a593Smuzhiyun #define ARMD1_SSP3_BASE 0xD401F000 51*4882a593Smuzhiyun #define ARMD1_SSP4_BASE 0xD4020000 52*4882a593Smuzhiyun #define ARMD1_SSP5_BASE 0xD4021000 53*4882a593Smuzhiyun #define ARMD1_UART3_BASE 0xD4026000 54*4882a593Smuzhiyun #define ARMD1_MPMU_BASE 0xD4050000 55*4882a593Smuzhiyun #define ARMD1_USB_HOST_BASE 0xD4209000 56*4882a593Smuzhiyun #define ARMD1_APMU_BASE 0xD4282800 57*4882a593Smuzhiyun #define ARMD1_CPU_BASE 0xD4282C00 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif /* CONFIG_ARMADA100 */ 60*4882a593Smuzhiyun #endif /* _ASM_ARCH_ARMADA100_H */ 61