1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: i.MX8M DDR Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Leonard Crestez <leonard.crestez@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun The DDRC block is integrated in i.MX8M for interfacing with DDR based 14*4882a593Smuzhiyun memories. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun It supports switching between different frequencies at runtime but during 17*4882a593Smuzhiyun this process RAM itself becomes briefly inaccessible so actual frequency 18*4882a593Smuzhiyun switching is implemented by TF-A code which runs from a SRAM area. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun The Linux driver for the DDRC doesn't even map registers (they're included 21*4882a593Smuzhiyun for the sake of "describing hardware"), it mostly just exposes firmware 22*4882a593Smuzhiyun capabilities through standard Linux mechanism like devfreq and OPP tables. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunproperties: 25*4882a593Smuzhiyun compatible: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - enum: 28*4882a593Smuzhiyun - fsl,imx8mn-ddrc 29*4882a593Smuzhiyun - fsl,imx8mm-ddrc 30*4882a593Smuzhiyun - fsl,imx8mq-ddrc 31*4882a593Smuzhiyun - const: fsl,imx8m-ddrc 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reg: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun description: 36*4882a593Smuzhiyun Base address and size of DDRC CTL area. 37*4882a593Smuzhiyun This is not currently mapped by the imx8m-ddrc driver. 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clocks: 40*4882a593Smuzhiyun maxItems: 4 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun clock-names: 43*4882a593Smuzhiyun items: 44*4882a593Smuzhiyun - const: core 45*4882a593Smuzhiyun - const: pll 46*4882a593Smuzhiyun - const: alt 47*4882a593Smuzhiyun - const: apb 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun operating-points-v2: true 50*4882a593Smuzhiyun opp-table: true 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunrequired: 53*4882a593Smuzhiyun - reg 54*4882a593Smuzhiyun - compatible 55*4882a593Smuzhiyun - clocks 56*4882a593Smuzhiyun - clock-names 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunadditionalProperties: false 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunexamples: 61*4882a593Smuzhiyun - | 62*4882a593Smuzhiyun #include <dt-bindings/clock/imx8mm-clock.h> 63*4882a593Smuzhiyun ddrc: memory-controller@3d400000 { 64*4882a593Smuzhiyun compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 65*4882a593Smuzhiyun reg = <0x3d400000 0x400000>; 66*4882a593Smuzhiyun clock-names = "core", "pll", "alt", "apb"; 67*4882a593Smuzhiyun clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 68*4882a593Smuzhiyun <&clk IMX8MM_DRAM_PLL>, 69*4882a593Smuzhiyun <&clk IMX8MM_CLK_DRAM_ALT>, 70*4882a593Smuzhiyun <&clk IMX8MM_CLK_DRAM_APB>; 71*4882a593Smuzhiyun operating-points-v2 = <&ddrc_opp_table>; 72*4882a593Smuzhiyun }; 73