1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/ 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Renesas R-Car PCIe Endpoint 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 12*4882a593Smuzhiyun - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunproperties: 15*4882a593Smuzhiyun compatible: 16*4882a593Smuzhiyun items: 17*4882a593Smuzhiyun - enum: 18*4882a593Smuzhiyun - renesas,r8a774a1-pcie-ep # RZ/G2M 19*4882a593Smuzhiyun - renesas,r8a774b1-pcie-ep # RZ/G2N 20*4882a593Smuzhiyun - renesas,r8a774c0-pcie-ep # RZ/G2E 21*4882a593Smuzhiyun - renesas,r8a774e1-pcie-ep # RZ/G2H 22*4882a593Smuzhiyun - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg: 25*4882a593Smuzhiyun maxItems: 5 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg-names: 28*4882a593Smuzhiyun items: 29*4882a593Smuzhiyun - const: apb-base 30*4882a593Smuzhiyun - const: memory0 31*4882a593Smuzhiyun - const: memory1 32*4882a593Smuzhiyun - const: memory2 33*4882a593Smuzhiyun - const: memory3 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun power-domains: 36*4882a593Smuzhiyun maxItems: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun resets: 39*4882a593Smuzhiyun maxItems: 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun clocks: 42*4882a593Smuzhiyun maxItems: 1 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun clock-names: 45*4882a593Smuzhiyun items: 46*4882a593Smuzhiyun - const: pcie 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun max-functions: 49*4882a593Smuzhiyun minimum: 1 50*4882a593Smuzhiyun maximum: 1 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunrequired: 53*4882a593Smuzhiyun - compatible 54*4882a593Smuzhiyun - reg 55*4882a593Smuzhiyun - reg-names 56*4882a593Smuzhiyun - resets 57*4882a593Smuzhiyun - power-domains 58*4882a593Smuzhiyun - clocks 59*4882a593Smuzhiyun - clock-names 60*4882a593Smuzhiyun - max-functions 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunadditionalProperties: false 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunexamples: 65*4882a593Smuzhiyun - | 66*4882a593Smuzhiyun #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 67*4882a593Smuzhiyun #include <dt-bindings/power/r8a774c0-sysc.h> 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun pcie0_ep: pcie-ep@fe000000 { 70*4882a593Smuzhiyun compatible = "renesas,r8a774c0-pcie-ep", 71*4882a593Smuzhiyun "renesas,rcar-gen3-pcie-ep"; 72*4882a593Smuzhiyun reg = <0xfe000000 0x80000>, 73*4882a593Smuzhiyun <0xfe100000 0x100000>, 74*4882a593Smuzhiyun <0xfe200000 0x200000>, 75*4882a593Smuzhiyun <0x30000000 0x8000000>, 76*4882a593Smuzhiyun <0x38000000 0x8000000>; 77*4882a593Smuzhiyun reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 78*4882a593Smuzhiyun resets = <&cpg 319>; 79*4882a593Smuzhiyun power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 80*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 319>; 81*4882a593Smuzhiyun clock-names = "pcie"; 82*4882a593Smuzhiyun max-functions = /bits/ 8 <1>; 83*4882a593Smuzhiyun }; 84