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/OK3568_Linux_fs/kernel/drivers/gpu/drm/etnaviv/
H A Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dmpc8536ds_36b.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0xf 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
35 0x2 0x0 0xf 0xffa00000 0x00040000
36 0x3 0x0 0xf 0xffdf0000 0x00008000>;
40 ranges = <0x0 0xf 0xffe00000 0x100000>;
44 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/OK3568_Linux_fs/kernel/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]
/OK3568_Linux_fs/kernel/Documentation/x86/
H A Dmtrr.rst73 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
74 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
78 # echo "base=0xf8000000 size=0x400000 type=write-combining" >! /proc/mtrr
82 # echo "base=0xf8000000 size=0x400000 type=write-combining" >| /proc/mtrr
87 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
88 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
89 reg02: base=0xf8000000 (3968MB), size= 4MB: write-combining, count=1
91 This is for video RAM at base address 0xf8000000 and size 4 megabytes. To
96 (--) S3: PCI: 968 rev 0, Linear FB @ 0xf8000000
107 That's 4 megabytes, which is 0x400000 bytes (in hexadecimal).
[all …]
/OK3568_Linux_fs/kernel/arch/arm/include/debug/
H A Dsa1100.S10 #define UTCR3 0x0c
11 #define UTDR 0x14
12 #define UTSR1 0x20
13 #define UTCR3_TXE 0x00000002 /* Transmit Enable */
14 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
15 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
18 mrc p15, 0, \rp, c1, c0
20 moveq \rp, #0x80000000 @ physical base address
21 movne \rp, #0xf8000000 @ virtual address
28 add \rp, \rp, #0x00050000
[all …]
H A Dvt8500.S10 #define DEBUG_LL_PHYS_BASE 0xD8000000
11 #define DEBUG_LL_VIRT_BASE 0xF8000000
12 #define DEBUG_LL_UART_OFFSET 0x00200000
22 strb \rd, [\rx, #0]
26 1001: ldr \rd, [\rx, #0x1c]
27 ands \rd, \rd, #0x2
H A Dvexpress.S10 #define DEBUG_LL_PHYS_BASE 0x10000000
11 #define DEBUG_LL_UART_OFFSET 0x00009000
13 #define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
14 #define DEBUG_LL_UART_OFFSET_RS1 0x00090000
16 #define DEBUG_LL_UART_PHYS_CRX 0xb0090000
18 #define DEBUG_LL_VIRT_BASE 0xf8000000
27 @ should use UART at 0x10009000
29 @ at 0x1c090000
30 mrc p15, 0, \rp, c0, c0, 0
31 movw \rv, #0xc091
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/mpc8544ds/
H A Dtlb.c14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A DMPC8568MDS.h13 #define CONFIG_SYS_TEXT_BASE 0xfff80000
44 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
45 #define CONFIG_SYS_MEMTEST_END 0x00400000
47 #define CONFIG_SYS_CCSRBAR 0xe0000000
56 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
58 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
65 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
81 * Boot from BR0/OR0 bank at 0xff00_0000
82 * Alternate BR1/OR1 bank at 0xff80_0000
85 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
[all …]
H A DMPC8541CDS.h19 #define CONFIG_SYS_TEXT_BASE 0xfff80000
39 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
40 #define CONFIG_SYS_MEMTEST_END 0x00400000
42 #define CONFIG_SYS_CCSRBAR 0xe0000000
50 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
59 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
77 * Boot from BR0/OR0 bank at 0xff00_0000
78 * Alternate BR1/OR1 bank at 0xff80_0000
81 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
[all …]
H A DMPC8555CDS.h19 #define CONFIG_SYS_TEXT_BASE 0xfff80000
39 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
40 #define CONFIG_SYS_MEMTEST_END 0x00400000
42 #define CONFIG_SYS_CCSRBAR 0xe0000000
50 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
59 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
75 * Boot from BR0/OR0 bank at 0xff00_0000
76 * Alternate BR1/OR1 bank at 0xff80_0000
79 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
[all …]
H A DMPC8548CDS.h17 #define CONFIG_SYS_TEXT_BASE 0xfff80000
58 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
59 #define CONFIG_SYS_MEMTEST_END 0x00400000
61 #define CONFIG_SYS_CCSRBAR 0xe0000000
71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
80 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
92 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
93 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
94 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
[all …]
H A Drk1808_common.h13 #define CONFIG_SPL_TEXT_BASE 0x00000000
14 #define CONFIG_SPL_MAX_SIZE 0x00020000
15 #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
16 #define CONFIG_SPL_BSS_MAX_SIZE 0x00002000
17 #define CONFIG_SPL_STACK 0x03fe0000
22 #define CONFIG_SYS_TEXT_BASE 0x00600000
23 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000
24 #define CONFIG_SYS_LOAD_ADDR 0x00800800
28 #define GICD_BASE 0xff100000
29 #define GICR_BASE 0xff140000
[all …]
H A Drk3399_common.h20 #define CONFIG_SYS_TEXT_BASE 0x00200000
21 #define CONFIG_SYS_INIT_SP_ADDR 0x00400000
22 #define CONFIG_SYS_LOAD_ADDR 0x00800800
23 #define CONFIG_SPL_STACK 0x00400000
24 #define CONFIG_SPL_TEXT_BASE 0x00000000
25 #define CONFIG_SPL_MAX_SIZE 0x40000
26 #define CONFIG_SPL_BSS_START_ADDR 0x00400000
27 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
30 #define GICD_BASE 0xFEE00000
31 #define GICR_BASE 0xFEF00000
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler.h24 0xbf820001, 0xbf820121,
25 0xb8f4f802, 0x89748674,
26 0xb8f5f803, 0x8675ff75,
27 0x00000400, 0xbf850017,
28 0xc00a1e37, 0x00000000,
29 0xbf8c007f, 0x87777978,
30 0xbf840005, 0x8f728374,
31 0xb972e0c2, 0xbf800002,
32 0xb9740002, 0xbe801d78,
33 0xb8f5f803, 0x8675ff75,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d3.h24 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
36 #define ATMEL_ID_USART0 12 /* USART 0 */
42 #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
45 #define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
48 #define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
62 #define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
76 #define ARCH_ID_SAMA5D3 0x8a5c07c0
77 #define ARCH_EXID_SAMA5D31 0x00444300
78 #define ARCH_EXID_SAMA5D33 0x00414300
79 #define ARCH_EXID_SAMA5D34 0x00414301
[all …]
H A Dsama5d4.h21 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt */
27 #define ATMEL_ID_USART0 6 /* USART 0 */
29 #define ATMEL_ID_DMA0 8 /* DMA Controller 0 */
46 #define ATMEL_ID_UART0 27 /* UART 0 */
51 #define ATMEL_ID_TWI0 32 /* Two-Wire Interface 0 */
54 #define ATMEL_ID_MCI0 35 /* High Speed Multimedia Card Interface 0 */
56 #define ATMEL_ID_SPI0 37 /* Serial Peripheral Interface 0 */
59 #define ATMEL_ID_TC0 40 /* Timer Counter 0 (ch. 0, 1, 2) */
67 #define ATMEL_ID_SSC0 48 /* Synchronous Serial Controller 0 */
73 #define ATMEL_ID_GMAC0 54 /* Ethernet MAC 0 */
[all …]
/OK3568_Linux_fs/kernel/sound/isa/gus/
H A Dgus_volume.c24 while (e > 0 && tmp < (1 << e)) in snd_gf1_lvol_to_gvol_raw()
33 if (m > 0) { in snd_gf1_lvol_to_gvol_raw()
43 #if 0
51 return 0;
81 vol_rates[0] :
83 for (i = 0; i < 3; i++) {
95 return (range << 6) | (increment & 0x3f);
98 #endif /* 0 */
105 if (freq16 & 0xf8000000) { in snd_gf1_translate_freq()
106 freq16 = ~0xf8000000; in snd_gf1_translate_freq()
[all …]
/OK3568_Linux_fs/u-boot/board/sbc8641d/
H A Dlaw.c17 * 0x0000_0000 DDR 256M
18 * 0x1000_0000 DDR2 256M
19 * 0x8000_0000 PCIE1 MEM 512M
20 * 0xa000_0000 PCIE2 MEM 512M
21 * 0xc000_0000 RapidIO 512M
22 * 0xe200_0000 PCIE1 IO 16M
23 * 0xe300_0000 PCIE2 IO 16M
24 * 0xf800_0000 CCSRBAR 2M
25 * 0xfe00_0000 FLASH (boot bank) 32M
33 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Daxis.txt23 reg = <0xf8000000 0x48>;
/OK3568_Linux_fs/kernel/sound/pci/hda/
H A Dca0132_regs.h12 #define DSP_CHIP_OFFSET 0x100000
13 #define DSP_DBGCNTL_MODULE_OFFSET 0xE30
17 #define DSP_DBGCNTL_EXEC_LOBIT 0x0
18 #define DSP_DBGCNTL_EXEC_HIBIT 0x3
19 #define DSP_DBGCNTL_EXEC_MASK 0xF
21 #define DSP_DBGCNTL_SS_LOBIT 0x4
22 #define DSP_DBGCNTL_SS_HIBIT 0x7
23 #define DSP_DBGCNTL_SS_MASK 0xF0
25 #define DSP_DBGCNTL_STATE_LOBIT 0xA
26 #define DSP_DBGCNTL_STATE_HIBIT 0xD
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dhisilicon,hi655x.txt19 - #clock-cells: From common clock binding; shall be set to 0
28 reg = <0x0 0xf8000000 0x0 0x1000>;
32 #clock-cells = <0>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dat91sam9x5_can.dtsi17 reg = <0xf8000000 0x300>;
20 pinctrl-0 = <&pinctrl_can0_rx_tx>;
28 reg = <0xf8004000 0x300>;
31 pinctrl-0 = <&pinctrl_can1_rx_tx>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dartpec6.txt30 #clock-cells = <0>;
38 reg = <0xf8000000 0x48>;

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