1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * IO mappings for OMAP2+ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * IO definitions for TI OMAP processors and boards 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copied from arch/arm/mach-sa1100/include/mach/io.h 7*4882a593Smuzhiyun * Copyright (C) 1997-1999 Russell King 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Copyright (C) 2009-2012 Texas Instruments 10*4882a593Smuzhiyun * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 13*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the 14*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your 15*4882a593Smuzhiyun * option) any later version. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 18*4882a593Smuzhiyun * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20*4882a593Smuzhiyun * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21*4882a593Smuzhiyun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22*4882a593Smuzhiyun * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 23*4882a593Smuzhiyun * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 24*4882a593Smuzhiyun * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26*4882a593Smuzhiyun * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along 29*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc., 30*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define OMAP2_L3_IO_OFFSET 0x90000000 34*4882a593Smuzhiyun #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define OMAP2_L4_IO_OFFSET 0xb2000000 37*4882a593Smuzhiyun #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define OMAP4_L3_IO_OFFSET 0xb4000000 40*4882a593Smuzhiyun #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define AM33XX_L4_WK_IO_OFFSET 0xb5000000 43*4882a593Smuzhiyun #define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define OMAP4_L3_PER_IO_OFFSET 0xb1100000 46*4882a593Smuzhiyun #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ 49*4882a593Smuzhiyun #define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 53*4882a593Smuzhiyun * Omap2 specific IO mapping 54*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* We map both L3 and L4 on OMAP2 */ 58*4882a593Smuzhiyun #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ 59*4882a593Smuzhiyun #define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) 60*4882a593Smuzhiyun #define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 61*4882a593Smuzhiyun #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ 62*4882a593Smuzhiyun #define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) 63*4882a593Smuzhiyun #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ 66*4882a593Smuzhiyun #define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) 67*4882a593Smuzhiyun #define L4_WK_243X_SIZE SZ_1M 68*4882a593Smuzhiyun #define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE 69*4882a593Smuzhiyun #define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) 70*4882a593Smuzhiyun /* 0x6e000000 --> 0xfe000000 */ 71*4882a593Smuzhiyun #define OMAP243X_GPMC_SIZE SZ_1M 72*4882a593Smuzhiyun #define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE 73*4882a593Smuzhiyun /* 0x6D000000 --> 0xfd000000 */ 74*4882a593Smuzhiyun #define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) 75*4882a593Smuzhiyun #define OMAP243X_SDRC_SIZE SZ_1M 76*4882a593Smuzhiyun #define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE 77*4882a593Smuzhiyun /* 0x6c000000 --> 0xfc000000 */ 78*4882a593Smuzhiyun #define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) 79*4882a593Smuzhiyun #define OMAP243X_SMS_SIZE SZ_1M 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 2420 IVA */ 82*4882a593Smuzhiyun #define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE 83*4882a593Smuzhiyun /* 0x58000000 --> 0xfc100000 */ 84*4882a593Smuzhiyun #define DSP_MEM_2420_VIRT 0xfc100000 85*4882a593Smuzhiyun #define DSP_MEM_2420_SIZE 0x28000 86*4882a593Smuzhiyun #define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE 87*4882a593Smuzhiyun /* 0x59000000 --> 0xfc128000 */ 88*4882a593Smuzhiyun #define DSP_IPI_2420_VIRT 0xfc128000 89*4882a593Smuzhiyun #define DSP_IPI_2420_SIZE SZ_4K 90*4882a593Smuzhiyun #define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE 91*4882a593Smuzhiyun /* 0x5a000000 --> 0xfc129000 */ 92*4882a593Smuzhiyun #define DSP_MMU_2420_VIRT 0xfc129000 93*4882a593Smuzhiyun #define DSP_MMU_2420_SIZE SZ_4K 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 2430 IVA2.1 - currently unmapped */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* 98*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 99*4882a593Smuzhiyun * Omap3 specific IO mapping 100*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 101*4882a593Smuzhiyun */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* We map both L3 and L4 on OMAP3 */ 104*4882a593Smuzhiyun #define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ 105*4882a593Smuzhiyun #define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) 106*4882a593Smuzhiyun #define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ 109*4882a593Smuzhiyun #define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) 110*4882a593Smuzhiyun #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 114*4882a593Smuzhiyun * AM33XX specific IO mapping 115*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun #define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE 118*4882a593Smuzhiyun #define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET) 119*4882a593Smuzhiyun #define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* 122*4882a593Smuzhiyun * Need to look at the Size 4M for L4. 123*4882a593Smuzhiyun * VPOM3430 was not working for Int controller 124*4882a593Smuzhiyun */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define L4_PER_34XX_PHYS L4_PER_34XX_BASE 127*4882a593Smuzhiyun /* 0x49000000 --> 0xfb000000 */ 128*4882a593Smuzhiyun #define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) 129*4882a593Smuzhiyun #define L4_PER_34XX_SIZE SZ_1M 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE 132*4882a593Smuzhiyun /* 0x54000000 --> 0xfe800000 */ 133*4882a593Smuzhiyun #define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) 134*4882a593Smuzhiyun #define L4_EMU_34XX_SIZE SZ_8M 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE 137*4882a593Smuzhiyun /* 0x6e000000 --> 0xfe000000 */ 138*4882a593Smuzhiyun #define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) 139*4882a593Smuzhiyun #define OMAP34XX_GPMC_SIZE SZ_1M 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE 142*4882a593Smuzhiyun /* 0x6c000000 --> 0xfc000000 */ 143*4882a593Smuzhiyun #define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) 144*4882a593Smuzhiyun #define OMAP343X_SMS_SIZE SZ_1M 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE 147*4882a593Smuzhiyun /* 0x6D000000 --> 0xfd000000 */ 148*4882a593Smuzhiyun #define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) 149*4882a593Smuzhiyun #define OMAP343X_SDRC_SIZE SZ_1M 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* 3430 IVA - currently unmapped */ 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* 154*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 155*4882a593Smuzhiyun * Omap4 specific IO mapping 156*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 157*4882a593Smuzhiyun */ 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* We map both L3 and L4 on OMAP4 */ 160*4882a593Smuzhiyun #define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ 161*4882a593Smuzhiyun #define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) 162*4882a593Smuzhiyun #define L3_44XX_SIZE SZ_1M 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ 165*4882a593Smuzhiyun #define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) 166*4882a593Smuzhiyun #define L4_44XX_SIZE SZ_4M 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #define L4_PER_44XX_PHYS L4_PER_44XX_BASE 169*4882a593Smuzhiyun /* 0x48000000 --> 0xfa000000 */ 170*4882a593Smuzhiyun #define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) 171*4882a593Smuzhiyun #define L4_PER_44XX_SIZE SZ_4M 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE 174*4882a593Smuzhiyun /* 0x49000000 --> 0xfb000000 */ 175*4882a593Smuzhiyun #define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) 176*4882a593Smuzhiyun #define L4_ABE_44XX_SIZE SZ_1M 177*4882a593Smuzhiyun /* 178*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 179*4882a593Smuzhiyun * Omap5 specific IO mapping 180*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 181*4882a593Smuzhiyun */ 182*4882a593Smuzhiyun #define L3_54XX_PHYS L3_54XX_BASE /* 0x44000000 --> 0xf8000000 */ 183*4882a593Smuzhiyun #define L3_54XX_VIRT (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET) 184*4882a593Smuzhiyun #define L3_54XX_SIZE SZ_1M 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define L4_54XX_PHYS L4_54XX_BASE /* 0x4a000000 --> 0xfc000000 */ 187*4882a593Smuzhiyun #define L4_54XX_VIRT (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET) 188*4882a593Smuzhiyun #define L4_54XX_SIZE SZ_4M 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define L4_WK_54XX_PHYS L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */ 191*4882a593Smuzhiyun #define L4_WK_54XX_VIRT (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET) 192*4882a593Smuzhiyun #define L4_WK_54XX_SIZE SZ_2M 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun #define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */ 195*4882a593Smuzhiyun #define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET) 196*4882a593Smuzhiyun #define L4_PER_54XX_SIZE SZ_4M 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* 199*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 200*4882a593Smuzhiyun * DRA7xx specific IO mapping 201*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 202*4882a593Smuzhiyun */ 203*4882a593Smuzhiyun /* 204*4882a593Smuzhiyun * L3_MAIN_SN_DRA7XX_PHYS 0x44000000 --> 0xf8000000 205*4882a593Smuzhiyun * The overall space is 24MiB (0x4400_0000<->0x457F_FFFF), but mapping 206*4882a593Smuzhiyun * everything is just inefficient, since, there are too many address holes. 207*4882a593Smuzhiyun */ 208*4882a593Smuzhiyun #define L3_MAIN_SN_DRA7XX_PHYS L3_MAIN_SN_DRA7XX_BASE 209*4882a593Smuzhiyun #define L3_MAIN_SN_DRA7XX_VIRT (L3_MAIN_SN_DRA7XX_PHYS + OMAP4_L3_IO_OFFSET) 210*4882a593Smuzhiyun #define L3_MAIN_SN_DRA7XX_SIZE SZ_1M 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun /* 213*4882a593Smuzhiyun * L4_PER1_DRA7XX_PHYS (0x4800_000<>0x480D_2FFF) -> 0.82MiB (alloc 1MiB) 214*4882a593Smuzhiyun * (0x48000000<->0x48100000) <=> (0xFA000000<->0xFA100000) 215*4882a593Smuzhiyun */ 216*4882a593Smuzhiyun #define L4_PER1_DRA7XX_PHYS L4_PER1_DRA7XX_BASE 217*4882a593Smuzhiyun #define L4_PER1_DRA7XX_VIRT (L4_PER1_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 218*4882a593Smuzhiyun #define L4_PER1_DRA7XX_SIZE SZ_1M 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* 221*4882a593Smuzhiyun * L4_CFG_MPU_DRA7XX_PHYS (0x48210000<>0x482A_F2FF) -> 0.62MiB (alloc 1MiB) 222*4882a593Smuzhiyun * (0x48210000<->0x48310000) <=> (0xFA210000<->0xFA310000) 223*4882a593Smuzhiyun * NOTE: This is a bit of an orphan memory map sitting isolated in TRM 224*4882a593Smuzhiyun */ 225*4882a593Smuzhiyun #define L4_CFG_MPU_DRA7XX_PHYS L4_CFG_MPU_DRA7XX_BASE 226*4882a593Smuzhiyun #define L4_CFG_MPU_DRA7XX_VIRT (L4_CFG_MPU_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 227*4882a593Smuzhiyun #define L4_CFG_MPU_DRA7XX_SIZE SZ_1M 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun /* 230*4882a593Smuzhiyun * L4_PER2_DRA7XX_PHYS (0x4840_0000<>0x4848_8FFF) -> .53MiB (alloc 1MiB) 231*4882a593Smuzhiyun * (0x48400000<->0x48500000) <=> (0xFA400000<->0xFA500000) 232*4882a593Smuzhiyun */ 233*4882a593Smuzhiyun #define L4_PER2_DRA7XX_PHYS L4_PER2_DRA7XX_BASE 234*4882a593Smuzhiyun #define L4_PER2_DRA7XX_VIRT (L4_PER2_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 235*4882a593Smuzhiyun #define L4_PER2_DRA7XX_SIZE SZ_1M 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* 238*4882a593Smuzhiyun * L4_PER3_DRA7XX_PHYS (0x4880_0000<>0x489E_0FFF) -> 1.87MiB (alloc 2MiB) 239*4882a593Smuzhiyun * (0x48800000<->0x48A00000) <=> (0xFA800000<->0xFAA00000) 240*4882a593Smuzhiyun */ 241*4882a593Smuzhiyun #define L4_PER3_DRA7XX_PHYS L4_PER3_DRA7XX_BASE 242*4882a593Smuzhiyun #define L4_PER3_DRA7XX_VIRT (L4_PER3_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 243*4882a593Smuzhiyun #define L4_PER3_DRA7XX_SIZE SZ_2M 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* 246*4882a593Smuzhiyun * L4_CFG_DRA7XX_PHYS (0x4A00_0000<>0x4A22_BFFF) ->2.17MiB (alloc 3MiB)? 247*4882a593Smuzhiyun * (0x4A000000<->0x4A300000) <=> (0xFC000000<->0xFC300000) 248*4882a593Smuzhiyun */ 249*4882a593Smuzhiyun #define L4_CFG_DRA7XX_PHYS L4_CFG_DRA7XX_BASE 250*4882a593Smuzhiyun #define L4_CFG_DRA7XX_VIRT (L4_CFG_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 251*4882a593Smuzhiyun #define L4_CFG_DRA7XX_SIZE (SZ_1M + SZ_2M) 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun /* 254*4882a593Smuzhiyun * L4_WKUP_DRA7XX_PHYS (0x4AE0_0000<>0x4AE3_EFFF) -> .24 mb (alloc 1MiB)? 255*4882a593Smuzhiyun * (0x4AE00000<->4AF00000) <=> (0xFCE00000<->0xFCF00000) 256*4882a593Smuzhiyun */ 257*4882a593Smuzhiyun #define L4_WKUP_DRA7XX_PHYS L4_WKUP_DRA7XX_BASE 258*4882a593Smuzhiyun #define L4_WKUP_DRA7XX_VIRT (L4_WKUP_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET) 259*4882a593Smuzhiyun #define L4_WKUP_DRA7XX_SIZE SZ_1M 260