Lines Matching +full:0 +full:xf8000000
19 #define CONFIG_SYS_TEXT_BASE 0xfff80000
39 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
40 #define CONFIG_SYS_MEMTEST_END 0x00400000
42 #define CONFIG_SYS_CCSRBAR 0xe0000000
50 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
59 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
77 * Boot from BR0/OR0 bank at 0xff00_0000
78 * Alternate BR1/OR1 bank at 0xff80_0000
81 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
82 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
87 * 0 4 8 12 16 20 24 28
92 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
100 * 0 4 8 12 16 20 24 28
104 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
106 #define CONFIG_SYS_BR0_PRELIM 0xff801001
107 #define CONFIG_SYS_BR1_PRELIM 0xff001001
109 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
110 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
112 #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
128 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
133 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
136 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
142 * 0 4 8 12 16 20 24 28
149 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
155 * 64MB mask for AM, OR2[0:7] = 1111 1100
161 * 0 4 8 12 16 20 24 28
165 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
167 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
168 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
169 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
170 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
189 * The new memory map places CADMUS at 0xf8000000.
192 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
198 * 0 4 8 12 16 20 24 28
202 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
203 * disable buffer ctrl OR[19] = 0
208 * SETA OR[28] = 0
213 * 0 4 8 12 16 20 24 28
219 #define CADMUS_BASE_ADDR 0xf8000000
220 #define CONFIG_SYS_BR3_PRELIM 0xf8000801
221 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
224 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
225 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
237 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
242 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
243 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
251 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
252 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
253 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
259 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
264 * Memory space is mapped 1-1, but I/O space must start from 0.
266 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
267 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
268 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
269 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
270 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
271 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
272 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
273 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
275 #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
276 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
277 #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
278 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
279 #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
280 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
281 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
282 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
300 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
311 #define TSEC1_PHY_ADDR 0
313 #define TSEC1_PHYIDX 0
314 #define TSEC2_PHYIDX 0
318 /* Options are: TSEC[0-1] */
326 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
327 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
328 #define CONFIG_ENV_SIZE 0x2000
349 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
387 "netdev=eth0\0" \
388 "consoledev=ttyS1\0" \
389 "ramdiskaddr=600000\0" \
390 "ramdiskfile=your.ramdisk.u-boot\0" \
391 "fdtaddr=400000\0" \
392 "fdtfile=your.fdt.dtb\0"