Lines Matching +full:0 +full:xf8000000

14 	/* TLB 0 - for temp stack in cache */
15 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
16 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 		      0, 0, BOOKE_PAGESZ_4K, 0),
18 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 		      0, 0, BOOKE_PAGESZ_4K, 0),
21 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 		      0, 0, BOOKE_PAGESZ_4K, 0),
24 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 		      0, 0, BOOKE_PAGESZ_4K, 0),
28 	 * TLB 0:	64M	Non-cacheable, guarded
29 	 * 0xfc000000	64M	Covers FLASH at 0xFE800000 and 0xFF800000
34 		      0, 0, BOOKE_PAGESZ_64M, 1),
37 	 * 0x80000000	1G	PCIE  8,9,a,b
41 		      0, 1, BOOKE_PAGESZ_1G, 1),
48 		      0, 2, BOOKE_PAGESZ_256M, 1),
53 	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
55 		      0, 3, BOOKE_PAGESZ_256M, 1),
59 	 * 0xe000_0000	1M	CCSRBAR
60 	 * 0xe100_0000	255M	PCI IO range
64 		      0, 4, BOOKE_PAGESZ_64M, 1),
68 	 * 0xf8000000	64M	PIXIS 0xF8000000 - 0xFBFFFFFF
72 		      0, 5, BOOKE_PAGESZ_64M, 1),