1*4882a593SmuzhiyunHisilicon Hi655x Power Management Integrated Circuit (PMIC) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe hardware layout for access PMIC Hi655x from AP SoC Hi6220. 4*4882a593SmuzhiyunBetween PMIC Hi655x and Hi6220, the physical signal channel is SSI. 5*4882a593SmuzhiyunWe can use memory-mapped I/O to communicate. 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun+----------------+ +-------------+ 8*4882a593Smuzhiyun| | | | 9*4882a593Smuzhiyun| Hi6220 | SSI bus | Hi655x | 10*4882a593Smuzhiyun| |-------------| | 11*4882a593Smuzhiyun| |(REGMAP_MMIO)| | 12*4882a593Smuzhiyun+----------------+ +-------------+ 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties: 15*4882a593Smuzhiyun- compatible: Should be "hisilicon,hi655x-pmic". 16*4882a593Smuzhiyun- reg: Base address of PMIC on Hi6220 SoC. 17*4882a593Smuzhiyun- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain). 18*4882a593Smuzhiyun- pmic-gpios: The GPIO used by PMIC IRQ. 19*4882a593Smuzhiyun- #clock-cells: From common clock binding; shall be set to 0 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional properties: 22*4882a593Smuzhiyun- clock-output-names: From common clock binding to override the 23*4882a593Smuzhiyun default output clock name 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun pmic: pmic@f8000000 { 27*4882a593Smuzhiyun compatible = "hisilicon,hi655x-pmic"; 28*4882a593Smuzhiyun reg = <0x0 0xf8000000 0x0 0x1000>; 29*4882a593Smuzhiyun interrupt-controller; 30*4882a593Smuzhiyun #interrupt-cells = <2>; 31*4882a593Smuzhiyun pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 32*4882a593Smuzhiyun #clock-cells = <0>; 33*4882a593Smuzhiyun } 34