1*4882a593Smuzhiyun* Clock bindings for Axis ARTPEC-6 chip 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe bindings are based on the clock provider binding in 4*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunExternal clocks: 7*4882a593Smuzhiyun---------------- 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThere are two external inputs to the main clock controller which should be 10*4882a593Smuzhiyunprovided using the common clock bindings. 11*4882a593Smuzhiyun- "sys_refclk": External 50 Mhz oscillator (required) 12*4882a593Smuzhiyun- "i2s_refclk": Alternate audio reference clock (optional). 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunMain clock controller 15*4882a593Smuzhiyun--------------------- 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunRequired properties: 18*4882a593Smuzhiyun- #clock-cells: Should be <1> 19*4882a593Smuzhiyun See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers. 20*4882a593Smuzhiyun- compatible: Should be "axis,artpec6-clkctrl" 21*4882a593Smuzhiyun- reg: Must contain the base address and length of the system controller 22*4882a593Smuzhiyun- clocks: Must contain a phandle entry for each clock in clock-names 23*4882a593Smuzhiyun- clock-names: Must include the external oscillator ("sys_refclk"). Optional 24*4882a593Smuzhiyun ones are the audio reference clock ("i2s_refclk") and the audio fractional 25*4882a593Smuzhiyun dividers ("frac_clk0" and "frac_clk1"). 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExamples: 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunext_clk: ext_clk { 30*4882a593Smuzhiyun #clock-cells = <0>; 31*4882a593Smuzhiyun compatible = "fixed-clock"; 32*4882a593Smuzhiyun clock-frequency = <50000000>; 33*4882a593Smuzhiyun}; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunclkctrl: clkctrl@f8000000 { 36*4882a593Smuzhiyun #clock-cells = <1>; 37*4882a593Smuzhiyun compatible = "axis,artpec6-clkctrl"; 38*4882a593Smuzhiyun reg = <0xf8000000 0x48>; 39*4882a593Smuzhiyun clocks = <&ext_clk>; 40*4882a593Smuzhiyun clock-names = "sys_refclk"; 41*4882a593Smuzhiyun}; 42