Lines Matching +full:0 +full:xf8000000
17 #define CONFIG_SYS_TEXT_BASE 0xfff80000
58 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
59 #define CONFIG_SYS_MEMTEST_END 0x00400000
61 #define CONFIG_SYS_CCSRBAR 0xe0000000
71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
80 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
92 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
93 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
94 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
95 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
96 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
97 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
98 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
99 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
100 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
101 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
102 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
105 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
106 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
107 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
108 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
109 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
110 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
111 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
112 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
113 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
114 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
115 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
126 * Boot from BR0/OR0 bank at 0xff00_0000
127 * Alternate BR1/OR1 bank at 0xff80_0000
130 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
131 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
136 * 0 4 8 12 16 20 24 28
141 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
149 * 0 4 8 12 16 20 24 28
153 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
155 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
161 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
165 #define CONFIG_SYS_OR0_PRELIM 0xff806e65
166 #define CONFIG_SYS_OR1_PRELIM 0xff806e65
169 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
187 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
189 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
197 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
200 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
206 * 0 4 8 12 16 20 24 28
221 * 64MB mask for AM, OR2[0:7] = 1111 1100
227 * 0 4 8 12 16 20 24 28
231 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
233 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
234 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
235 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
236 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
255 * The new memory map places CADMUS at 0xf8000000.
258 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
264 * 0 4 8 12 16 20 24 28
268 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
269 * disable buffer ctrl OR[19] = 0
274 * SETA OR[28] = 0
279 * 0 4 8 12 16 20 24 28
285 #define CADMUS_BASE_ADDR 0xf8000000
287 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
293 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
296 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
297 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
309 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
314 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
315 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
323 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
324 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
325 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
331 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
336 * Memory space is mapped 1-1, but I/O space must start from 0.
338 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
340 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
341 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
343 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
344 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
346 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
347 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
348 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
350 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
352 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
354 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
358 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
360 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
361 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
363 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
364 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
366 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
367 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
368 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
370 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
372 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
374 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
380 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
382 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
384 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
386 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
419 #define TSEC1_PHY_ADDR 0
424 #define TSEC1_PHYIDX 0
425 #define TSEC2_PHYIDX 0
426 #define TSEC3_PHYIDX 0
427 #define TSEC4_PHYIDX 0
433 /* Options are: eTSEC[0-3] */
440 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
441 #define CONFIG_ENV_ADDR 0xfff80000
445 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
446 #define CONFIG_ENV_SIZE 0x2000
467 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
505 "hwconfig=fsl_ddr:ecc=off\0" \
506 "netdev=eth0\0" \
507 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
518 " $filesize\0" \
519 "consoledev=ttyS1\0" \
520 "ramdiskaddr=2000000\0" \
521 "ramdiskfile=ramdisk.uboot\0" \
522 "fdtaddr=1e00000\0" \
523 "fdtfile=mpc8548cds.dtb\0"