1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* arch/arm/include/debug/sa1100.S 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Debugging macro include header 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1994-1999 Russell King 7*4882a593Smuzhiyun * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks 8*4882a593Smuzhiyun*/ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#define UTCR3 0x0c 11*4882a593Smuzhiyun#define UTDR 0x14 12*4882a593Smuzhiyun#define UTSR1 0x20 13*4882a593Smuzhiyun#define UTCR3_TXE 0x00000002 /* Transmit Enable */ 14*4882a593Smuzhiyun#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ 15*4882a593Smuzhiyun#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun .macro addruart, rp, rv, tmp 18*4882a593Smuzhiyun mrc p15, 0, \rp, c1, c0 19*4882a593Smuzhiyun tst \rp, #1 @ MMU enabled? 20*4882a593Smuzhiyun moveq \rp, #0x80000000 @ physical base address 21*4882a593Smuzhiyun movne \rp, #0xf8000000 @ virtual address 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun @ We probe for the active serial port here, coherently with 24*4882a593Smuzhiyun @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h. 25*4882a593Smuzhiyun @ We assume r1 can be clobbered. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun @ see if Ser3 is active 28*4882a593Smuzhiyun add \rp, \rp, #0x00050000 29*4882a593Smuzhiyun ldr \rv, [\rp, #UTCR3] 30*4882a593Smuzhiyun tst \rv, #UTCR3_TXE 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun @ if Ser3 is inactive, then try Ser1 33*4882a593Smuzhiyun addeq \rp, \rp, #(0x00010000 - 0x00050000) 34*4882a593Smuzhiyun ldreq \rv, [\rp, #UTCR3] 35*4882a593Smuzhiyun tsteq \rv, #UTCR3_TXE 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun @ if Ser1 is inactive, then try Ser2 38*4882a593Smuzhiyun addeq \rp, \rp, #(0x00030000 - 0x00010000) 39*4882a593Smuzhiyun ldreq \rv, [\rp, #UTCR3] 40*4882a593Smuzhiyun tsteq \rv, #UTCR3_TXE 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun @ clear top bits, and generate both phys and virt addresses 43*4882a593Smuzhiyun lsl \rp, \rp, #8 44*4882a593Smuzhiyun lsr \rp, \rp, #8 45*4882a593Smuzhiyun orr \rv, \rp, #0xf8000000 @ virtual 46*4882a593Smuzhiyun orr \rp, \rp, #0x80000000 @ physical 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun .endm 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun .macro senduart,rd,rx 51*4882a593Smuzhiyun str \rd, [\rx, #UTDR] 52*4882a593Smuzhiyun .endm 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun .macro waituartcts,rd,rx 55*4882a593Smuzhiyun .endm 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun .macro waituarttxrdy,rd,rx 58*4882a593Smuzhiyun1001: ldr \rd, [\rx, #UTSR1] 59*4882a593Smuzhiyun tst \rd, #UTSR1_TNF 60*4882a593Smuzhiyun beq 1001b 61*4882a593Smuzhiyun .endm 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun .macro busyuart,rd,rx 64*4882a593Smuzhiyun1001: ldr \rd, [\rx, #UTSR1] 65*4882a593Smuzhiyun tst \rd, #UTSR1_TBY 66*4882a593Smuzhiyun bne 1001b 67*4882a593Smuzhiyun .endm 68