1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 4*4882a593Smuzhiyun * Ethernet interface. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h> 10*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun ahb { 14*4882a593Smuzhiyun apb { 15*4882a593Smuzhiyun can0: can@f8000000 { 16*4882a593Smuzhiyun compatible = "atmel,at91sam9x5-can"; 17*4882a593Smuzhiyun reg = <0xf8000000 0x300>; 18*4882a593Smuzhiyun interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; 19*4882a593Smuzhiyun pinctrl-names = "default"; 20*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can0_rx_tx>; 21*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 22*4882a593Smuzhiyun clock-names = "can_clk"; 23*4882a593Smuzhiyun status = "disabled"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun can1: can@f8004000 { 27*4882a593Smuzhiyun compatible = "atmel,at91sam9x5-can"; 28*4882a593Smuzhiyun reg = <0xf8004000 0x300>; 29*4882a593Smuzhiyun interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; 30*4882a593Smuzhiyun pinctrl-names = "default"; 31*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1_rx_tx>; 32*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 33*4882a593Smuzhiyun clock-names = "can_clk"; 34*4882a593Smuzhiyun status = "disabled"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun pinctrl@fffff400 { 38*4882a593Smuzhiyun can0 { 39*4882a593Smuzhiyun pinctrl_can0_rx_tx: can0_rx_tx { 40*4882a593Smuzhiyun atmel,pins = 41*4882a593Smuzhiyun <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0, conflicts with DRXD */ 42*4882a593Smuzhiyun AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX0, conflicts with DTXD */ 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun can1 { 47*4882a593Smuzhiyun pinctrl_can1_rx_tx: can1_rx_tx { 48*4882a593Smuzhiyun atmel,pins = 49*4882a593Smuzhiyun <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1, conflicts with RXD1 */ 50*4882a593Smuzhiyun AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX1, conflicts with TXD1 */ 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun}; 57