Lines Matching +full:0 +full:xf8000000
13 #define CONFIG_SYS_TEXT_BASE 0xfff80000
44 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
45 #define CONFIG_SYS_MEMTEST_END 0x00400000
47 #define CONFIG_SYS_CCSRBAR 0xe0000000
56 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
58 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
65 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
81 * Boot from BR0/OR0 bank at 0xff00_0000
82 * Alternate BR1/OR1 bank at 0xff80_0000
85 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
86 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
91 * 0 4 8 12 16 20 24 28
96 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
104 * 0 4 8 12 16 20 24 28
107 #define CONFIG_SYS_BCSR_BASE 0xf8000000
109 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
111 /*Chip select 0 - Flash*/
112 #define CONFIG_SYS_BR0_PRELIM 0xfe001001
113 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
116 #define CONFIG_SYS_BR1_PRELIM 0xf8000801
117 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
119 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
135 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
139 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
140 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
142 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
143 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
144 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
145 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
164 * The new memory map places bcsr at 0xf8000000.
167 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
173 * 0 4 8 12 16 20 24 28
177 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
178 * disable buffer ctrl OR[19] = 0
183 * SETA OR[28] = 0
188 * 0 4 8 12 16 20 24 28
191 #define CONFIG_SYS_BCSR (0xf8000000)
194 #define CONFIG_SYS_BR4_PRELIM 0xf8008801
195 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
198 #define CONFIG_SYS_BR5_PRELIM 0xf8010801
199 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7
202 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
203 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
215 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
220 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
221 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
229 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
230 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
232 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
233 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
234 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
235 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
239 * Memory Addresses are mapped 1-1. I/O is mapped from 0
241 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
242 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
243 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
244 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
245 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
246 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
247 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
248 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
251 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
252 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
253 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
254 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
255 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
256 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
257 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
258 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
260 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
261 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
263 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
277 #define CONFIG_MIIM_ADDRESS 0xE0024520
283 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
310 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
325 #define TSEC1_PHYIDX 0
326 #define TSEC2_PHYIDX 0
331 /* Options are: eTSEC[0-1] */
339 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
340 #define CONFIG_ENV_SIZE 0x2000
362 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
401 "netdev=eth0\0" \
402 "consoledev=ttyS0\0" \
403 "ramdiskaddr=600000\0" \
404 "ramdiskfile=your.ramdisk.u-boot\0" \
405 "fdtaddr=400000\0" \
406 "fdtfile=your.fdt.dtb\0" \
410 "console=$consoledev,$baudrate $othbootargs\0" \
412 "console=$consoledev,$baudrate $othbootargs\0" \