1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __CONFIG_RK1808_COMMON_H 8*4882a593Smuzhiyun #define __CONFIG_RK1808_COMMON_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "rockchip-common.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 13*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x00000000 14*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE 0x00020000 15*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 17*4882a593Smuzhiyun #define CONFIG_SPL_STACK 0x03fe0000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 21*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 22*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00600000 23*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 24*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x00800800 25*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 26*4882a593Smuzhiyun #define COUNTER_FREQUENCY 24000000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define GICD_BASE 0xff100000 29*4882a593Smuzhiyun #define GICR_BASE 0xff140000 30*4882a593Smuzhiyun #define GICC_BASE 0xff300000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* MMC/SD IP block */ 33*4882a593Smuzhiyun #define CONFIG_BOUNCE_BUFFER 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Nand */ 36*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 37*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 38*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE 2048 39*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT 64 40*4882a593Smuzhiyun #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 41*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0 44*4882a593Smuzhiyun #define SDRAM_MAX_SIZE 0xf8000000 45*4882a593Smuzhiyun #define SDRAM_BANK_SIZE (2UL << 30) 46*4882a593Smuzhiyun #define CONFIG_PREBOOT 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 49*4882a593Smuzhiyun /* usb mass storage */ 50*4882a593Smuzhiyun #define CONFIG_USB_FUNCTION_MASS_STORAGE 51*4882a593Smuzhiyun #define CONFIG_ROCKUSB_G_DNL_PID 0x330d 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define ENV_MEM_LAYOUT_SETTINGS \ 54*4882a593Smuzhiyun "scriptaddr=0x00500000\0" \ 55*4882a593Smuzhiyun "pxefile_addr_r=0x00600000\0" \ 56*4882a593Smuzhiyun "fdt_addr_r=0x01f00000\0" \ 57*4882a593Smuzhiyun "kernel_addr_no_low_bl32_r=0x00280000\0" \ 58*4882a593Smuzhiyun "kernel_addr_r=0x00680000\0" \ 59*4882a593Smuzhiyun "kernel_addr_c=0x04080000\0" \ 60*4882a593Smuzhiyun "ramdisk_addr_r=0x0a200000\0" 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #include <config_distro_bootcmd.h> 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 65*4882a593Smuzhiyun ENV_MEM_LAYOUT_SETTINGS \ 66*4882a593Smuzhiyun "partitions=" PARTS_DEFAULT \ 67*4882a593Smuzhiyun ROCKCHIP_DEVICE_SETTINGS \ 68*4882a593Smuzhiyun RKIMG_DET_BOOTDEV \ 69*4882a593Smuzhiyun BOOTENV 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #endif /* __CONFIG_RK1808_COMMON_H */ 73