1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2000 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/mmu.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 14*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 15*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 16*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 17*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 18*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 19*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 20*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 21*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 23*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 24*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * TLB 0: 64M Non-cacheable, guarded 29*4882a593Smuzhiyun * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 30*4882a593Smuzhiyun * Out of reset this entry is only 4K. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK, 33*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 34*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_64M, 1), 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * TLB 1: 1G Non-cacheable, guarded 37*4882a593Smuzhiyun * 0x80000000 1G PCIE 8,9,a,b 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS, 40*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_1G, 1), 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * TLB 2: 256M Non-cacheable, guarded 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, 47*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 48*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_256M, 1), 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun * TLB 3: 256M Non-cacheable, guarded 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, 54*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_256M, 1), 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * TLB 4: 64M Non-cacheable, guarded 59*4882a593Smuzhiyun * 0xe000_0000 1M CCSRBAR 60*4882a593Smuzhiyun * 0xe100_0000 255M PCI IO range 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 63*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 64*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_64M, 1), 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* 67*4882a593Smuzhiyun * TLB 5: 64M Non-cacheable, guarded 68*4882a593Smuzhiyun * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE, 71*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 72*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_64M, 1), 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 76