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12

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Difc.txt37 reg = <0x0 0xffe1e000 0 0x2000>;
42 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
43 0x1 0x0 0x0 0xffa00000 0x00010000
44 0x3 0x0 0x0 0xffb00000 0x00020000>;
46 flash@0,0 {
50 reg = <0x0 0x0 0x2000000>;
54 partition@0 {
56 reg = <0x0 0x02000000>;
61 flash@1,0 {
65 reg = <0x1 0x0 0x10000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Drenesas,usb-xhci.yaml82 reg = <0xee000000 0xc00>;
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/fsl/
H A Dp1010rdb_32b.dtsi41 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
42 0x1 0x0 0x0 0xff800000 0x00010000
43 0x3 0x0 0x0 0xffb00000 0x00000020>;
44 reg = <0x0 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 reg = <0 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xa0000000
[all …]
H A Dp1010rdb_36b.dtsi41 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
42 0x1 0x0 0xf 0xff800000 0x00010000
43 0x3 0x0 0xf 0xffb00000 0x00000020>;
44 reg = <0xf 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0xf 0xffe00000 0x100000>;
52 reg = <0xf 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xc0000000
[all …]
/OK3568_Linux_fs/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c14 #define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
15 #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
16 #define SERDES_COMLANE_REGS 0x0a00
17 #define SERDES_WIZ_REGS 0x1fc0
19 #define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
20 #define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
21 #define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
22 #define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
23 #define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
24 #define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/
H A Dpcm990_baseboard.h29 #define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
30 #define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
31 #define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
32 #define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
34 #define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
35 #define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
36 #define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
37 #define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
39 #define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
40 #define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dxpedite537x.h22 #define CONFIG_SYS_TEXT_BASE 0xfff80000
37 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
48 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
49 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
73 #define CONFIG_SYS_CCSRBAR 0xef000000
[all …]
H A Dxpedite550x.h24 #define CONFIG_SYS_TEXT_BASE 0xfff80000
38 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 #define SPD_EEPROM_ADDRESS 0x54
48 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
63 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
72 #define CONFIG_SYS_CCSRBAR 0xef000000
79 #define CONFIG_SYS_MEMTEST_START 0x10000000
[all …]
H A DP1010RDB.h21 #define CONFIG_SYS_TEXT_BASE 0x11001000
22 #define CONFIG_SPL_TEXT_BASE 0xD0001000
23 #define CONFIG_SPL_PAD_TO 0x18000
26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
40 #define CONFIG_SYS_TEXT_BASE 0x11000000
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
46 #define CONFIG_SYS_TEXT_BASE 0x11001000
47 #define CONFIG_SPL_TEXT_BASE 0xD0001000
48 #define CONFIG_SPL_PAD_TO 0x18000
[all …]
H A Dp1_p2_rdb_pc.h17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0xe4
19 #define __SW_BOOT_SD 0x54
25 #define __SW_BOOT_MASK 0x03
26 #define __SW_BOOT_NOR 0xe0
27 #define __SW_BOOT_SD 0x50
36 #define __SW_BOOT_MASK 0x03
37 #define __SW_BOOT_NOR 0x5c
38 #define __SW_BOOT_SPI 0x1c
39 #define __SW_BOOT_SD 0x9c
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.b4860qds75 for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for
122 SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
134 SW1 [1.1] = 0
139 SW2 [1.1] = 0
147 SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
159 SW1 [1.1] = 0
164 SW2 [1.1] = 0
172 0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
173 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
174 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
[all …]
/OK3568_Linux_fs/kernel/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/via/
H A Dvia_3d_reg.h27 #define HC_REG_BASE 0x0400
29 #define HC_REG_TRANS_SPACE 0x0040
31 #define HC_ParaN_MASK 0xffffffff
32 #define HC_Para_MASK 0x00ffffff
33 #define HC_SubA_MASK 0xff000000
37 #define HC_REG_TRANS_SET 0x003c
38 #define HC_ParaSubType_MASK 0xff000000
39 #define HC_ParaType_MASK 0x00ff0000
40 #define HC_ParaOS_MASK 0x0000ff00
41 #define HC_ParaAdr_MASK 0x000000ff
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dr8a7795.dtsi38 #size-cells = <0>;
40 a57_0: cpu@0 {
42 reg = <0x0>;
51 reg = <0x1>;
60 reg = <0x2>;
69 reg = <0x3>;
78 reg = <0x100>;
87 reg = <0x101>;
96 reg = <0x102>;
105 reg = <0x103>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/renesas/
H A Dr8a774c0.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a77990.dtsi29 * The external audio clocks are configured as 0 Hz fixed frequency
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
81 #size-cells = <0>;
[all …]
H A Dr8a77961.dtsi20 * The external audio clocks are configured as 0 Hz fixed frequency
26 #clock-cells = <0>;
27 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
118 #size-cells = <0>;
[all …]
H A Dr8a774a1.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #clock-cells = <0>;
45 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
106 #size-cells = <0>;
[all …]
H A Dr8a774b1.dtsi21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
74 #size-cells = <0>;
[all …]

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