Lines Matching +full:0 +full:xee000000
24 #define CONFIG_SYS_TEXT_BASE 0xfff80000
38 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 #define SPD_EEPROM_ADDRESS 0x54
48 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
63 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
72 #define CONFIG_SYS_CCSRBAR 0xef000000
79 #define CONFIG_SYS_MEMTEST_START 0x10000000
80 #define CONFIG_SYS_MEMTEST_END 0x20000000
93 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
94 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
95 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
96 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
97 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
98 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
99 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
100 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
101 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
109 #define CONFIG_SYS_NAND_BASE 0xef800000
110 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
119 #define CONFIG_SYS_FLASH_BASE 0xf8000000
120 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
129 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
130 {0xf7f40000, 0xc0000} }
136 /* NOR Flash 0 on CS0 */
184 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
185 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
199 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
200 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
201 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
215 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
216 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
218 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
219 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
222 #define CONFIG_SYS_I2C_LM75_ADDR 0x48
225 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C
228 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
235 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
240 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
241 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
242 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
243 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
249 /* PCA9557 @ 0x18*/
250 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
251 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232…
252 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
253 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232…
254 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
255 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
257 /* PCA9557 @ 0x1e*/
258 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
259 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
260 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
261 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
262 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
263 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
264 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
266 /* PCA9557 @ 0x1f */
267 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
268 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
269 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
270 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
271 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
272 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
273 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
274 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
278 * Memory space is mapped 1-1, but I/O space must start from 0.
282 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
284 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
285 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
286 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
287 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
312 #define TSEC1_PHYIDX 0
319 #define TSEC2_PHYIDX 0
326 #define TSEC3_PHYIDX 0
339 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
342 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
357 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
358 #define CONFIG_ENV_SIZE 0x8000
375 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
376 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
377 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
378 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
379 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
380 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
384 "if test $? -eq 0; then " \
390 "if test $? -ne 0; then " \
401 "if test $? -eq 0; then " \
407 "if test $? -ne 0; then " \
418 "if test $? -eq 0; then " \
421 "if test $? -eq 0; then " \
435 "if test $? -eq 0; then " \
439 "if test $? -ne 0; then " \
450 "if test $? -eq 0; then " \
454 "if test $? -ne 0; then " \
465 "if test $? -eq 0; then " \
469 "if test $? -ne 0; then " \
480 "if test $? -eq 0; then " \
484 "if test $? -ne 0; then " \
494 "autoload=yes\0" \
495 "download_cmd=tftp\0" \
496 "console_args=console=ttyS0,115200\0" \
497 "root_args=root=/dev/nfs rw\0" \
498 "misc_args=ip=on\0" \
499 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
500 "bootfile=/home/user/file\0" \
501 "osfile=/home/user/board.uImage\0" \
502 "fdtfile=/home/user/board.dtb\0" \
503 "ubootfile=/home/user/u-boot.bin\0" \
504 "fdtaddr=0x1e00000\0" \
505 "osaddr=0x1000000\0" \
506 "loadaddr=0x1000000\0" \
507 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
508 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
509 "prog_os1="CONFIG_PROG_OS1"\0" \
510 "prog_os2="CONFIG_PROG_OS2"\0" \
511 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
512 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
513 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
515 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
517 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
518 "bootcmd=run bootcmd_flash1\0"