include/configs/xpedite537x.h

22 #define CONFIG_SYS_TEXT_BASE	0xfff80000
37 #define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
46 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
47 #define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
48 #define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
49 #define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
54 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
63 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
64 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
73 #define CONFIG_SYS_CCSRBAR		0xef000000
80 #define CONFIG_SYS_MEMTEST_START	0x10000000
81 #define CONFIG_SYS_MEMTEST_END		0x20000000
84 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
85 #define I2C_ADDR_IGNORE_LIST		{0x50}
89  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
90  * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
91  * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
92  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
93  * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
94  * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
95  * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
96  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
97  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
98  * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
99  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
107 #define CONFIG_SYS_NAND_BASE		0xef800000
108 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
117 #define CONFIG_SYS_FLASH_BASE		0xf8000000
118 #define CONFIG_SYS_FLASH_BASE2		0xf0000000
127 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
128 						  {0xf7f40000, 0xc0000} }
134 /* NOR Flash 0 on CS0 */
182 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
183 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
197 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
198 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
199 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
211 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
212 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
214 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
215 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
216 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
219 #define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
222 #define CONFIG_SYS_I2C_LM90_ADDR	0x4c
225 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
232 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
237 #define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
238 #define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
239 #define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
240 #define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
247 /* PCA9557 @ 0x18*/
248 #define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
249 #define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
250 #define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
251 #define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
252 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
253 #define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
254 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
255 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
257 /* PCA9557 @ 0x1c*/
258 #define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
259 #define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
260 #define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
261 #define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
262 #define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
263 #define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
264 #define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
265 #define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
267 /* PCA9557 @ 0x1e*/
268 #define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
269 #define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
270 #define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
271 #define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
272 #define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
273 #define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
274 #define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
276 /* PCA9557 @ 0x1f */
277 #define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
278 #define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
279 #define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
280 #define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
281 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
285  * Memory space is mapped 1-1, but I/O space must start from 0.
288 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
290 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
291 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
292 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
293 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
296 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
298 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
299 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
300 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
301 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
326 #define TSEC1_PHYIDX		0
333 #define TSEC2_PHYIDX		0
340 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
343 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
358 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
359 #define CONFIG_ENV_SIZE		0x8000
376 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
377 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
378 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
379 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
380 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
381 #define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
385 	"if test $? -eq 0; then "					\
391 		"if test $? -ne 0; then "				\
402 	"if test $? -eq 0; then "					\
408 		"if test $? -ne 0; then "				\
419 	"if test $? -eq 0; then "					\
422 			"if test $? -eq 0; then "			\
436 	"if test $? -eq 0; then "					\
440 		"if test $? -ne 0; then "				\
451 	"if test $? -eq 0; then "					\
455 		"if test $? -ne 0; then "				\
466 	"if test $? -eq 0; then "					\
470 		"if test $? -ne 0; then "				\
481 	"if test $? -eq 0; then "					\
485 		"if test $? -ne 0; then "				\
495 	"autoload=yes\0"						\
496 	"download_cmd=tftp\0"						\
497 	"console_args=console=ttyS0,115200\0"				\
498 	"root_args=root=/dev/nfs rw\0"					\
499 	"misc_args=ip=on\0"						\
500 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
501 	"bootfile=/home/user/file\0"					\
502 	"osfile=/home/user/board.uImage\0"				\
503 	"fdtfile=/home/user/board.dtb\0"				\
504 	"ubootfile=/home/user/u-boot.bin\0"				\
505 	"fdtaddr=0x1e00000\0"						\
506 	"osaddr=0x1000000\0"						\
507 	"loadaddr=0x1000000\0"						\
508 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
509 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
510 	"prog_os1="CONFIG_PROG_OS1"\0"					\
511 	"prog_os2="CONFIG_PROG_OS2"\0"					\
512 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
513 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
514 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
516 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
518 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
519 	"bootcmd=run bootcmd_flash1\0"