1 /* 2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TARGET_P1020MBG) 14 #define CONFIG_BOARDNAME "P1020MBG-PC" 15 #define CONFIG_VSC7385_ENET 16 #define CONFIG_SLIC 17 #define __SW_BOOT_MASK 0x03 18 #define __SW_BOOT_NOR 0xe4 19 #define __SW_BOOT_SD 0x54 20 #define CONFIG_SYS_L2_SIZE (256 << 10) 21 #endif 22 23 #if defined(CONFIG_TARGET_P1020UTM) 24 #define CONFIG_BOARDNAME "P1020UTM-PC" 25 #define __SW_BOOT_MASK 0x03 26 #define __SW_BOOT_NOR 0xe0 27 #define __SW_BOOT_SD 0x50 28 #define CONFIG_SYS_L2_SIZE (256 << 10) 29 #endif 30 31 #if defined(CONFIG_TARGET_P1020RDB_PC) 32 #define CONFIG_BOARDNAME "P1020RDB-PC" 33 #define CONFIG_NAND_FSL_ELBC 34 #define CONFIG_VSC7385_ENET 35 #define CONFIG_SLIC 36 #define __SW_BOOT_MASK 0x03 37 #define __SW_BOOT_NOR 0x5c 38 #define __SW_BOOT_SPI 0x1c 39 #define __SW_BOOT_SD 0x9c 40 #define __SW_BOOT_NAND 0xec 41 #define __SW_BOOT_PCIE 0x6c 42 #define CONFIG_SYS_L2_SIZE (256 << 10) 43 #endif 44 45 /* 46 * P1020RDB-PD board has user selectable switches for evaluating different 47 * frequency and boot options for the P1020 device. The table that 48 * follow describe the available options. The front six binary number was in 49 * accordance with SW3[1:6]. 50 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 51 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 52 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 53 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 54 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 55 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 56 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 57 */ 58 #if defined(CONFIG_TARGET_P1020RDB_PD) 59 #define CONFIG_BOARDNAME "P1020RDB-PD" 60 #define CONFIG_NAND_FSL_ELBC 61 #define CONFIG_VSC7385_ENET 62 #define CONFIG_SLIC 63 #define __SW_BOOT_MASK 0x03 64 #define __SW_BOOT_NOR 0x64 65 #define __SW_BOOT_SPI 0x34 66 #define __SW_BOOT_SD 0x24 67 #define __SW_BOOT_NAND 0x44 68 #define __SW_BOOT_PCIE 0x74 69 #define CONFIG_SYS_L2_SIZE (256 << 10) 70 /* 71 * Dynamic MTD Partition support with mtdparts 72 */ 73 #define CONFIG_FLASH_CFI_MTD 74 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 75 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ 76 "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" 77 #endif 78 79 #if defined(CONFIG_TARGET_P1021RDB) 80 #define CONFIG_BOARDNAME "P1021RDB-PC" 81 #define CONFIG_NAND_FSL_ELBC 82 #define CONFIG_QE 83 #define CONFIG_VSC7385_ENET 84 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 85 addresses in the LBC */ 86 #define __SW_BOOT_MASK 0x03 87 #define __SW_BOOT_NOR 0x5c 88 #define __SW_BOOT_SPI 0x1c 89 #define __SW_BOOT_SD 0x9c 90 #define __SW_BOOT_NAND 0xec 91 #define __SW_BOOT_PCIE 0x6c 92 #define CONFIG_SYS_L2_SIZE (256 << 10) 93 /* 94 * Dynamic MTD Partition support with mtdparts 95 */ 96 #define CONFIG_FLASH_CFI_MTD 97 #ifdef CONFIG_PHYS_64BIT 98 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 99 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 100 "256k(dtb),4608k(kernel),9728k(fs)," \ 101 "256k(qe-ucode-firmware),1280k(u-boot)" 102 #else 103 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 104 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 105 "256k(dtb),4608k(kernel),9728k(fs)," \ 106 "256k(qe-ucode-firmware),1280k(u-boot)" 107 #endif 108 #endif 109 110 #if defined(CONFIG_TARGET_P1024RDB) 111 #define CONFIG_BOARDNAME "P1024RDB" 112 #define CONFIG_NAND_FSL_ELBC 113 #define CONFIG_SLIC 114 #define __SW_BOOT_MASK 0xf3 115 #define __SW_BOOT_NOR 0x00 116 #define __SW_BOOT_SPI 0x08 117 #define __SW_BOOT_SD 0x04 118 #define __SW_BOOT_NAND 0x0c 119 #define CONFIG_SYS_L2_SIZE (256 << 10) 120 #endif 121 122 #if defined(CONFIG_TARGET_P1025RDB) 123 #define CONFIG_BOARDNAME "P1025RDB" 124 #define CONFIG_NAND_FSL_ELBC 125 #define CONFIG_QE 126 #define CONFIG_SLIC 127 128 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 129 addresses in the LBC */ 130 #define __SW_BOOT_MASK 0xf3 131 #define __SW_BOOT_NOR 0x00 132 #define __SW_BOOT_SPI 0x08 133 #define __SW_BOOT_SD 0x04 134 #define __SW_BOOT_NAND 0x0c 135 #define CONFIG_SYS_L2_SIZE (256 << 10) 136 #endif 137 138 #if defined(CONFIG_TARGET_P2020RDB) 139 #define CONFIG_BOARDNAME "P2020RDB-PC" 140 #define CONFIG_NAND_FSL_ELBC 141 #define CONFIG_VSC7385_ENET 142 #define __SW_BOOT_MASK 0x03 143 #define __SW_BOOT_NOR 0xc8 144 #define __SW_BOOT_SPI 0x28 145 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 146 #define __SW_BOOT_NAND 0xe8 147 #define __SW_BOOT_PCIE 0xa8 148 #define CONFIG_SYS_L2_SIZE (512 << 10) 149 /* 150 * Dynamic MTD Partition support with mtdparts 151 */ 152 #define CONFIG_FLASH_CFI_MTD 153 #ifdef CONFIG_PHYS_64BIT 154 #define MTDIDS_DEFAULT "nor0=fef000000.nor" 155 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ 156 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 157 #else 158 #define MTDIDS_DEFAULT "nor0=ef000000.nor" 159 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ 160 "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" 161 #endif 162 #endif 163 164 #ifdef CONFIG_SDCARD 165 #define CONFIG_SPL_MMC_MINIMAL 166 #define CONFIG_SPL_FLUSH_IMAGE 167 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 168 #define CONFIG_SYS_TEXT_BASE 0x11001000 169 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 170 #define CONFIG_SPL_PAD_TO 0x20000 171 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 172 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 173 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 174 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 175 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 176 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 177 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 178 #define CONFIG_SPL_MMC_BOOT 179 #ifdef CONFIG_SPL_BUILD 180 #define CONFIG_SPL_COMMON_INIT_DDR 181 #endif 182 #endif 183 184 #ifdef CONFIG_SPIFLASH 185 #define CONFIG_SPL_SPI_FLASH_MINIMAL 186 #define CONFIG_SPL_FLUSH_IMAGE 187 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 188 #define CONFIG_SYS_TEXT_BASE 0x11001000 189 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 190 #define CONFIG_SPL_PAD_TO 0x20000 191 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 192 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 193 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 194 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 195 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 196 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 197 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 198 #define CONFIG_SPL_SPI_BOOT 199 #ifdef CONFIG_SPL_BUILD 200 #define CONFIG_SPL_COMMON_INIT_DDR 201 #endif 202 #endif 203 204 #ifdef CONFIG_NAND 205 #ifdef CONFIG_TPL_BUILD 206 #define CONFIG_SPL_NAND_BOOT 207 #define CONFIG_SPL_FLUSH_IMAGE 208 #define CONFIG_SPL_NAND_INIT 209 #define CONFIG_SPL_COMMON_INIT_DDR 210 #define CONFIG_SPL_MAX_SIZE (128 << 10) 211 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 212 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 213 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 214 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 215 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 216 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 217 #elif defined(CONFIG_SPL_BUILD) 218 #define CONFIG_SPL_INIT_MINIMAL 219 #define CONFIG_SPL_FLUSH_IMAGE 220 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 221 #define CONFIG_SPL_TEXT_BASE 0xff800000 222 #define CONFIG_SPL_MAX_SIZE 4096 223 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 224 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 225 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 226 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 227 #endif /* not CONFIG_TPL_BUILD */ 228 229 #define CONFIG_SPL_PAD_TO 0x20000 230 #define CONFIG_TPL_PAD_TO 0x20000 231 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 232 #define CONFIG_SYS_TEXT_BASE 0x11001000 233 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 234 #endif 235 236 #ifndef CONFIG_SYS_TEXT_BASE 237 #define CONFIG_SYS_TEXT_BASE 0xeff40000 238 #endif 239 240 #ifndef CONFIG_RESET_VECTOR_ADDRESS 241 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 242 #endif 243 244 #ifndef CONFIG_SYS_MONITOR_BASE 245 #ifdef CONFIG_SPL_BUILD 246 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 247 #else 248 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 249 #endif 250 #endif 251 252 #define CONFIG_MP 253 254 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 255 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 256 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 257 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 258 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 259 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 260 261 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 262 #define CONFIG_ENV_OVERWRITE 263 264 #define CONFIG_SATA_SIL 265 #define CONFIG_SYS_SATA_MAX_DEVICE 2 266 #define CONFIG_LIBATA 267 #define CONFIG_LBA48 268 269 #if defined(CONFIG_TARGET_P2020RDB) 270 #define CONFIG_SYS_CLK_FREQ 100000000 271 #else 272 #define CONFIG_SYS_CLK_FREQ 66666666 273 #endif 274 #define CONFIG_DDR_CLK_FREQ 66666666 275 276 #define CONFIG_HWCONFIG 277 /* 278 * These can be toggled for performance analysis, otherwise use default. 279 */ 280 #define CONFIG_L2_CACHE 281 #define CONFIG_BTB 282 283 #define CONFIG_ENABLE_36BIT_PHYS 284 285 #ifdef CONFIG_PHYS_64BIT 286 #define CONFIG_ADDR_MAP 1 287 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 288 #endif 289 290 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 291 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 292 293 #define CONFIG_SYS_CCSRBAR 0xffe00000 294 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 295 296 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 297 SPL code*/ 298 #ifdef CONFIG_SPL_BUILD 299 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 300 #endif 301 302 /* DDR Setup */ 303 #define CONFIG_SYS_DDR_RAW_TIMING 304 #define CONFIG_DDR_SPD 305 #define CONFIG_SYS_SPD_BUS_NUM 1 306 #define SPD_EEPROM_ADDRESS 0x52 307 #undef CONFIG_FSL_DDR_INTERACTIVE 308 309 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 310 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 311 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 312 #else 313 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 314 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 315 #endif 316 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 317 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 318 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 319 320 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 321 322 /* Default settings for DDR3 */ 323 #ifndef CONFIG_TARGET_P2020RDB 324 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 325 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 326 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 327 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 328 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 329 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 330 331 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 332 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 333 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 334 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 335 336 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 337 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 338 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 339 #define CONFIG_SYS_DDR_RCW_1 0x00000000 340 #define CONFIG_SYS_DDR_RCW_2 0x00000000 341 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 342 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 343 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 344 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 345 346 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 347 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 348 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 349 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 350 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 351 #define CONFIG_SYS_DDR_MODE_1 0x40461520 352 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 353 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 354 #endif 355 356 #undef CONFIG_CLOCKS_IN_MHZ 357 358 /* 359 * Memory map 360 * 361 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 362 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 363 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 364 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 365 * (early boot only) 366 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 367 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 368 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 369 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 370 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 371 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 372 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 373 */ 374 375 /* 376 * Local Bus Definitions 377 */ 378 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 379 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 380 #define CONFIG_SYS_FLASH_BASE 0xec000000 381 #elif defined(CONFIG_TARGET_P1020UTM) 382 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 383 #define CONFIG_SYS_FLASH_BASE 0xee000000 384 #else 385 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 386 #define CONFIG_SYS_FLASH_BASE 0xef000000 387 #endif 388 389 #ifdef CONFIG_PHYS_64BIT 390 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 391 #else 392 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 393 #endif 394 395 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 396 | BR_PS_16 | BR_V) 397 398 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 399 400 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 401 #define CONFIG_SYS_FLASH_QUIET_TEST 402 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 403 404 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 405 406 #undef CONFIG_SYS_FLASH_CHECKSUM 407 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 408 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 409 410 #define CONFIG_FLASH_CFI_DRIVER 411 #define CONFIG_SYS_FLASH_CFI 412 #define CONFIG_SYS_FLASH_EMPTY_INFO 413 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 414 415 /* Nand Flash */ 416 #ifdef CONFIG_NAND_FSL_ELBC 417 #define CONFIG_SYS_NAND_BASE 0xff800000 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 420 #else 421 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 422 #endif 423 424 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 425 #define CONFIG_SYS_MAX_NAND_DEVICE 1 426 #if defined(CONFIG_TARGET_P1020RDB_PD) 427 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 428 #else 429 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 430 #endif 431 432 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 433 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 434 | BR_PS_8 /* Port Size = 8 bit */ \ 435 | BR_MS_FCM /* MSEL = FCM */ \ 436 | BR_V) /* valid */ 437 #if defined(CONFIG_TARGET_P1020RDB_PD) 438 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 439 | OR_FCM_PGS /* Large Page*/ \ 440 | OR_FCM_CSCT \ 441 | OR_FCM_CST \ 442 | OR_FCM_CHT \ 443 | OR_FCM_SCY_1 \ 444 | OR_FCM_TRLX \ 445 | OR_FCM_EHTR) 446 #else 447 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 448 | OR_FCM_CSCT \ 449 | OR_FCM_CST \ 450 | OR_FCM_CHT \ 451 | OR_FCM_SCY_1 \ 452 | OR_FCM_TRLX \ 453 | OR_FCM_EHTR) 454 #endif 455 #endif /* CONFIG_NAND_FSL_ELBC */ 456 457 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 458 459 #define CONFIG_SYS_INIT_RAM_LOCK 460 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 464 /* The assembler doesn't like typecast */ 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 466 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 467 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 468 #else 469 /* Initial L1 address */ 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 473 #endif 474 /* Size of used area in RAM */ 475 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 476 477 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 478 GENERATED_GBL_DATA_SIZE) 479 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 480 481 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 482 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 483 484 #define CONFIG_SYS_CPLD_BASE 0xffa00000 485 #ifdef CONFIG_PHYS_64BIT 486 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 487 #else 488 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 489 #endif 490 /* CPLD config size: 1Mb */ 491 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 492 BR_PS_8 | BR_V) 493 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 494 495 #define CONFIG_SYS_PMC_BASE 0xff980000 496 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 497 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 498 BR_PS_8 | BR_V) 499 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 500 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 501 OR_GPCM_EAD) 502 503 #ifdef CONFIG_NAND 504 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 505 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 506 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 507 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 508 #else 509 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 510 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 511 #ifdef CONFIG_NAND_FSL_ELBC 512 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 513 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 514 #endif 515 #endif 516 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 517 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 518 519 /* Vsc7385 switch */ 520 #ifdef CONFIG_VSC7385_ENET 521 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 522 523 #ifdef CONFIG_PHYS_64BIT 524 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 525 #else 526 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 527 #endif 528 529 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 530 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 531 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 532 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 533 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 534 535 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 536 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 537 538 /* The size of the VSC7385 firmware image */ 539 #define CONFIG_VSC7385_IMAGE_SIZE 8192 540 #endif 541 542 /* 543 * Config the L2 Cache as L2 SRAM 544 */ 545 #if defined(CONFIG_SPL_BUILD) 546 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 547 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 548 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 549 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 550 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 551 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 552 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 553 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 554 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 555 #if defined(CONFIG_TARGET_P2020RDB) 556 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 557 #else 558 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 559 #endif 560 #elif defined(CONFIG_NAND) 561 #ifdef CONFIG_TPL_BUILD 562 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 563 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 564 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 565 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 566 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 567 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 568 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 569 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 570 #else 571 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 572 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 573 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 574 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 575 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 576 #endif /* CONFIG_TPL_BUILD */ 577 #endif 578 #endif 579 580 /* Serial Port - controlled on board with jumper J8 581 * open - index 2 582 * shorted - index 1 583 */ 584 #define CONFIG_CONS_INDEX 1 585 #undef CONFIG_SERIAL_SOFTWARE_FIFO 586 #define CONFIG_SYS_NS16550_SERIAL 587 #define CONFIG_SYS_NS16550_REG_SIZE 1 588 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 589 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 590 #define CONFIG_NS16550_MIN_FUNCTIONS 591 #endif 592 593 #define CONFIG_SYS_BAUDRATE_TABLE \ 594 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 595 596 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 597 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 598 599 /* I2C */ 600 #define CONFIG_SYS_I2C 601 #define CONFIG_SYS_I2C_FSL 602 #define CONFIG_SYS_FSL_I2C_SPEED 400000 603 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 604 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 605 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 606 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 607 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 608 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 609 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 610 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 611 612 /* 613 * I2C2 EEPROM 614 */ 615 #undef CONFIG_ID_EEPROM 616 617 #define CONFIG_RTC_PT7C4338 618 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 619 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 620 621 /* enable read and write access to EEPROM */ 622 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 623 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 624 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 625 626 /* 627 * eSPI - Enhanced SPI 628 */ 629 #define CONFIG_HARD_SPI 630 631 #if defined(CONFIG_SPI_FLASH) 632 #define CONFIG_SF_DEFAULT_SPEED 10000000 633 #define CONFIG_SF_DEFAULT_MODE 0 634 #endif 635 636 #if defined(CONFIG_PCI) 637 /* 638 * General PCI 639 * Memory space is mapped 1-1, but I/O space must start from 0. 640 */ 641 642 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 643 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 644 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 645 #ifdef CONFIG_PHYS_64BIT 646 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 647 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 648 #else 649 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 650 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 651 #endif 652 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 653 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 654 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 655 #ifdef CONFIG_PHYS_64BIT 656 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 657 #else 658 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 659 #endif 660 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 661 662 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 663 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 664 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 665 #ifdef CONFIG_PHYS_64BIT 666 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 667 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 668 #else 669 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 670 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 671 #endif 672 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 673 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 674 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 675 #ifdef CONFIG_PHYS_64BIT 676 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 677 #else 678 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 679 #endif 680 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 681 682 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 683 #endif /* CONFIG_PCI */ 684 685 #if defined(CONFIG_TSEC_ENET) 686 #define CONFIG_MII /* MII PHY management */ 687 #define CONFIG_TSEC1 688 #define CONFIG_TSEC1_NAME "eTSEC1" 689 #define CONFIG_TSEC2 690 #define CONFIG_TSEC2_NAME "eTSEC2" 691 #define CONFIG_TSEC3 692 #define CONFIG_TSEC3_NAME "eTSEC3" 693 694 #define TSEC1_PHY_ADDR 2 695 #define TSEC2_PHY_ADDR 0 696 #define TSEC3_PHY_ADDR 1 697 698 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 699 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 700 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 701 702 #define TSEC1_PHYIDX 0 703 #define TSEC2_PHYIDX 0 704 #define TSEC3_PHYIDX 0 705 706 #define CONFIG_ETHPRIME "eTSEC1" 707 708 #define CONFIG_HAS_ETH0 709 #define CONFIG_HAS_ETH1 710 #define CONFIG_HAS_ETH2 711 #endif /* CONFIG_TSEC_ENET */ 712 713 #ifdef CONFIG_QE 714 /* QE microcode/firmware address */ 715 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 716 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 717 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 718 #endif /* CONFIG_QE */ 719 720 #ifdef CONFIG_TARGET_P1025RDB 721 /* 722 * QE UEC ethernet configuration 723 */ 724 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 725 726 #undef CONFIG_UEC_ETH 727 #define CONFIG_PHY_MODE_NEED_CHANGE 728 729 #define CONFIG_UEC_ETH1 /* ETH1 */ 730 #define CONFIG_HAS_ETH0 731 732 #ifdef CONFIG_UEC_ETH1 733 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 734 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 735 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 736 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 737 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 738 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 739 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 740 #endif /* CONFIG_UEC_ETH1 */ 741 742 #define CONFIG_UEC_ETH5 /* ETH5 */ 743 #define CONFIG_HAS_ETH1 744 745 #ifdef CONFIG_UEC_ETH5 746 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 747 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 748 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 749 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 750 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 751 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 752 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 753 #endif /* CONFIG_UEC_ETH5 */ 754 #endif /* CONFIG_TARGET_P1025RDB */ 755 756 /* 757 * Environment 758 */ 759 #ifdef CONFIG_SPIFLASH 760 #define CONFIG_ENV_SPI_BUS 0 761 #define CONFIG_ENV_SPI_CS 0 762 #define CONFIG_ENV_SPI_MAX_HZ 10000000 763 #define CONFIG_ENV_SPI_MODE 0 764 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 765 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 766 #define CONFIG_ENV_SECT_SIZE 0x10000 767 #elif defined(CONFIG_SDCARD) 768 #define CONFIG_FSL_FIXED_MMC_LOCATION 769 #define CONFIG_ENV_SIZE 0x2000 770 #define CONFIG_SYS_MMC_ENV_DEV 0 771 #elif defined(CONFIG_NAND) 772 #ifdef CONFIG_TPL_BUILD 773 #define CONFIG_ENV_SIZE 0x2000 774 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 775 #else 776 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 777 #endif 778 #define CONFIG_ENV_OFFSET (1024 * 1024) 779 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 780 #elif defined(CONFIG_SYS_RAMBOOT) 781 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 782 #define CONFIG_ENV_SIZE 0x2000 783 #else 784 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 785 #define CONFIG_ENV_SIZE 0x2000 786 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 787 #endif 788 789 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 790 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 791 792 /* 793 * USB 794 */ 795 #define CONFIG_HAS_FSL_DR_USB 796 797 #if defined(CONFIG_HAS_FSL_DR_USB) 798 #ifdef CONFIG_USB_EHCI_HCD 799 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 800 #define CONFIG_USB_EHCI_FSL 801 #endif 802 #endif 803 804 #if defined(CONFIG_TARGET_P1020RDB_PD) 805 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 806 #endif 807 808 #ifdef CONFIG_MMC 809 #define CONFIG_FSL_ESDHC 810 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 811 #endif 812 813 #undef CONFIG_WATCHDOG /* watchdog disabled */ 814 815 /* 816 * Miscellaneous configurable options 817 */ 818 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 819 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 820 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 821 822 /* 823 * For booting Linux, the board info and command line data 824 * have to be in the first 64 MB of memory, since this is 825 * the maximum mapped by the Linux kernel during initialization. 826 */ 827 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 828 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 829 830 #if defined(CONFIG_CMD_KGDB) 831 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 832 #endif 833 834 /* 835 * Environment Configuration 836 */ 837 #define CONFIG_HOSTNAME unknown 838 #define CONFIG_ROOTPATH "/opt/nfsroot" 839 #define CONFIG_BOOTFILE "uImage" 840 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 841 842 /* default location for tftp and bootm */ 843 #define CONFIG_LOADADDR 1000000 844 845 #ifdef __SW_BOOT_NOR 846 #define __NOR_RST_CMD \ 847 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 848 i2c mw 18 3 __SW_BOOT_MASK 1; reset 849 #endif 850 #ifdef __SW_BOOT_SPI 851 #define __SPI_RST_CMD \ 852 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 853 i2c mw 18 3 __SW_BOOT_MASK 1; reset 854 #endif 855 #ifdef __SW_BOOT_SD 856 #define __SD_RST_CMD \ 857 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 858 i2c mw 18 3 __SW_BOOT_MASK 1; reset 859 #endif 860 #ifdef __SW_BOOT_NAND 861 #define __NAND_RST_CMD \ 862 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 863 i2c mw 18 3 __SW_BOOT_MASK 1; reset 864 #endif 865 #ifdef __SW_BOOT_PCIE 866 #define __PCIE_RST_CMD \ 867 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 868 i2c mw 18 3 __SW_BOOT_MASK 1; reset 869 #endif 870 871 #define CONFIG_EXTRA_ENV_SETTINGS \ 872 "netdev=eth0\0" \ 873 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 874 "loadaddr=1000000\0" \ 875 "bootfile=uImage\0" \ 876 "tftpflash=tftpboot $loadaddr $uboot; " \ 877 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 878 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 879 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 880 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 881 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 882 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 883 "consoledev=ttyS0\0" \ 884 "ramdiskaddr=2000000\0" \ 885 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 886 "fdtaddr=1e00000\0" \ 887 "bdev=sda1\0" \ 888 "jffs2nor=mtdblock3\0" \ 889 "norbootaddr=ef080000\0" \ 890 "norfdtaddr=ef040000\0" \ 891 "jffs2nand=mtdblock9\0" \ 892 "nandbootaddr=100000\0" \ 893 "nandfdtaddr=80000\0" \ 894 "ramdisk_size=120000\0" \ 895 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 896 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 897 __stringify(__NOR_RST_CMD)"\0" \ 898 __stringify(__SPI_RST_CMD)"\0" \ 899 __stringify(__SD_RST_CMD)"\0" \ 900 __stringify(__NAND_RST_CMD)"\0" \ 901 __stringify(__PCIE_RST_CMD)"\0" 902 903 #define CONFIG_NFSBOOTCOMMAND \ 904 "setenv bootargs root=/dev/nfs rw " \ 905 "nfsroot=$serverip:$rootpath " \ 906 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 907 "console=$consoledev,$baudrate $othbootargs;" \ 908 "tftp $loadaddr $bootfile;" \ 909 "tftp $fdtaddr $fdtfile;" \ 910 "bootm $loadaddr - $fdtaddr" 911 912 #define CONFIG_HDBOOT \ 913 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 914 "console=$consoledev,$baudrate $othbootargs;" \ 915 "usb start;" \ 916 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 917 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 918 "bootm $loadaddr - $fdtaddr" 919 920 #define CONFIG_USB_FAT_BOOT \ 921 "setenv bootargs root=/dev/ram rw " \ 922 "console=$consoledev,$baudrate $othbootargs " \ 923 "ramdisk_size=$ramdisk_size;" \ 924 "usb start;" \ 925 "fatload usb 0:2 $loadaddr $bootfile;" \ 926 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 927 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 928 "bootm $loadaddr $ramdiskaddr $fdtaddr" 929 930 #define CONFIG_USB_EXT2_BOOT \ 931 "setenv bootargs root=/dev/ram rw " \ 932 "console=$consoledev,$baudrate $othbootargs " \ 933 "ramdisk_size=$ramdisk_size;" \ 934 "usb start;" \ 935 "ext2load usb 0:4 $loadaddr $bootfile;" \ 936 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 937 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 938 "bootm $loadaddr $ramdiskaddr $fdtaddr" 939 940 #define CONFIG_NORBOOT \ 941 "setenv bootargs root=/dev/$jffs2nor rw " \ 942 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 943 "bootm $norbootaddr - $norfdtaddr" 944 945 #define CONFIG_RAMBOOTCOMMAND \ 946 "setenv bootargs root=/dev/ram rw " \ 947 "console=$consoledev,$baudrate $othbootargs " \ 948 "ramdisk_size=$ramdisk_size;" \ 949 "tftp $ramdiskaddr $ramdiskfile;" \ 950 "tftp $loadaddr $bootfile;" \ 951 "tftp $fdtaddr $fdtfile;" \ 952 "bootm $loadaddr $ramdiskaddr $fdtaddr" 953 954 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 955 956 #endif /* __CONFIG_H */ 957