1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-pxa/include/mach/pcm990_baseboard.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de> 6*4882a593Smuzhiyun * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "pcm027.h" 10*4882a593Smuzhiyun #include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * definitions relevant only when the PCM-990 14*4882a593Smuzhiyun * development base board is in use 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ 18*4882a593Smuzhiyun #define PCM990_CTRL_INT_IRQ_GPIO 9 19*4882a593Smuzhiyun #define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO) 20*4882a593Smuzhiyun #define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING 21*4882a593Smuzhiyun #define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ 22*4882a593Smuzhiyun #define PCM990_CTRL_SIZE (1*1024*1024) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PCM990_CTRL_PWR_IRQ_GPIO 14 25*4882a593Smuzhiyun #define PCM990_CTRL_PWR_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO) 26*4882a593Smuzhiyun #define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* visible CPLD (U7) registers */ 29*4882a593Smuzhiyun #define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */ 30*4882a593Smuzhiyun #define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */ 31*4882a593Smuzhiyun #define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */ 32*4882a593Smuzhiyun #define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */ 35*4882a593Smuzhiyun #define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */ 36*4882a593Smuzhiyun #define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */ 37*4882a593Smuzhiyun #define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */ 40*4882a593Smuzhiyun #define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */ 41*4882a593Smuzhiyun #define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */ 42*4882a593Smuzhiyun #define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ 45*4882a593Smuzhiyun #define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ 46*4882a593Smuzhiyun #define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ 47*4882a593Smuzhiyun #define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ 48*4882a593Smuzhiyun #define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */ 51*4882a593Smuzhiyun #define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */ 54*4882a593Smuzhiyun #define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */ 55*4882a593Smuzhiyun #define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */ 56*4882a593Smuzhiyun #define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ 57*4882a593Smuzhiyun #define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define PCM990_CTRL_INTSETCLR 0x000C /* Interrupt Clear REGISTER */ 60*4882a593Smuzhiyun #define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */ 61*4882a593Smuzhiyun #define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */ 62*4882a593Smuzhiyun #define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */ 63*4882a593Smuzhiyun #define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define PCM990_CTRL_INTMSKENA 0x000E /* Interrupt Enable REGISTER */ 66*4882a593Smuzhiyun #define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */ 67*4882a593Smuzhiyun #define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */ 68*4882a593Smuzhiyun #define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */ 69*4882a593Smuzhiyun #define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */ 72*4882a593Smuzhiyun #define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */ 73*4882a593Smuzhiyun #define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */ 74*4882a593Smuzhiyun #define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */ 75*4882a593Smuzhiyun #define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */ 78*4882a593Smuzhiyun #define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */ 79*4882a593Smuzhiyun #define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */ 80*4882a593Smuzhiyun #define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */ 83*4882a593Smuzhiyun #define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */ 84*4882a593Smuzhiyun #define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */ 87*4882a593Smuzhiyun #define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */ 88*4882a593Smuzhiyun #define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */ 89*4882a593Smuzhiyun #define PCM990_CTRL_ACPRES 0x0004 /* DC Present */ 90*4882a593Smuzhiyun #define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* 93*4882a593Smuzhiyun * IDE 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun #define PCM990_IDE_IRQ_GPIO 13 96*4882a593Smuzhiyun #define PCM990_IDE_IRQ PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO) 97*4882a593Smuzhiyun #define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING 98*4882a593Smuzhiyun #define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ 99*4882a593Smuzhiyun #define PCM990_IDE_PLD_BASE 0xee000000 100*4882a593Smuzhiyun #define PCM990_IDE_PLD_SIZE (1*1024*1024) 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* visible CPLD (U6) registers */ 103*4882a593Smuzhiyun #define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */ 104*4882a593Smuzhiyun #define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */ 105*4882a593Smuzhiyun #define PCM990_IDE_STBY 0x0008 /* R System StandBy */ 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */ 108*4882a593Smuzhiyun #define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */ 109*4882a593Smuzhiyun #define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */ 110*4882a593Smuzhiyun #define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */ 113*4882a593Smuzhiyun #define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */ 114*4882a593Smuzhiyun #define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */ 115*4882a593Smuzhiyun #define PCM990_IDE_RDY 0x0008 /* RDY */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */ 118*4882a593Smuzhiyun #define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */ 119*4882a593Smuzhiyun #define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */ 120*4882a593Smuzhiyun #define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */ 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */ 123*4882a593Smuzhiyun #define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */ 124*4882a593Smuzhiyun #define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */ 125*4882a593Smuzhiyun #define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE) 128*4882a593Smuzhiyun #define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* 131*4882a593Smuzhiyun * Compact Flash 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun #define PCM990_CF_IRQ_GPIO 11 134*4882a593Smuzhiyun #define PCM990_CF_IRQ PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO) 135*4882a593Smuzhiyun #define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define PCM990_CF_CD_GPIO 12 138*4882a593Smuzhiyun #define PCM990_CF_CD PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO) 139*4882a593Smuzhiyun #define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* visible CPLD (U6) registers */ 144*4882a593Smuzhiyun #define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */ 145*4882a593Smuzhiyun #define PCM990_CF_REG0_LED 0x0001 /* RW LED on */ 146*4882a593Smuzhiyun #define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */ 147*4882a593Smuzhiyun #define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */ 148*4882a593Smuzhiyun #define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */ 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */ 151*4882a593Smuzhiyun #define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */ 152*4882a593Smuzhiyun #define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */ 155*4882a593Smuzhiyun #define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */ 156*4882a593Smuzhiyun #define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */ 157*4882a593Smuzhiyun #define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */ 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */ 160*4882a593Smuzhiyun #define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */ 161*4882a593Smuzhiyun #define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */ 162*4882a593Smuzhiyun #define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */ 163*4882a593Smuzhiyun #define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */ 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */ 166*4882a593Smuzhiyun #define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */ 167*4882a593Smuzhiyun #define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */ 168*4882a593Smuzhiyun #define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */ 169*4882a593Smuzhiyun #define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */ 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */ 172*4882a593Smuzhiyun #define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */ 173*4882a593Smuzhiyun #define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */ 174*4882a593Smuzhiyun #define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */ 175*4882a593Smuzhiyun #define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */ 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */ 178*4882a593Smuzhiyun #define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ 179*4882a593Smuzhiyun #define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* 182*4882a593Smuzhiyun * Wolfson AC97 Touch 183*4882a593Smuzhiyun */ 184*4882a593Smuzhiyun #define PCM990_AC97_IRQ_GPIO 10 185*4882a593Smuzhiyun #define PCM990_AC97_IRQ PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO) 186*4882a593Smuzhiyun #define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* 189*4882a593Smuzhiyun * MMC phyCORE 190*4882a593Smuzhiyun */ 191*4882a593Smuzhiyun #define PCM990_MMC0_IRQ_GPIO 9 192*4882a593Smuzhiyun #define PCM990_MMC0_IRQ PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO) 193*4882a593Smuzhiyun #define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* 196*4882a593Smuzhiyun * USB phyCore 197*4882a593Smuzhiyun */ 198*4882a593Smuzhiyun #define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN) 199*4882a593Smuzhiyun #define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT) 200