Lines Matching +full:0 +full:xee000000
21 #define CONFIG_SYS_TEXT_BASE 0x11001000
22 #define CONFIG_SPL_TEXT_BASE 0xD0001000
23 #define CONFIG_SPL_PAD_TO 0x18000
26 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
27 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
40 #define CONFIG_SYS_TEXT_BASE 0x11000000
41 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
46 #define CONFIG_SYS_TEXT_BASE 0x11001000
47 #define CONFIG_SPL_TEXT_BASE 0xD0001000
48 #define CONFIG_SPL_PAD_TO 0x18000
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
70 #define CONFIG_SYS_TEXT_BASE 0x00201000
71 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
73 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
74 #define CONFIG_SPL_RELOC_STACK 0x00100000
75 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
76 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
77 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
78 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
87 #define CONFIG_SPL_TEXT_BASE 0xD0001000
90 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
91 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
97 #define CONFIG_SPL_TEXT_BASE 0xff800000
100 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
101 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
104 #define CONFIG_SPL_PAD_TO 0x20000
105 #define CONFIG_TPL_PAD_TO 0x20000
107 #define CONFIG_SYS_TEXT_BASE 0x11001000
114 #define CONFIG_SYS_TEXT_BASE 0x11000000
115 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
119 #define CONFIG_SYS_TEXT_BASE 0xeff40000
123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
145 * Memory space is mapped 1-1, but I/O space must start from 0.
149 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
151 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
152 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
154 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
155 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
157 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
158 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
159 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
160 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
162 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
164 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
173 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
175 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
176 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
178 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
179 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
181 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
182 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
183 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
184 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
186 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
188 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
217 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
218 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
224 #define SPD_EEPROM_ADDRESS 0x52
226 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
232 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
239 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
240 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
241 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
242 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
243 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
244 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
245 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
246 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
247 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
248 #define CONFIG_SYS_DDR_RCW_1 0x00000000
249 #define CONFIG_SYS_DDR_RCW_2 0x00000000
250 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
251 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
252 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
253 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
255 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
256 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
257 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
258 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
259 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
260 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
261 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000
262 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
263 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
266 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
267 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
268 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
269 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
270 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
271 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
272 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
273 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
274 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
276 #define CONFIG_SYS_CCSRBAR 0xffe00000
287 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
288 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
289 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
292 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
293 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
294 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
295 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
303 #define CONFIG_SYS_FLASH_BASE 0xee000000
307 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
319 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
320 FTIM0_NOR_TEADC(0x5) | \
321 FTIM0_NOR_TEAHC(0x5)
322 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
323 FTIM1_NOR_TRAD_NOR(0x0f)
324 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
325 FTIM2_NOR_TCH(0x4) | \
326 FTIM2_NOR_TWP(0x1c)
327 #define CONFIG_SYS_NOR_FTIM3 0x0
345 #define CONFIG_SYS_NAND_BASE 0xff800000
347 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
390 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
391 FTIM0_NAND_TWP(0x0C) | \
392 FTIM0_NAND_TWCHT(0x04) | \
393 FTIM0_NAND_TWH(0x05)
394 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
395 FTIM1_NAND_TWBE(0x1d) | \
396 FTIM1_NAND_TRR(0x07) | \
397 FTIM1_NAND_TRP(0x0c)
398 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
399 FTIM2_NAND_TREH(0x05) | \
400 FTIM2_NAND_TWHRE(0x0f)
401 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
406 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
407 FTIM0_NAND_TWP(0x18) | \
408 FTIM0_NAND_TWCHT(0x07) | \
409 FTIM0_NAND_TWH(0x0a))
410 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
411 FTIM1_NAND_TWBE(0x39) | \
412 FTIM1_NAND_TRR(0x0e) | \
413 FTIM1_NAND_TRP(0x18))
414 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
415 FTIM2_NAND_TREH(0x0a) | \
416 FTIM2_NAND_TWHRE(0x1e))
417 #define CONFIG_SYS_NAND_FTIM3 0x0
456 #define CONFIG_SYS_CPLD_BASE 0xffb00000
459 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
469 #define CONFIG_SYS_CSOR3 0x0
471 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
472 FTIM0_GPCM_TEADC(0x0e) | \
473 FTIM0_GPCM_TEAHC(0x0e))
474 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
475 FTIM1_GPCM_TRAD(0x1f))
476 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
477 FTIM2_GPCM_TCH(0x8) | \
478 FTIM2_GPCM_TWP(0x1f))
479 #define CONFIG_SYS_CS3_FTIM3 0x0
498 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
499 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
513 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
517 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
525 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
529 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
535 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
539 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
540 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
550 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
558 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
559 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
565 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
566 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
568 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
569 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
570 #define I2C_PCA9557_ADDR1 0x18
571 #define I2C_PCA9557_ADDR2 0x19
572 #define I2C_PCA9557_BUS_NUM 0
581 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
582 #define CONFIG_SYS_EEPROM_BUS_NUM 0
592 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
615 #define TSEC2_PHY_ADDR 0
622 #define TSEC1_PHYIDX 0
623 #define TSEC2_PHYIDX 0
624 #define TSEC3_PHYIDX 0
674 #define CONFIG_SYS_MMC_ENV_DEV 0
675 #define CONFIG_ENV_SIZE 0x2000
677 #define CONFIG_ENV_SPI_BUS 0
678 #define CONFIG_ENV_SPI_CS 0
680 #define CONFIG_ENV_SPI_MODE 0
681 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
682 #define CONFIG_ENV_SECT_SIZE 0x10000
683 #define CONFIG_ENV_SIZE 0x2000
686 #define CONFIG_ENV_SIZE 0x2000
699 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
700 #define CONFIG_ENV_SIZE 0x2000
703 #define CONFIG_ENV_SIZE 0x2000
704 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
722 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
754 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
755 "netdev=eth0\0" \
756 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
757 "loadaddr=1000000\0" \
758 "consoledev=ttyS0\0" \
759 "ramdiskaddr=2000000\0" \
760 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
761 "fdtaddr=1e00000\0" \
762 "fdtfile=p1010rdb.dtb\0" \
763 "bdev=sda1\0" \
764 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
765 "othbootargs=ramdisk_size=600000\0" \
769 "fatload usb 0:2 $loadaddr $bootfile;" \
770 "fatload usb 0:2 $fdtaddr $fdtfile;" \
771 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
772 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
776 "ext2load usb 0:4 $loadaddr $bootfile;" \
777 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
778 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
779 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
784 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
785 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
786 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
787 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
788 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
789 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
793 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
794 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
795 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
796 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
797 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
798 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
799 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
800 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
801 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
802 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"