1*4882a593SmuzhiyunIntegrated Flash Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunProperties: 4*4882a593Smuzhiyun- name : Should be ifc 5*4882a593Smuzhiyun- compatible : should contain "fsl,ifc". The version of the integrated 6*4882a593Smuzhiyun flash controller can be found in the IFC_REV register at 7*4882a593Smuzhiyun offset zero. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- #address-cells : Should be either two or three. The first cell is the 10*4882a593Smuzhiyun chipselect number, and the remaining cells are the 11*4882a593Smuzhiyun offset into the chipselect. 12*4882a593Smuzhiyun- #size-cells : Either one or two, depending on how large each chipselect 13*4882a593Smuzhiyun can be. 14*4882a593Smuzhiyun- reg : Offset and length of the register set for the device 15*4882a593Smuzhiyun- interrupts: IFC may have one or two interrupts. If two interrupt 16*4882a593Smuzhiyun specifiers are present, the first is the "common" 17*4882a593Smuzhiyun interrupt (CM_EVTER_STAT), and the second is the NAND 18*4882a593Smuzhiyun interrupt (NAND_EVTER_STAT). If there is only one, 19*4882a593Smuzhiyun that interrupt reports both types of event. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- little-endian : If this property is absent, the big-endian mode will 22*4882a593Smuzhiyun be in use as default for registers. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- ranges : Each range corresponds to a single chipselect, and covers 25*4882a593Smuzhiyun the entire access window as configured. 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunChild device nodes describe the devices connected to IFC such as NOR (e.g. 28*4882a593Smuzhiyuncfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices 29*4882a593Smuzhiyunlike FPGAs, CPLDs, etc. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunExample: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun ifc@ffe1e000 { 34*4882a593Smuzhiyun compatible = "fsl,ifc", "simple-bus"; 35*4882a593Smuzhiyun #address-cells = <2>; 36*4882a593Smuzhiyun #size-cells = <1>; 37*4882a593Smuzhiyun reg = <0x0 0xffe1e000 0 0x2000>; 38*4882a593Smuzhiyun interrupts = <16 2 19 2>; 39*4882a593Smuzhiyun little-endian; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* NOR, NAND Flashes and CPLD on board */ 42*4882a593Smuzhiyun ranges = <0x0 0x0 0x0 0xee000000 0x02000000 43*4882a593Smuzhiyun 0x1 0x0 0x0 0xffa00000 0x00010000 44*4882a593Smuzhiyun 0x3 0x0 0x0 0xffb00000 0x00020000>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun flash@0,0 { 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <1>; 49*4882a593Smuzhiyun compatible = "cfi-flash"; 50*4882a593Smuzhiyun reg = <0x0 0x0 0x2000000>; 51*4882a593Smuzhiyun bank-width = <2>; 52*4882a593Smuzhiyun device-width = <1>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun partition@0 { 55*4882a593Smuzhiyun /* 32MB for user data */ 56*4882a593Smuzhiyun reg = <0x0 0x02000000>; 57*4882a593Smuzhiyun label = "NOR Data"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun flash@1,0 { 62*4882a593Smuzhiyun #address-cells = <1>; 63*4882a593Smuzhiyun #size-cells = <1>; 64*4882a593Smuzhiyun compatible = "fsl,ifc-nand"; 65*4882a593Smuzhiyun reg = <0x1 0x0 0x10000>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun partition@0 { 68*4882a593Smuzhiyun /* This location must not be altered */ 69*4882a593Smuzhiyun /* 1MB for u-boot Bootloader Image */ 70*4882a593Smuzhiyun reg = <0x0 0x00100000>; 71*4882a593Smuzhiyun label = "NAND U-Boot Image"; 72*4882a593Smuzhiyun read-only; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun cpld@3,0 { 77*4882a593Smuzhiyun #address-cells = <1>; 78*4882a593Smuzhiyun #size-cells = <1>; 79*4882a593Smuzhiyun compatible = "fsl,p1010rdb-cpld"; 80*4882a593Smuzhiyun reg = <0x3 0x0 0x000001f>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83