Lines Matching +full:0 +full:xee000000
17 #define __SW_BOOT_MASK 0x03
18 #define __SW_BOOT_NOR 0xe4
19 #define __SW_BOOT_SD 0x54
25 #define __SW_BOOT_MASK 0x03
26 #define __SW_BOOT_NOR 0xe0
27 #define __SW_BOOT_SD 0x50
36 #define __SW_BOOT_MASK 0x03
37 #define __SW_BOOT_NOR 0x5c
38 #define __SW_BOOT_SPI 0x1c
39 #define __SW_BOOT_SD 0x9c
40 #define __SW_BOOT_NAND 0xec
41 #define __SW_BOOT_PCIE 0x6c
63 #define __SW_BOOT_MASK 0x03
64 #define __SW_BOOT_NOR 0x64
65 #define __SW_BOOT_SPI 0x34
66 #define __SW_BOOT_SD 0x24
67 #define __SW_BOOT_NAND 0x44
68 #define __SW_BOOT_PCIE 0x74
84 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
86 #define __SW_BOOT_MASK 0x03
87 #define __SW_BOOT_NOR 0x5c
88 #define __SW_BOOT_SPI 0x1c
89 #define __SW_BOOT_SD 0x9c
90 #define __SW_BOOT_NAND 0xec
91 #define __SW_BOOT_PCIE 0x6c
114 #define __SW_BOOT_MASK 0xf3
115 #define __SW_BOOT_NOR 0x00
116 #define __SW_BOOT_SPI 0x08
117 #define __SW_BOOT_SD 0x04
118 #define __SW_BOOT_NAND 0x0c
128 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
130 #define __SW_BOOT_MASK 0xf3
131 #define __SW_BOOT_NOR 0x00
132 #define __SW_BOOT_SPI 0x08
133 #define __SW_BOOT_SD 0x04
134 #define __SW_BOOT_NAND 0x0c
142 #define __SW_BOOT_MASK 0x03
143 #define __SW_BOOT_NOR 0xc8
144 #define __SW_BOOT_SPI 0x28
145 #define __SW_BOOT_SD 0x68 /* or 0x18 */
146 #define __SW_BOOT_NAND 0xe8
147 #define __SW_BOOT_PCIE 0xa8
168 #define CONFIG_SYS_TEXT_BASE 0x11001000
169 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
170 #define CONFIG_SPL_PAD_TO 0x20000
173 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
174 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
188 #define CONFIG_SYS_TEXT_BASE 0x11001000
189 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
190 #define CONFIG_SPL_PAD_TO 0x20000
193 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
194 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
211 #define CONFIG_SPL_TEXT_BASE 0xf8f81000
214 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
215 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
221 #define CONFIG_SPL_TEXT_BASE 0xff800000
224 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
225 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
229 #define CONFIG_SPL_PAD_TO 0x20000
230 #define CONFIG_TPL_PAD_TO 0x20000
232 #define CONFIG_SYS_TEXT_BASE 0x11001000
237 #define CONFIG_SYS_TEXT_BASE 0xeff40000
241 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
290 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
291 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
293 #define CONFIG_SYS_CCSRBAR 0xffe00000
306 #define SPD_EEPROM_ADDRESS 0x52
317 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
324 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
325 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
326 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
327 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
328 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
329 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
331 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
332 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
333 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
334 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
336 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
337 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
338 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
339 #define CONFIG_SYS_DDR_RCW_1 0x00000000
340 #define CONFIG_SYS_DDR_RCW_2 0x00000000
341 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
342 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
343 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
344 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
346 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
347 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
348 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
349 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
350 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
351 #define CONFIG_SYS_DDR_MODE_1 0x40461520
352 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
353 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
361 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
362 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
363 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
364 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
366 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
367 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
368 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
369 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
370 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
371 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
372 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
380 #define CONFIG_SYS_FLASH_BASE 0xec000000
383 #define CONFIG_SYS_FLASH_BASE 0xee000000
386 #define CONFIG_SYS_FLASH_BASE 0xef000000
390 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
398 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
417 #define CONFIG_SYS_NAND_BASE 0xff800000
419 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
460 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
475 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
484 #define CONFIG_SYS_CPLD_BASE 0xffa00000
486 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
493 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
495 #define CONFIG_SYS_PMC_BASE 0xff980000
521 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
524 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
547 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
550 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
562 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
565 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
571 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
574 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
575 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
588 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
596 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
597 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
603 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
604 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
606 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
607 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
608 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
609 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
618 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
619 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
633 #define CONFIG_SF_DEFAULT_MODE 0
639 * Memory space is mapped 1-1, but I/O space must start from 0.
644 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
646 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
647 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
649 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
650 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
652 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
653 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
654 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
656 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
658 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
660 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
664 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
666 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
667 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
669 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
670 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
672 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
673 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
674 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
676 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
678 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
680 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
695 #define TSEC2_PHY_ADDR 0
702 #define TSEC1_PHYIDX 0
703 #define TSEC2_PHYIDX 0
704 #define TSEC3_PHYIDX 0
716 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000
717 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
724 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
733 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
737 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
750 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
760 #define CONFIG_ENV_SPI_BUS 0
761 #define CONFIG_ENV_SPI_CS 0
763 #define CONFIG_ENV_SPI_MODE 0
764 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
765 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
766 #define CONFIG_ENV_SECT_SIZE 0x10000
769 #define CONFIG_ENV_SIZE 0x2000
770 #define CONFIG_SYS_MMC_ENV_DEV 0
773 #define CONFIG_ENV_SIZE 0x2000
781 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
782 #define CONFIG_ENV_SIZE 0x2000
785 #define CONFIG_ENV_SIZE 0x2000
786 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
820 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
872 "netdev=eth0\0" \
873 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
874 "loadaddr=1000000\0" \
875 "bootfile=uImage\0" \
881 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
882 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
883 "consoledev=ttyS0\0" \
884 "ramdiskaddr=2000000\0" \
885 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
886 "fdtaddr=1e00000\0" \
887 "bdev=sda1\0" \
888 "jffs2nor=mtdblock3\0" \
889 "norbootaddr=ef080000\0" \
890 "norfdtaddr=ef040000\0" \
891 "jffs2nand=mtdblock9\0" \
892 "nandbootaddr=100000\0" \
893 "nandfdtaddr=80000\0" \
894 "ramdisk_size=120000\0" \
895 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
896 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
897 __stringify(__NOR_RST_CMD)"\0" \
898 __stringify(__SPI_RST_CMD)"\0" \
899 __stringify(__SD_RST_CMD)"\0" \
900 __stringify(__NAND_RST_CMD)"\0" \
901 __stringify(__PCIE_RST_CMD)"\0"
916 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
917 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
925 "fatload usb 0:2 $loadaddr $bootfile;" \
926 "fatload usb 0:2 $fdtaddr $fdtfile;" \
927 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
935 "ext2load usb 0:4 $loadaddr $bootfile;" \
936 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
937 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \