Home
last modified time | relevance | path

Searched +full:0 +full:xe6060000 (Results 1 – 25 of 46) sorted by relevance

12

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,pfc.yaml129 $ref: "#/additionalProperties/anyOf/0"
135 reg = <0xe6050000 0x8000>,
136 <0xe605800c 0x20>;
139 gpio-ranges = <&pfc 0 0 212>;
141 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
142 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
143 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
144 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
145 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
146 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/blanche/
H A Dblanche.c38 #define PMMR 0xE6060000
39 #define GPSR0 0xE6060004
40 #define GPSR1 0xE6060008
41 #define GPSR4 0xE6060014
42 #define GPSR5 0xE6060018
43 #define GPSR6 0xE606001C
44 #define GPSR7 0xE6060020
45 #define GPSR8 0xE6060024
46 #define GPSR9 0xE6060028
47 #define GPSR10 0xE606002C
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dr8a7792.dtsi40 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0>;
70 L2_CA15: cache-controller-0 {
81 #clock-cells = <0>;
83 clock-frequency = <0>;
96 #clock-cells = <0>;
98 clock-frequency = <0>;
[all …]
H A Dr8a77470.dtsi27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0>;
50 L2_CA7: cache-controller-0 {
61 #clock-cells = <0>;
63 clock-frequency = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
92 reg = <0 0xe6020000 0 0x0c>;
102 reg = <0 0xe6050000 0 0x50>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7745.dtsi36 * The external audio clocks are configured as 0 Hz fixed
42 #clock-cells = <0>;
43 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #size-cells = <0>;
[all …]
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dr8a7796.dtsi38 #size-cells = <0>;
40 a57_0: cpu@0 {
42 reg = <0x0>;
51 reg = <0x1>;
60 reg = <0x100>;
69 reg = <0x101>;
78 reg = <0x102>;
87 reg = <0x103>;
94 L2_CA57: cache-controller-0 {
111 #clock-cells = <0>;
[all …]
H A Dr8a7795.dtsi38 #size-cells = <0>;
40 a57_0: cpu@0 {
42 reg = <0x0>;
51 reg = <0x1>;
60 reg = <0x2>;
69 reg = <0x3>;
78 reg = <0x100>;
87 reg = <0x101>;
96 reg = <0x102>;
105 reg = <0x103>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rmobile/
H A Dpfc-r8a7791.c15 PINMUX_RESERVED = 0,
439 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
473 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
474 0, 0,
475 0, 0,
476 0, 0,
477 0, 0,
478 0, 0,
479 0, 0,
507 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
[all …]
H A Dpfc-r8a7794.c64 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
79 PINMUX_RESERVED = 0,
866 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
900 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
901 0, 0,
902 0, 0,
903 0, 0,
904 0, 0,
905 0, 0,
906 0, 0,
[all …]
H A Dpfc-r8a7790.c21 PINMUX_RESERVED = 0,
1125 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1159 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1160 0, 0,
1161 0, 0,
1193 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
1194 0, 0,
1195 0, 0,
1227 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1261 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
[all …]
H A Dpfc-r8a7792.c16 PINMUX_RESERVED = 0,
880 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
881 0, 0,
882 0, 0,
883 0, 0,
914 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
915 0, 0,
916 0, 0,
917 0, 0,
918 0, 0,
[all …]
H A Dpfc-r8a7793.c56 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
71 PINMUX_RESERVED = 0,
157 /* IPSR 0 -5 */
1039 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1073 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1074 0, 0,
1075 0, 0,
1076 0, 0,
1077 0, 0,
1078 0, 0,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/renesas/
H A Dr8a77995.dtsi21 #clock-cells = <0>;
22 clock-frequency = <0>;
27 #size-cells = <0>;
29 a53_0: cpu@0 {
31 reg = <0x0>;
48 #clock-cells = <0>;
50 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
79 reg = <0 0xe6020000 0 0x0c>;
[all …]
H A Dr8a77970.dtsi30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #size-cells = <0>;
38 a53_0: cpu@0 {
41 reg = <0>;
68 #clock-cells = <0>;
70 clock-frequency = <0>;
75 #clock-cells = <0>;
77 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
H A Dr8a77980.dtsi31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #size-cells = <0>;
39 a53_0: cpu@0 {
42 reg = <0>;
89 #clock-cells = <0>;
91 clock-frequency = <0>;
96 #clock-cells = <0>;
98 clock-frequency = <0>;
104 #clock-cells = <0>;
[all …]
H A Dr8a774c0.dtsi18 * The external audio clocks are configured as 0 Hz fixed frequency
24 #clock-cells = <0>;
25 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
36 #clock-cells = <0>;
37 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a77990.dtsi29 * The external audio clocks are configured as 0 Hz fixed frequency
35 #clock-cells = <0>;
36 clock-frequency = <0>;
41 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
81 #size-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/renesas/
H A Dpfc-r8a7791.c15 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
19 PORT_GP_32(0, fn, sfx), \
37 PINMUX_RESERVED = 0,
1713 /* ADICHS 0 */
1717 /* ADICHS 0 */
1745 /* ADICHS B 0 */
1749 /* ADICHS B 0 */
1844 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1867 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2038 /* R[7:0], G[7:0], B[7:0] */
[all …]

12