Lines Matching +full:0 +full:xe6060000
56 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
71 PINMUX_RESERVED = 0,
157 /* IPSR 0 -5 */
1039 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1073 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1074 0, 0,
1075 0, 0,
1076 0, 0,
1077 0, 0,
1078 0, 0,
1079 0, 0,
1107 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
1141 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1175 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
1209 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
1243 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
1244 0, 0,
1245 0, 0,
1267 0, 0,
1277 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
1278 0, 0,
1279 0, 0,
1280 0, 0,
1281 0, 0,
1282 0, 0,
1283 0, 0,
1314 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
1317 0, 0, 0, 0,
1321 0, 0, 0,
1325 0, 0, 0,
1329 0, 0, 0,
1334 0, 0, 0,
1338 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
1340 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
1342 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
1348 0, 0,
1351 FN_SCIF_CLK, 0, FN_BPFCLK_E,
1352 0, 0, }
1357 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
1361 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
1363 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
1383 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
1385 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
1389 0, 0, 0,
1393 0, 0, 0,
1396 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
1399 0, 0, 0,
1402 0, 0, 0, }
1404 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
1407 0, 0, 0, 0,
1411 0, 0, 0,
1415 0, 0, 0,
1417 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
1419 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
1421 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
1427 0, 0, 0,
1431 0, 0, 0,
1435 0, 0, 0,
1439 0, 0, 0,
1445 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
1449 0, 0,
1452 0, 0, 0, 0,
1460 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
1466 0, 0,
1470 0, 0,
1486 0, 0, 0,
1494 0, 0, 0, }
1496 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
1500 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
1503 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
1505 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
1506 0, 0, 0,
1508 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
1509 0, 0, 0,
1511 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
1513 0, 0,
1515 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
1517 0, 0,
1520 0, 0, 0,
1523 0, 0, 0,
1537 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
1539 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
1542 0, 0, 0, 0,
1544 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
1546 0, 0,
1548 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
1550 0, 0,
1552 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
1553 FN_TCLK2, FN_VI1_DATA3_C, 0,
1555 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
1556 0, 0, 0,
1558 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
1560 0, 0,
1564 0, 0,
1568 0, 0,
1572 0, 0, 0,
1574 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
1576 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
1578 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
1580 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
1583 0, 0, 0, 0, 0, 0, 0, 0,
1584 0, 0, 0, 0, 0, 0, 0, 0,
1586 0, 0, 0, 0, 0, 0, 0, 0,
1587 0, 0, 0, 0, 0, 0, 0, 0,
1589 0, 0, 0, 0, 0, 0, 0, 0,
1590 0, 0, 0, 0, 0, 0, 0, 0,
1592 0, 0, 0, 0, 0, 0, 0, 0,
1593 0, 0, 0, 0, 0, 0, 0, 0,
1595 0, 0, 0, 0, 0, 0, 0, 0,
1596 0, 0, 0, 0, 0, 0, 0, 0,
1606 0, 0, 0,
1610 0, 0, 0, }
1612 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
1616 0, 0,
1627 0, 0, 0, 0,
1629 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
1641 0, 0, 0,
1643 0, 0, 0, 0,
1645 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
1647 0, 0, 0, 0,
1655 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
1657 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
1663 0, 0, 0,
1665 0, 0,
1671 0, 0,
1675 0, 0,
1679 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
1681 0, 0, 0, 0,
1687 0, 0, 0,
1689 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
1691 0, 0,
1695 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
1697 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
1701 0, 0,
1705 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
1715 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
1717 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
1719 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
1725 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
1731 0, 0, 0, 0,
1737 0, 0, 0,
1739 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
1741 0, 0, 0, 0,
1743 0, 0, 0, 0,
1745 0, 0, }
1747 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
1753 0, 0, 0,
1755 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
1757 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
1759 0, 0,
1769 0, 0, 0,
1771 0, 0, 0, 0,
1773 0, 0, 0, 0,
1777 0, 0, 0,
1779 0, 0,
1785 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
1787 0, 0, 0, 0,
1789 0, 0, 0, 0,
1791 0, 0, 0, 0, }
1793 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
1794 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
1795 0, 0,
1796 0, 0,
1797 0, 0,
1798 0, 0,
1799 0, 0,
1800 0, 0,
1828 { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
1829 { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
1830 { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
1831 { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
1832 { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
1833 { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
1834 0, 0,
1835 0, 0,
1836 0, 0,
1837 0, 0,
1838 0, 0,
1839 0, 0,
1871 { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
1872 { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
1873 0, 0, 0, 0,
1874 0, 0, GP_1_25_DATA, GP_1_24_DATA,
1882 { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
1883 { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
1884 { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
1885 { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
1886 { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
1887 { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
1888 0, 0, 0, 0,
1889 0, 0, GP_7_25_DATA, GP_7_24_DATA,
1903 .unlock_reg = 0xe6060000, /* PMMR */