Lines Matching +full:0 +full:xe6060000
15 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
19 PORT_GP_32(0, fn, sfx), \
37 PINMUX_RESERVED = 0,
1713 /* ADICHS 0 */
1717 /* ADICHS 0 */
1745 /* ADICHS B 0 */
1749 /* ADICHS B 0 */
1844 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1867 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2038 /* R[7:0], G[7:0], B[7:0] */
2041 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2150 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2177 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2198 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2326 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2348 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2362 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2456 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2565 /* D[0] */
2572 /* D[0:3] */
2580 /* D[0:7] */
2591 /* D[0:7] */
2654 RCAR_GP_PIN(0, 16),
2661 RCAR_GP_PIN(0, 17),
2668 RCAR_GP_PIN(0, 18),
2675 RCAR_GP_PIN(0, 19),
2682 RCAR_GP_PIN(0, 21),
2689 RCAR_GP_PIN(0, 20),
2740 RCAR_GP_PIN(0, 22),
2747 RCAR_GP_PIN(0, 23),
2754 RCAR_GP_PIN(0, 24),
2761 RCAR_GP_PIN(0, 25),
2768 RCAR_GP_PIN(0, 27),
2775 RCAR_GP_PIN(0, 26),
2855 RCAR_GP_PIN(0, 28),
2862 RCAR_GP_PIN(0, 30),
2869 RCAR_GP_PIN(0, 29),
2876 RCAR_GP_PIN(0, 27),
2883 RCAR_GP_PIN(0, 26),
2963 RCAR_GP_PIN(3, 0),
3136 RCAR_GP_PIN(0, 16),
3203 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3233 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3384 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3421 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3450 RCAR_GP_PIN(1, 0),
3537 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3588 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3616 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3744 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3789 /* D[0:3] */
3798 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3826 /* D[0:3] */
3863 /* D[0:3] */
3913 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4277 RCAR_GP_PIN(4, 0),
4296 RCAR_GP_PIN(5, 0), /* HSYNC */
4324 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
5431 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
5465 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
5466 0, 0,
5467 0, 0,
5468 0, 0,
5469 0, 0,
5470 0, 0,
5471 0, 0,
5499 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
5533 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5567 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5601 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5635 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
5669 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
5670 0, 0,
5671 0, 0,
5672 0, 0,
5673 0, 0,
5674 0, 0,
5675 0, 0,
5703 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5708 0, 0,
5711 0, 0,
5714 0, 0,
5717 0, 0,
5720 0, 0,
5723 0, 0,
5726 0, 0,
5729 0, 0, 0,
5731 FN_D15, 0,
5733 FN_D14, 0,
5735 FN_D13, 0,
5737 FN_D12, 0,
5739 FN_D11, 0,
5741 FN_D10, 0,
5743 FN_D9, 0,
5745 FN_D8, 0,
5747 FN_D7, 0,
5749 FN_D6, 0,
5751 FN_D5, 0,
5753 FN_D4, 0,
5755 FN_D3, 0,
5757 FN_D2, 0,
5759 FN_D1, 0,
5761 FN_D0, 0, ))
5763 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5767 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5768 0, 0, 0,
5770 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5771 0, 0, 0, 0,
5773 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5774 0, 0, 0,
5777 0, 0, 0, 0, 0, 0,
5780 0, 0, 0,
5783 0, 0, 0, 0,
5786 0, 0, 0, 0,
5789 0, 0, 0, 0,
5791 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5793 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5795 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5798 0, 0, ))
5800 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5804 0, 0, 0, 0,
5807 FN_ATAG0_N, 0, FN_EX_WAIT1,
5808 0, 0,
5810 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5812 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5814 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5816 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5819 0, 0,
5822 0, 0, 0,
5825 0, 0, 0,
5828 0, 0, 0,
5830 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5832 FN_A20, FN_SPCLK, 0, 0,
5834 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5835 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
5837 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5841 0, 0,
5845 0, 0, 0,
5849 0, 0, 0,
5851 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5854 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5856 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5858 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5862 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5865 0, 0, 0,
5868 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5871 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5873 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5874 0, 0, 0, ))
5876 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5881 0, 0,
5885 0, 0,
5887 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5889 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5891 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5893 FN_SSI_SDATA3, 0,
5895 FN_SSI_WS34, 0,
5897 FN_SSI_SCK34, 0,
5900 0, 0, 0, 0,
5904 0, 0,
5907 0, 0, 0,
5912 FN_GLO_I1_D, 0, 0, 0,
5916 0, 0, 0,
5921 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5926 0, 0, 0, 0, 0,
5929 0, 0, 0, 0,
5931 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5933 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5935 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5938 0, 0, 0, 0,
5940 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5943 0, 0, 0, 0,
5946 0, 0, 0, 0,
5950 0, 0,
5954 0, 0,
5958 0, 0, ))
5960 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5964 0, 0, 0, 0,
5968 0, 0, 0,
5972 0, 0, 0,
5976 0, 0, 0,
5981 FN_INTC_IRQ4_N, 0, 0, 0,
5985 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5987 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5989 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5995 0, 0,
5999 0, 0, ))
6001 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
6005 0, 0, 0, 0,
6009 0, 0,
6013 0, 0,
6017 0, 0,
6019 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
6021 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
6023 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
6025 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
6027 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
6029 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
6033 0, 0,
6037 0, 0,
6041 0, 0, ))
6043 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6047 0, 0,
6050 0, 0, 0,
6054 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
6058 0, 0,
6062 0, 0,
6066 0, 0,
6070 0, 0, 0,
6074 0, 0, 0,
6078 0, 0,
6082 0, 0,
6084 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6085 0, 0, 0, ))
6087 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6093 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6095 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6105 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6111 0, 0, 0,
6119 0, 0,
6127 0, 0, 0,
6130 0, 0, 0, ))
6132 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6137 0, 0, 0,
6144 0, 0, 0,
6148 0, 0, 0,
6150 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6152 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6155 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6159 0, 0,
6162 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6165 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6168 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
6170 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6175 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6177 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6197 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6199 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6203 0, 0, 0,
6207 0, 0, 0,
6210 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6213 0, 0, 0,
6216 FN_I2C1_SDA_D, 0, 0, 0, ))
6218 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6222 0, 0, 0, 0,
6226 0, 0, 0,
6230 0, 0, 0,
6232 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6234 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6236 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6242 0, 0, 0,
6246 0, 0, 0,
6250 0, 0, 0,
6254 0, 0, 0,
6260 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6265 0, 0,
6268 0, 0, 0, 0,
6276 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6282 0, 0,
6286 0, 0,
6302 0, 0, 0,
6310 0, 0, 0, ))
6312 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6318 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6321 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6323 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6324 0, 0, 0,
6326 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6327 0, 0, 0,
6329 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6331 0, 0,
6333 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6335 0, 0,
6338 0, 0, 0,
6341 0, 0, 0,
6355 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
6357 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6361 0, 0, 0, 0,
6363 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6365 0, 0,
6367 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6369 0, 0,
6371 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6372 FN_TCLK2, FN_VI1_DATA3_C, 0,
6374 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6375 0, 0, 0,
6377 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6379 0, 0,
6383 0, 0,
6387 0, 0,
6391 0, 0, 0,
6393 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6395 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6397 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
6399 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6403 0, 0, 0, 0, 0, 0, 0, 0,
6404 0, 0, 0, 0, 0, 0, 0, 0,
6406 0, 0, 0, 0, 0, 0, 0, 0,
6407 0, 0, 0, 0, 0, 0, 0, 0,
6409 0, 0, 0, 0, 0, 0, 0, 0,
6410 0, 0, 0, 0, 0, 0, 0, 0,
6412 0, 0, 0, 0, 0, 0, 0, 0,
6413 0, 0, 0, 0, 0, 0, 0, 0,
6415 0, 0, 0, 0, 0, 0, 0, 0,
6416 0, 0, 0, 0, 0, 0, 0, 0,
6426 0, 0, 0,
6430 0, 0, 0, ))
6432 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6437 0, 0,
6448 0, 0, 0, 0,
6450 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6462 0, 0, 0,
6464 0, 0, 0, 0,
6466 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6468 0, 0, 0, 0,
6476 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
6478 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6485 0, 0, 0,
6487 0, 0,
6493 0, 0,
6497 0, 0,
6501 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6503 0, 0, 0, 0,
6509 0, 0, 0,
6511 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6513 0, 0,
6517 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6519 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6523 0, 0,
6527 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6538 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6540 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6542 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6548 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6554 0, 0, 0, 0,
6560 0, 0, 0,
6562 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6564 0, 0, 0, 0,
6566 0, 0, 0, 0,
6568 0, 0, ))
6570 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6577 0, 0, 0,
6579 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6581 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6583 0, 0,
6593 0, 0, 0,
6595 0, 0, 0, 0,
6597 0, 0, 0, 0,
6601 0, 0, 0,
6603 0, 0,
6609 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6611 0, 0, 0, 0,
6613 0, 0, 0, 0,
6615 0, 0, 0, 0, ))
6622 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) in r8a7791_pin_to_pocctrl()
6625 *pocctrl = 0xe606008c; in r8a7791_pin_to_pocctrl()
6627 return 31 - (pin & 0x1f); in r8a7791_pin_to_pocctrl()
6638 .unlock_reg = 0xe6060000, /* PMMR */
6660 .unlock_reg = 0xe6060000, /* PMMR */
6682 .unlock_reg = 0xe6060000, /* PMMR */
6706 .unlock_reg = 0xe6060000, /* PMMR */