xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/r8a7745.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the r8a7745 SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016-2017 Cogent Embedded Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
9*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h>
10*4882a593Smuzhiyun#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
11*4882a593Smuzhiyun#include <dt-bindings/power/r8a7745-sysc.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	compatible = "renesas,r8a7745";
15*4882a593Smuzhiyun	#address-cells = <2>;
16*4882a593Smuzhiyun	#size-cells = <2>;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	aliases {
19*4882a593Smuzhiyun		i2c0 = &i2c0;
20*4882a593Smuzhiyun		i2c1 = &i2c1;
21*4882a593Smuzhiyun		i2c2 = &i2c2;
22*4882a593Smuzhiyun		i2c3 = &i2c3;
23*4882a593Smuzhiyun		i2c4 = &i2c4;
24*4882a593Smuzhiyun		i2c5 = &i2c5;
25*4882a593Smuzhiyun		i2c6 = &iic0;
26*4882a593Smuzhiyun		i2c7 = &iic1;
27*4882a593Smuzhiyun		spi0 = &qspi;
28*4882a593Smuzhiyun		spi1 = &msiof0;
29*4882a593Smuzhiyun		spi2 = &msiof1;
30*4882a593Smuzhiyun		spi3 = &msiof2;
31*4882a593Smuzhiyun		vin0 = &vin0;
32*4882a593Smuzhiyun		vin1 = &vin1;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	/*
36*4882a593Smuzhiyun	 * The external audio clocks are configured  as 0 Hz fixed
37*4882a593Smuzhiyun	 * frequency clocks by default.  Boards that provide audio
38*4882a593Smuzhiyun	 * clocks should override them.
39*4882a593Smuzhiyun	 */
40*4882a593Smuzhiyun	audio_clka: audio_clka {
41*4882a593Smuzhiyun		compatible = "fixed-clock";
42*4882a593Smuzhiyun		#clock-cells = <0>;
43*4882a593Smuzhiyun		clock-frequency = <0>;
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun	audio_clkb: audio_clkb {
46*4882a593Smuzhiyun		compatible = "fixed-clock";
47*4882a593Smuzhiyun		#clock-cells = <0>;
48*4882a593Smuzhiyun		clock-frequency = <0>;
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun	audio_clkc: audio_clkc {
51*4882a593Smuzhiyun		compatible = "fixed-clock";
52*4882a593Smuzhiyun		#clock-cells = <0>;
53*4882a593Smuzhiyun		clock-frequency = <0>;
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	/* External CAN clock */
57*4882a593Smuzhiyun	can_clk: can {
58*4882a593Smuzhiyun		compatible = "fixed-clock";
59*4882a593Smuzhiyun		#clock-cells = <0>;
60*4882a593Smuzhiyun		/* This value must be overridden by the board. */
61*4882a593Smuzhiyun		clock-frequency = <0>;
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun	cpus {
65*4882a593Smuzhiyun		#address-cells = <1>;
66*4882a593Smuzhiyun		#size-cells = <0>;
67*4882a593Smuzhiyun		enable-method = "renesas,apmu";
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		cpu0: cpu@0 {
70*4882a593Smuzhiyun			device_type = "cpu";
71*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
72*4882a593Smuzhiyun			reg = <0>;
73*4882a593Smuzhiyun			clock-frequency = <1000000000>;
74*4882a593Smuzhiyun			clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
75*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
76*4882a593Smuzhiyun			next-level-cache = <&L2_CA7>;
77*4882a593Smuzhiyun		};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun		cpu1: cpu@1 {
80*4882a593Smuzhiyun			device_type = "cpu";
81*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
82*4882a593Smuzhiyun			reg = <1>;
83*4882a593Smuzhiyun			clock-frequency = <1000000000>;
84*4882a593Smuzhiyun			clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
85*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
86*4882a593Smuzhiyun			next-level-cache = <&L2_CA7>;
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun		L2_CA7: cache-controller-0 {
90*4882a593Smuzhiyun			compatible = "cache";
91*4882a593Smuzhiyun			cache-unified;
92*4882a593Smuzhiyun			cache-level = <2>;
93*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_CA7_SCU>;
94*4882a593Smuzhiyun		};
95*4882a593Smuzhiyun	};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	/* External root clock */
98*4882a593Smuzhiyun	extal_clk: extal {
99*4882a593Smuzhiyun		compatible = "fixed-clock";
100*4882a593Smuzhiyun		#clock-cells = <0>;
101*4882a593Smuzhiyun		/* This value must be overridden by the board. */
102*4882a593Smuzhiyun		clock-frequency = <0>;
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun	pmu {
106*4882a593Smuzhiyun		compatible = "arm,cortex-a7-pmu";
107*4882a593Smuzhiyun		interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
108*4882a593Smuzhiyun				      <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
109*4882a593Smuzhiyun		interrupt-affinity = <&cpu0>, <&cpu1>;
110*4882a593Smuzhiyun	};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun	/* External SCIF clock */
113*4882a593Smuzhiyun	scif_clk: scif {
114*4882a593Smuzhiyun		compatible = "fixed-clock";
115*4882a593Smuzhiyun		#clock-cells = <0>;
116*4882a593Smuzhiyun		/* This value must be overridden by the board. */
117*4882a593Smuzhiyun		clock-frequency = <0>;
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun	soc {
121*4882a593Smuzhiyun		compatible = "simple-bus";
122*4882a593Smuzhiyun		interrupt-parent = <&gic>;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun		#address-cells = <2>;
125*4882a593Smuzhiyun		#size-cells = <2>;
126*4882a593Smuzhiyun		ranges;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun		gpio0: gpio@e6050000 {
129*4882a593Smuzhiyun			compatible = "renesas,gpio-r8a7745",
130*4882a593Smuzhiyun				     "renesas,rcar-gen2-gpio";
131*4882a593Smuzhiyun			reg = <0 0xe6050000 0 0x50>;
132*4882a593Smuzhiyun			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
133*4882a593Smuzhiyun			#gpio-cells = <2>;
134*4882a593Smuzhiyun			gpio-controller;
135*4882a593Smuzhiyun			gpio-ranges = <&pfc 0 0 32>;
136*4882a593Smuzhiyun			#interrupt-cells = <2>;
137*4882a593Smuzhiyun			interrupt-controller;
138*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 912>;
139*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
140*4882a593Smuzhiyun			resets = <&cpg 912>;
141*4882a593Smuzhiyun		};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun		gpio1: gpio@e6051000 {
144*4882a593Smuzhiyun			compatible = "renesas,gpio-r8a7745",
145*4882a593Smuzhiyun				     "renesas,rcar-gen2-gpio";
146*4882a593Smuzhiyun			reg = <0 0xe6051000 0 0x50>;
147*4882a593Smuzhiyun			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
148*4882a593Smuzhiyun			#gpio-cells = <2>;
149*4882a593Smuzhiyun			gpio-controller;
150*4882a593Smuzhiyun			gpio-ranges = <&pfc 0 32 26>;
151*4882a593Smuzhiyun			#interrupt-cells = <2>;
152*4882a593Smuzhiyun			interrupt-controller;
153*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 911>;
154*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
155*4882a593Smuzhiyun			resets = <&cpg 911>;
156*4882a593Smuzhiyun		};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun		gpio2: gpio@e6052000 {
159*4882a593Smuzhiyun			compatible = "renesas,gpio-r8a7745",
160*4882a593Smuzhiyun				     "renesas,rcar-gen2-gpio";
161*4882a593Smuzhiyun			reg = <0 0xe6052000 0 0x50>;
162*4882a593Smuzhiyun			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
163*4882a593Smuzhiyun			#gpio-cells = <2>;
164*4882a593Smuzhiyun			gpio-controller;
165*4882a593Smuzhiyun			gpio-ranges = <&pfc 0 64 32>;
166*4882a593Smuzhiyun			#interrupt-cells = <2>;
167*4882a593Smuzhiyun			interrupt-controller;
168*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 910>;
169*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
170*4882a593Smuzhiyun			resets = <&cpg 910>;
171*4882a593Smuzhiyun		};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun		gpio3: gpio@e6053000 {
174*4882a593Smuzhiyun			compatible = "renesas,gpio-r8a7745",
175*4882a593Smuzhiyun				     "renesas,rcar-gen2-gpio";
176*4882a593Smuzhiyun			reg = <0 0xe6053000 0 0x50>;
177*4882a593Smuzhiyun			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
178*4882a593Smuzhiyun			#gpio-cells = <2>;
179*4882a593Smuzhiyun			gpio-controller;
180*4882a593Smuzhiyun			gpio-ranges = <&pfc 0 96 32>;
181*4882a593Smuzhiyun			#interrupt-cells = <2>;
182*4882a593Smuzhiyun			interrupt-controller;
183*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 909>;
184*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
185*4882a593Smuzhiyun			resets = <&cpg 909>;
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun		gpio4: gpio@e6054000 {
189*4882a593Smuzhiyun			compatible = "renesas,gpio-r8a7745",
190*4882a593Smuzhiyun				     "renesas,rcar-gen2-gpio";
191*4882a593Smuzhiyun			reg = <0 0xe6054000 0 0x50>;
192*4882a593Smuzhiyun			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
193*4882a593Smuzhiyun			#gpio-cells = <2>;
194*4882a593Smuzhiyun			gpio-controller;
195*4882a593Smuzhiyun			gpio-ranges = <&pfc 0 128 32>;
196*4882a593Smuzhiyun			#interrupt-cells = <2>;
197*4882a593Smuzhiyun			interrupt-controller;
198*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 908>;
199*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
200*4882a593Smuzhiyun			resets = <&cpg 908>;
201*4882a593Smuzhiyun		};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun		gpio5: gpio@e6055000 {
204*4882a593Smuzhiyun			compatible = "renesas,gpio-r8a7745",
205*4882a593Smuzhiyun				     "renesas,rcar-gen2-gpio";
206*4882a593Smuzhiyun			reg = <0 0xe6055000 0 0x50>;
207*4882a593Smuzhiyun			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
208*4882a593Smuzhiyun			#gpio-cells = <2>;
209*4882a593Smuzhiyun			gpio-controller;
210*4882a593Smuzhiyun			gpio-ranges = <&pfc 0 160 28>;
211*4882a593Smuzhiyun			#interrupt-cells = <2>;
212*4882a593Smuzhiyun			interrupt-controller;
213*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 907>;
214*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
215*4882a593Smuzhiyun			resets = <&cpg 907>;
216*4882a593Smuzhiyun		};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun		gpio6: gpio@e6055400 {
219*4882a593Smuzhiyun			compatible = "renesas,gpio-r8a7745",
220*4882a593Smuzhiyun				     "renesas,rcar-gen2-gpio";
221*4882a593Smuzhiyun			reg = <0 0xe6055400 0 0x50>;
222*4882a593Smuzhiyun			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
223*4882a593Smuzhiyun			#gpio-cells = <2>;
224*4882a593Smuzhiyun			gpio-controller;
225*4882a593Smuzhiyun			gpio-ranges = <&pfc 0 192 26>;
226*4882a593Smuzhiyun			#interrupt-cells = <2>;
227*4882a593Smuzhiyun			interrupt-controller;
228*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 905>;
229*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
230*4882a593Smuzhiyun			resets = <&cpg 905>;
231*4882a593Smuzhiyun		};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun		pfc: pinctrl@e6060000 {
234*4882a593Smuzhiyun			compatible = "renesas,pfc-r8a7745";
235*4882a593Smuzhiyun			reg = <0 0xe6060000 0 0x11c>;
236*4882a593Smuzhiyun		};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun		tpu: pwm@e60f0000 {
239*4882a593Smuzhiyun			compatible = "renesas,tpu-r8a7745", "renesas,tpu";
240*4882a593Smuzhiyun			reg = <0 0xe60f0000 0 0x148>;
241*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 304>;
242*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
243*4882a593Smuzhiyun			resets = <&cpg 304>;
244*4882a593Smuzhiyun			#pwm-cells = <3>;
245*4882a593Smuzhiyun			status = "disabled";
246*4882a593Smuzhiyun		};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun		cpg: clock-controller@e6150000 {
249*4882a593Smuzhiyun			compatible = "renesas,r8a7745-cpg-mssr";
250*4882a593Smuzhiyun			reg = <0 0xe6150000 0 0x1000>;
251*4882a593Smuzhiyun			clocks = <&extal_clk>, <&usb_extal_clk>;
252*4882a593Smuzhiyun			clock-names = "extal", "usb_extal";
253*4882a593Smuzhiyun			#clock-cells = <2>;
254*4882a593Smuzhiyun			#power-domain-cells = <0>;
255*4882a593Smuzhiyun			#reset-cells = <1>;
256*4882a593Smuzhiyun		};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun		apmu@e6151000 {
259*4882a593Smuzhiyun			compatible = "renesas,r8a7745-apmu", "renesas,apmu";
260*4882a593Smuzhiyun			reg = <0 0xe6151000 0 0x188>;
261*4882a593Smuzhiyun			cpus = <&cpu0 &cpu1>;
262*4882a593Smuzhiyun		};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun		rst: reset-controller@e6160000 {
265*4882a593Smuzhiyun			compatible = "renesas,r8a7745-rst";
266*4882a593Smuzhiyun			reg = <0 0xe6160000 0 0x100>;
267*4882a593Smuzhiyun		};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun		rwdt: watchdog@e6020000 {
270*4882a593Smuzhiyun			compatible = "renesas,r8a7745-wdt",
271*4882a593Smuzhiyun				     "renesas,rcar-gen2-wdt";
272*4882a593Smuzhiyun			reg = <0 0xe6020000 0 0x0c>;
273*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 402>;
274*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
275*4882a593Smuzhiyun			resets = <&cpg 402>;
276*4882a593Smuzhiyun			status = "disabled";
277*4882a593Smuzhiyun		};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun		sysc: system-controller@e6180000 {
280*4882a593Smuzhiyun			compatible = "renesas,r8a7745-sysc";
281*4882a593Smuzhiyun			reg = <0 0xe6180000 0 0x200>;
282*4882a593Smuzhiyun			#power-domain-cells = <1>;
283*4882a593Smuzhiyun		};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun		irqc: interrupt-controller@e61c0000 {
286*4882a593Smuzhiyun			compatible = "renesas,irqc-r8a7745", "renesas,irqc";
287*4882a593Smuzhiyun			#interrupt-cells = <2>;
288*4882a593Smuzhiyun			interrupt-controller;
289*4882a593Smuzhiyun			reg = <0 0xe61c0000 0 0x200>;
290*4882a593Smuzhiyun			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
291*4882a593Smuzhiyun				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
292*4882a593Smuzhiyun				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
293*4882a593Smuzhiyun				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
294*4882a593Smuzhiyun				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
295*4882a593Smuzhiyun				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
296*4882a593Smuzhiyun				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
297*4882a593Smuzhiyun				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
298*4882a593Smuzhiyun				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
299*4882a593Smuzhiyun				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
300*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 407>;
301*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
302*4882a593Smuzhiyun			resets = <&cpg 407>;
303*4882a593Smuzhiyun		};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun		ipmmu_sy0: iommu@e6280000 {
306*4882a593Smuzhiyun			compatible = "renesas,ipmmu-r8a7745",
307*4882a593Smuzhiyun				     "renesas,ipmmu-vmsa";
308*4882a593Smuzhiyun			reg = <0 0xe6280000 0 0x1000>;
309*4882a593Smuzhiyun			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
310*4882a593Smuzhiyun				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
311*4882a593Smuzhiyun			#iommu-cells = <1>;
312*4882a593Smuzhiyun			status = "disabled";
313*4882a593Smuzhiyun		};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun		ipmmu_sy1: iommu@e6290000 {
316*4882a593Smuzhiyun			compatible = "renesas,ipmmu-r8a7745",
317*4882a593Smuzhiyun				     "renesas,ipmmu-vmsa";
318*4882a593Smuzhiyun			reg = <0 0xe6290000 0 0x1000>;
319*4882a593Smuzhiyun			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
320*4882a593Smuzhiyun			#iommu-cells = <1>;
321*4882a593Smuzhiyun			status = "disabled";
322*4882a593Smuzhiyun		};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun		ipmmu_ds: iommu@e6740000 {
325*4882a593Smuzhiyun			compatible = "renesas,ipmmu-r8a7745",
326*4882a593Smuzhiyun				     "renesas,ipmmu-vmsa";
327*4882a593Smuzhiyun			reg = <0 0xe6740000 0 0x1000>;
328*4882a593Smuzhiyun			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
329*4882a593Smuzhiyun				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
330*4882a593Smuzhiyun			#iommu-cells = <1>;
331*4882a593Smuzhiyun			status = "disabled";
332*4882a593Smuzhiyun		};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun		ipmmu_mp: iommu@ec680000 {
335*4882a593Smuzhiyun			compatible = "renesas,ipmmu-r8a7745",
336*4882a593Smuzhiyun				     "renesas,ipmmu-vmsa";
337*4882a593Smuzhiyun			reg = <0 0xec680000 0 0x1000>;
338*4882a593Smuzhiyun			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
339*4882a593Smuzhiyun			#iommu-cells = <1>;
340*4882a593Smuzhiyun			status = "disabled";
341*4882a593Smuzhiyun		};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun		ipmmu_mx: iommu@fe951000 {
344*4882a593Smuzhiyun			compatible = "renesas,ipmmu-r8a7745",
345*4882a593Smuzhiyun				     "renesas,ipmmu-vmsa";
346*4882a593Smuzhiyun			reg = <0 0xfe951000 0 0x1000>;
347*4882a593Smuzhiyun			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
348*4882a593Smuzhiyun				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
349*4882a593Smuzhiyun			#iommu-cells = <1>;
350*4882a593Smuzhiyun			status = "disabled";
351*4882a593Smuzhiyun		};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun		ipmmu_gp: iommu@e62a0000 {
354*4882a593Smuzhiyun			compatible = "renesas,ipmmu-r8a7745",
355*4882a593Smuzhiyun				     "renesas,ipmmu-vmsa";
356*4882a593Smuzhiyun			reg = <0 0xe62a0000 0 0x1000>;
357*4882a593Smuzhiyun			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
358*4882a593Smuzhiyun				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
359*4882a593Smuzhiyun			#iommu-cells = <1>;
360*4882a593Smuzhiyun			status = "disabled";
361*4882a593Smuzhiyun		};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun		icram0:	sram@e63a0000 {
364*4882a593Smuzhiyun			compatible = "mmio-sram";
365*4882a593Smuzhiyun			reg = <0 0xe63a0000 0 0x12000>;
366*4882a593Smuzhiyun			#address-cells = <1>;
367*4882a593Smuzhiyun			#size-cells = <1>;
368*4882a593Smuzhiyun			ranges = <0 0 0xe63a0000 0x12000>;
369*4882a593Smuzhiyun		};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun		icram1:	sram@e63c0000 {
372*4882a593Smuzhiyun			compatible = "mmio-sram";
373*4882a593Smuzhiyun			reg = <0 0xe63c0000 0 0x1000>;
374*4882a593Smuzhiyun			#address-cells = <1>;
375*4882a593Smuzhiyun			#size-cells = <1>;
376*4882a593Smuzhiyun			ranges = <0 0 0xe63c0000 0x1000>;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun			smp-sram@0 {
379*4882a593Smuzhiyun				compatible = "renesas,smp-sram";
380*4882a593Smuzhiyun				reg = <0 0x100>;
381*4882a593Smuzhiyun			};
382*4882a593Smuzhiyun		};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun		icram2:	sram@e6300000 {
385*4882a593Smuzhiyun			compatible = "mmio-sram";
386*4882a593Smuzhiyun			reg = <0 0xe6300000 0 0x40000>;
387*4882a593Smuzhiyun			#address-cells = <1>;
388*4882a593Smuzhiyun			#size-cells = <1>;
389*4882a593Smuzhiyun			ranges = <0 0 0xe6300000 0x40000>;
390*4882a593Smuzhiyun		};
391*4882a593Smuzhiyun		i2c0: i2c@e6508000 {
392*4882a593Smuzhiyun			#address-cells = <1>;
393*4882a593Smuzhiyun			#size-cells = <0>;
394*4882a593Smuzhiyun			compatible = "renesas,i2c-r8a7745",
395*4882a593Smuzhiyun				     "renesas,rcar-gen2-i2c";
396*4882a593Smuzhiyun			reg = <0 0xe6508000 0 0x40>;
397*4882a593Smuzhiyun			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
398*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 931>;
399*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
400*4882a593Smuzhiyun			resets = <&cpg 931>;
401*4882a593Smuzhiyun			i2c-scl-internal-delay-ns = <6>;
402*4882a593Smuzhiyun			status = "disabled";
403*4882a593Smuzhiyun		};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun		i2c1: i2c@e6518000 {
406*4882a593Smuzhiyun			#address-cells = <1>;
407*4882a593Smuzhiyun			#size-cells = <0>;
408*4882a593Smuzhiyun			compatible = "renesas,i2c-r8a7745",
409*4882a593Smuzhiyun				     "renesas,rcar-gen2-i2c";
410*4882a593Smuzhiyun			reg = <0 0xe6518000 0 0x40>;
411*4882a593Smuzhiyun			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
412*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 930>;
413*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
414*4882a593Smuzhiyun			resets = <&cpg 930>;
415*4882a593Smuzhiyun			i2c-scl-internal-delay-ns = <6>;
416*4882a593Smuzhiyun			status = "disabled";
417*4882a593Smuzhiyun		};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun		i2c2: i2c@e6530000 {
420*4882a593Smuzhiyun			#address-cells = <1>;
421*4882a593Smuzhiyun			#size-cells = <0>;
422*4882a593Smuzhiyun			compatible = "renesas,i2c-r8a7745",
423*4882a593Smuzhiyun				     "renesas,rcar-gen2-i2c";
424*4882a593Smuzhiyun			reg = <0 0xe6530000 0 0x40>;
425*4882a593Smuzhiyun			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
426*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 929>;
427*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
428*4882a593Smuzhiyun			resets = <&cpg 929>;
429*4882a593Smuzhiyun			i2c-scl-internal-delay-ns = <6>;
430*4882a593Smuzhiyun			status = "disabled";
431*4882a593Smuzhiyun		};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun		i2c3: i2c@e6540000 {
434*4882a593Smuzhiyun			#address-cells = <1>;
435*4882a593Smuzhiyun			#size-cells = <0>;
436*4882a593Smuzhiyun			compatible = "renesas,i2c-r8a7745",
437*4882a593Smuzhiyun				     "renesas,rcar-gen2-i2c";
438*4882a593Smuzhiyun			reg = <0 0xe6540000 0 0x40>;
439*4882a593Smuzhiyun			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
440*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 928>;
441*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
442*4882a593Smuzhiyun			resets = <&cpg 928>;
443*4882a593Smuzhiyun			i2c-scl-internal-delay-ns = <6>;
444*4882a593Smuzhiyun			status = "disabled";
445*4882a593Smuzhiyun		};
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun		i2c4: i2c@e6520000 {
448*4882a593Smuzhiyun			#address-cells = <1>;
449*4882a593Smuzhiyun			#size-cells = <0>;
450*4882a593Smuzhiyun			compatible = "renesas,i2c-r8a7745",
451*4882a593Smuzhiyun				     "renesas,rcar-gen2-i2c";
452*4882a593Smuzhiyun			reg = <0 0xe6520000 0 0x40>;
453*4882a593Smuzhiyun			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
454*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 927>;
455*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
456*4882a593Smuzhiyun			resets = <&cpg 927>;
457*4882a593Smuzhiyun			i2c-scl-internal-delay-ns = <6>;
458*4882a593Smuzhiyun			status = "disabled";
459*4882a593Smuzhiyun		};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun		i2c5: i2c@e6528000 {
462*4882a593Smuzhiyun			#address-cells = <1>;
463*4882a593Smuzhiyun			#size-cells = <0>;
464*4882a593Smuzhiyun			compatible = "renesas,i2c-r8a7745",
465*4882a593Smuzhiyun				     "renesas,rcar-gen2-i2c";
466*4882a593Smuzhiyun			reg = <0 0xe6528000 0 0x40>;
467*4882a593Smuzhiyun			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
468*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 925>;
469*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
470*4882a593Smuzhiyun			resets = <&cpg 925>;
471*4882a593Smuzhiyun			i2c-scl-internal-delay-ns = <6>;
472*4882a593Smuzhiyun			status = "disabled";
473*4882a593Smuzhiyun		};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun		iic0: i2c@e6500000 {
476*4882a593Smuzhiyun			#address-cells = <1>;
477*4882a593Smuzhiyun			#size-cells = <0>;
478*4882a593Smuzhiyun			compatible = "renesas,iic-r8a7745",
479*4882a593Smuzhiyun				     "renesas,rcar-gen2-iic",
480*4882a593Smuzhiyun				     "renesas,rmobile-iic";
481*4882a593Smuzhiyun			reg = <0 0xe6500000 0 0x425>;
482*4882a593Smuzhiyun			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
483*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 318>;
484*4882a593Smuzhiyun			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
485*4882a593Smuzhiyun			       <&dmac1 0x61>, <&dmac1 0x62>;
486*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
487*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
488*4882a593Smuzhiyun			resets = <&cpg 318>;
489*4882a593Smuzhiyun			status = "disabled";
490*4882a593Smuzhiyun		};
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun		iic1: i2c@e6510000 {
493*4882a593Smuzhiyun			#address-cells = <1>;
494*4882a593Smuzhiyun			#size-cells = <0>;
495*4882a593Smuzhiyun			compatible = "renesas,iic-r8a7745",
496*4882a593Smuzhiyun				     "renesas,rcar-gen2-iic",
497*4882a593Smuzhiyun				     "renesas,rmobile-iic";
498*4882a593Smuzhiyun			reg = <0 0xe6510000 0 0x425>;
499*4882a593Smuzhiyun			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
500*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 323>;
501*4882a593Smuzhiyun			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
502*4882a593Smuzhiyun			       <&dmac1 0x65>, <&dmac1 0x66>;
503*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
504*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
505*4882a593Smuzhiyun			resets = <&cpg 323>;
506*4882a593Smuzhiyun			status = "disabled";
507*4882a593Smuzhiyun		};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun		hsusb: usb@e6590000 {
510*4882a593Smuzhiyun			compatible = "renesas,usbhs-r8a7745",
511*4882a593Smuzhiyun				     "renesas,rcar-gen2-usbhs";
512*4882a593Smuzhiyun			reg = <0 0xe6590000 0 0x100>;
513*4882a593Smuzhiyun			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
514*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 704>;
515*4882a593Smuzhiyun			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
516*4882a593Smuzhiyun			       <&usb_dmac1 0>, <&usb_dmac1 1>;
517*4882a593Smuzhiyun			dma-names = "ch0", "ch1", "ch2", "ch3";
518*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
519*4882a593Smuzhiyun			resets = <&cpg 704>;
520*4882a593Smuzhiyun			renesas,buswait = <4>;
521*4882a593Smuzhiyun			phys = <&usb0 1>;
522*4882a593Smuzhiyun			phy-names = "usb";
523*4882a593Smuzhiyun			status = "disabled";
524*4882a593Smuzhiyun		};
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun		usbphy: usb-phy@e6590100 {
527*4882a593Smuzhiyun			compatible = "renesas,usb-phy-r8a7745",
528*4882a593Smuzhiyun				     "renesas,rcar-gen2-usb-phy";
529*4882a593Smuzhiyun			reg = <0 0xe6590100 0 0x100>;
530*4882a593Smuzhiyun			#address-cells = <1>;
531*4882a593Smuzhiyun			#size-cells = <0>;
532*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 704>;
533*4882a593Smuzhiyun			clock-names = "usbhs";
534*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
535*4882a593Smuzhiyun			resets = <&cpg 704>;
536*4882a593Smuzhiyun			status = "disabled";
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun			usb0: usb-channel@0 {
539*4882a593Smuzhiyun				reg = <0>;
540*4882a593Smuzhiyun				#phy-cells = <1>;
541*4882a593Smuzhiyun			};
542*4882a593Smuzhiyun			usb2: usb-channel@2 {
543*4882a593Smuzhiyun				reg = <2>;
544*4882a593Smuzhiyun				#phy-cells = <1>;
545*4882a593Smuzhiyun			};
546*4882a593Smuzhiyun		};
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun		usb_dmac0: dma-controller@e65a0000 {
549*4882a593Smuzhiyun			compatible = "renesas,r8a7745-usb-dmac",
550*4882a593Smuzhiyun				     "renesas,usb-dmac";
551*4882a593Smuzhiyun			reg = <0 0xe65a0000 0 0x100>;
552*4882a593Smuzhiyun			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
553*4882a593Smuzhiyun				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
554*4882a593Smuzhiyun			interrupt-names = "ch0", "ch1";
555*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 330>;
556*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
557*4882a593Smuzhiyun			resets = <&cpg 330>;
558*4882a593Smuzhiyun			#dma-cells = <1>;
559*4882a593Smuzhiyun			dma-channels = <2>;
560*4882a593Smuzhiyun		};
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun		usb_dmac1: dma-controller@e65b0000 {
563*4882a593Smuzhiyun			compatible = "renesas,r8a7745-usb-dmac",
564*4882a593Smuzhiyun				     "renesas,usb-dmac";
565*4882a593Smuzhiyun			reg = <0 0xe65b0000 0 0x100>;
566*4882a593Smuzhiyun			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
567*4882a593Smuzhiyun				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
568*4882a593Smuzhiyun			interrupt-names = "ch0", "ch1";
569*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 331>;
570*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
571*4882a593Smuzhiyun			resets = <&cpg 331>;
572*4882a593Smuzhiyun			#dma-cells = <1>;
573*4882a593Smuzhiyun			dma-channels = <2>;
574*4882a593Smuzhiyun		};
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun		dmac0: dma-controller@e6700000 {
577*4882a593Smuzhiyun			compatible = "renesas,dmac-r8a7745",
578*4882a593Smuzhiyun				     "renesas,rcar-dmac";
579*4882a593Smuzhiyun			reg = <0 0xe6700000 0 0x20000>;
580*4882a593Smuzhiyun			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
581*4882a593Smuzhiyun				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
582*4882a593Smuzhiyun				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
583*4882a593Smuzhiyun				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
584*4882a593Smuzhiyun				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
585*4882a593Smuzhiyun				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
586*4882a593Smuzhiyun				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
587*4882a593Smuzhiyun				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
588*4882a593Smuzhiyun				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
589*4882a593Smuzhiyun				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
590*4882a593Smuzhiyun				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
591*4882a593Smuzhiyun				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
592*4882a593Smuzhiyun				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
593*4882a593Smuzhiyun				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
594*4882a593Smuzhiyun				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
595*4882a593Smuzhiyun				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
596*4882a593Smuzhiyun			interrupt-names = "error",
597*4882a593Smuzhiyun					  "ch0", "ch1", "ch2", "ch3",
598*4882a593Smuzhiyun					  "ch4", "ch5", "ch6", "ch7",
599*4882a593Smuzhiyun					  "ch8", "ch9", "ch10", "ch11",
600*4882a593Smuzhiyun					  "ch12", "ch13", "ch14";
601*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 219>;
602*4882a593Smuzhiyun			clock-names = "fck";
603*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
604*4882a593Smuzhiyun			resets = <&cpg 219>;
605*4882a593Smuzhiyun			#dma-cells = <1>;
606*4882a593Smuzhiyun			dma-channels = <15>;
607*4882a593Smuzhiyun		};
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun		dmac1: dma-controller@e6720000 {
610*4882a593Smuzhiyun			compatible = "renesas,dmac-r8a7745",
611*4882a593Smuzhiyun				     "renesas,rcar-dmac";
612*4882a593Smuzhiyun			reg = <0 0xe6720000 0 0x20000>;
613*4882a593Smuzhiyun			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
614*4882a593Smuzhiyun				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
615*4882a593Smuzhiyun				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
616*4882a593Smuzhiyun				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
617*4882a593Smuzhiyun				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
618*4882a593Smuzhiyun				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
619*4882a593Smuzhiyun				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
620*4882a593Smuzhiyun				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
621*4882a593Smuzhiyun				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
622*4882a593Smuzhiyun				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
623*4882a593Smuzhiyun				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
624*4882a593Smuzhiyun				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
625*4882a593Smuzhiyun				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
626*4882a593Smuzhiyun				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
627*4882a593Smuzhiyun				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
628*4882a593Smuzhiyun				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
629*4882a593Smuzhiyun			interrupt-names = "error",
630*4882a593Smuzhiyun					  "ch0", "ch1", "ch2", "ch3",
631*4882a593Smuzhiyun					  "ch4", "ch5", "ch6", "ch7",
632*4882a593Smuzhiyun					  "ch8", "ch9", "ch10", "ch11",
633*4882a593Smuzhiyun					  "ch12", "ch13", "ch14";
634*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 218>;
635*4882a593Smuzhiyun			clock-names = "fck";
636*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
637*4882a593Smuzhiyun			resets = <&cpg 218>;
638*4882a593Smuzhiyun			#dma-cells = <1>;
639*4882a593Smuzhiyun			dma-channels = <15>;
640*4882a593Smuzhiyun		};
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun		avb: ethernet@e6800000 {
643*4882a593Smuzhiyun			compatible = "renesas,etheravb-r8a7745",
644*4882a593Smuzhiyun				     "renesas,etheravb-rcar-gen2";
645*4882a593Smuzhiyun			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
646*4882a593Smuzhiyun			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
647*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 812>;
648*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
649*4882a593Smuzhiyun			resets = <&cpg 812>;
650*4882a593Smuzhiyun			#address-cells = <1>;
651*4882a593Smuzhiyun			#size-cells = <0>;
652*4882a593Smuzhiyun			status = "disabled";
653*4882a593Smuzhiyun		};
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun		qspi: spi@e6b10000 {
656*4882a593Smuzhiyun			compatible = "renesas,qspi-r8a7745", "renesas,qspi";
657*4882a593Smuzhiyun			reg = <0 0xe6b10000 0 0x2c>;
658*4882a593Smuzhiyun			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
659*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 917>;
660*4882a593Smuzhiyun			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
661*4882a593Smuzhiyun			       <&dmac1 0x17>, <&dmac1 0x18>;
662*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
663*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
664*4882a593Smuzhiyun			num-cs = <1>;
665*4882a593Smuzhiyun			#address-cells = <1>;
666*4882a593Smuzhiyun			#size-cells = <0>;
667*4882a593Smuzhiyun			resets = <&cpg 917>;
668*4882a593Smuzhiyun			status = "disabled";
669*4882a593Smuzhiyun		};
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun		scifa0: serial@e6c40000 {
672*4882a593Smuzhiyun			compatible = "renesas,scifa-r8a7745",
673*4882a593Smuzhiyun				     "renesas,rcar-gen2-scifa", "renesas,scifa";
674*4882a593Smuzhiyun			reg = <0 0xe6c40000 0 0x40>;
675*4882a593Smuzhiyun			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
676*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 204>;
677*4882a593Smuzhiyun			clock-names = "fck";
678*4882a593Smuzhiyun			dmas = <&dmac0 0x21>, <&dmac0 0x22>,
679*4882a593Smuzhiyun			       <&dmac1 0x21>, <&dmac1 0x22>;
680*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
681*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
682*4882a593Smuzhiyun			resets = <&cpg 204>;
683*4882a593Smuzhiyun			status = "disabled";
684*4882a593Smuzhiyun		};
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun		scifa1: serial@e6c50000 {
687*4882a593Smuzhiyun			compatible = "renesas,scifa-r8a7745",
688*4882a593Smuzhiyun				     "renesas,rcar-gen2-scifa", "renesas,scifa";
689*4882a593Smuzhiyun			reg = <0 0xe6c50000 0 0x40>;
690*4882a593Smuzhiyun			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
691*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 203>;
692*4882a593Smuzhiyun			clock-names = "fck";
693*4882a593Smuzhiyun			dmas = <&dmac0 0x25>, <&dmac0 0x26>,
694*4882a593Smuzhiyun			       <&dmac1 0x25>, <&dmac1 0x26>;
695*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
696*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
697*4882a593Smuzhiyun			resets = <&cpg 203>;
698*4882a593Smuzhiyun			status = "disabled";
699*4882a593Smuzhiyun		};
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun		scifa2: serial@e6c60000 {
702*4882a593Smuzhiyun			compatible = "renesas,scifa-r8a7745",
703*4882a593Smuzhiyun				     "renesas,rcar-gen2-scifa", "renesas,scifa";
704*4882a593Smuzhiyun			reg = <0 0xe6c60000 0 0x40>;
705*4882a593Smuzhiyun			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
706*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 202>;
707*4882a593Smuzhiyun			clock-names = "fck";
708*4882a593Smuzhiyun			dmas = <&dmac0 0x27>, <&dmac0 0x28>,
709*4882a593Smuzhiyun			       <&dmac1 0x27>, <&dmac1 0x28>;
710*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
711*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
712*4882a593Smuzhiyun			resets = <&cpg 202>;
713*4882a593Smuzhiyun			status = "disabled";
714*4882a593Smuzhiyun		};
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun		scifa3: serial@e6c70000 {
717*4882a593Smuzhiyun			compatible = "renesas,scifa-r8a7745",
718*4882a593Smuzhiyun				     "renesas,rcar-gen2-scifa", "renesas,scifa";
719*4882a593Smuzhiyun			reg = <0 0xe6c70000 0 0x40>;
720*4882a593Smuzhiyun			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
721*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 1106>;
722*4882a593Smuzhiyun			clock-names = "fck";
723*4882a593Smuzhiyun			dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
724*4882a593Smuzhiyun			       <&dmac1 0x1b>, <&dmac1 0x1c>;
725*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
726*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
727*4882a593Smuzhiyun			resets = <&cpg 1106>;
728*4882a593Smuzhiyun			status = "disabled";
729*4882a593Smuzhiyun		};
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun		scifa4: serial@e6c78000 {
732*4882a593Smuzhiyun			compatible = "renesas,scifa-r8a7745",
733*4882a593Smuzhiyun				     "renesas,rcar-gen2-scifa", "renesas,scifa";
734*4882a593Smuzhiyun			reg = <0 0xe6c78000 0 0x40>;
735*4882a593Smuzhiyun			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
736*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 1107>;
737*4882a593Smuzhiyun			clock-names = "fck";
738*4882a593Smuzhiyun			dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
739*4882a593Smuzhiyun			       <&dmac1 0x1f>, <&dmac1 0x20>;
740*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
741*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
742*4882a593Smuzhiyun			resets = <&cpg 1107>;
743*4882a593Smuzhiyun			status = "disabled";
744*4882a593Smuzhiyun		};
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun		scifa5: serial@e6c80000 {
747*4882a593Smuzhiyun			compatible = "renesas,scifa-r8a7745",
748*4882a593Smuzhiyun				     "renesas,rcar-gen2-scifa", "renesas,scifa";
749*4882a593Smuzhiyun			reg = <0 0xe6c80000 0 0x40>;
750*4882a593Smuzhiyun			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
751*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 1108>;
752*4882a593Smuzhiyun			clock-names = "fck";
753*4882a593Smuzhiyun			dmas = <&dmac0 0x23>, <&dmac0 0x24>,
754*4882a593Smuzhiyun			       <&dmac1 0x23>, <&dmac1 0x24>;
755*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
756*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
757*4882a593Smuzhiyun			resets = <&cpg 1108>;
758*4882a593Smuzhiyun			status = "disabled";
759*4882a593Smuzhiyun		};
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun		scifb0: serial@e6c20000 {
762*4882a593Smuzhiyun			compatible = "renesas,scifb-r8a7745",
763*4882a593Smuzhiyun				     "renesas,rcar-gen2-scifb", "renesas,scifb";
764*4882a593Smuzhiyun			reg = <0 0xe6c20000 0 0x100>;
765*4882a593Smuzhiyun			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
766*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 206>;
767*4882a593Smuzhiyun			clock-names = "fck";
768*4882a593Smuzhiyun			dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
769*4882a593Smuzhiyun			       <&dmac1 0x3d>, <&dmac1 0x3e>;
770*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
771*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
772*4882a593Smuzhiyun			resets = <&cpg 206>;
773*4882a593Smuzhiyun			status = "disabled";
774*4882a593Smuzhiyun		};
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun		scifb1: serial@e6c30000 {
777*4882a593Smuzhiyun			compatible = "renesas,scifb-r8a7745",
778*4882a593Smuzhiyun				     "renesas,rcar-gen2-scifb", "renesas,scifb";
779*4882a593Smuzhiyun			reg = <0 0xe6c30000 0 0x100>;
780*4882a593Smuzhiyun			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
781*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 207>;
782*4882a593Smuzhiyun			clock-names = "fck";
783*4882a593Smuzhiyun			dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
784*4882a593Smuzhiyun			       <&dmac1 0x19>, <&dmac1 0x1a>;
785*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
786*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
787*4882a593Smuzhiyun			resets = <&cpg 207>;
788*4882a593Smuzhiyun			status = "disabled";
789*4882a593Smuzhiyun		};
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun		scifb2: serial@e6ce0000 {
792*4882a593Smuzhiyun			compatible = "renesas,scifb-r8a7745",
793*4882a593Smuzhiyun				     "renesas,rcar-gen2-scifb", "renesas,scifb";
794*4882a593Smuzhiyun			reg = <0 0xe6ce0000 0 0x100>;
795*4882a593Smuzhiyun			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
796*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 216>;
797*4882a593Smuzhiyun			clock-names = "fck";
798*4882a593Smuzhiyun			dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
799*4882a593Smuzhiyun			       <&dmac1 0x1d>, <&dmac1 0x1e>;
800*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
801*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
802*4882a593Smuzhiyun			resets = <&cpg 216>;
803*4882a593Smuzhiyun			status = "disabled";
804*4882a593Smuzhiyun		};
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun		scif0: serial@e6e60000 {
807*4882a593Smuzhiyun			compatible = "renesas,scif-r8a7745",
808*4882a593Smuzhiyun				     "renesas,rcar-gen2-scif", "renesas,scif";
809*4882a593Smuzhiyun			reg = <0 0xe6e60000 0 0x40>;
810*4882a593Smuzhiyun			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
811*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 721>,
812*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
813*4882a593Smuzhiyun			clock-names = "fck", "brg_int", "scif_clk";
814*4882a593Smuzhiyun			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
815*4882a593Smuzhiyun			       <&dmac1 0x29>, <&dmac1 0x2a>;
816*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
817*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
818*4882a593Smuzhiyun			resets = <&cpg 721>;
819*4882a593Smuzhiyun			status = "disabled";
820*4882a593Smuzhiyun		};
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun		scif1: serial@e6e68000 {
823*4882a593Smuzhiyun			compatible = "renesas,scif-r8a7745",
824*4882a593Smuzhiyun				     "renesas,rcar-gen2-scif", "renesas,scif";
825*4882a593Smuzhiyun			reg = <0 0xe6e68000 0 0x40>;
826*4882a593Smuzhiyun			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
827*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 720>,
828*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
829*4882a593Smuzhiyun			clock-names = "fck", "brg_int", "scif_clk";
830*4882a593Smuzhiyun			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
831*4882a593Smuzhiyun			       <&dmac1 0x2d>, <&dmac1 0x2e>;
832*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
833*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
834*4882a593Smuzhiyun			resets = <&cpg 720>;
835*4882a593Smuzhiyun			status = "disabled";
836*4882a593Smuzhiyun		};
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun		scif2: serial@e6e58000 {
839*4882a593Smuzhiyun			compatible = "renesas,scif-r8a7745",
840*4882a593Smuzhiyun				     "renesas,rcar-gen2-scif", "renesas,scif";
841*4882a593Smuzhiyun			reg = <0 0xe6e58000 0 0x40>;
842*4882a593Smuzhiyun			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
843*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 719>,
844*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
845*4882a593Smuzhiyun			clock-names = "fck", "brg_int", "scif_clk";
846*4882a593Smuzhiyun			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
847*4882a593Smuzhiyun			       <&dmac1 0x2b>, <&dmac1 0x2c>;
848*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
849*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
850*4882a593Smuzhiyun			resets = <&cpg 719>;
851*4882a593Smuzhiyun			status = "disabled";
852*4882a593Smuzhiyun		};
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun		scif3: serial@e6ea8000 {
855*4882a593Smuzhiyun			compatible = "renesas,scif-r8a7745",
856*4882a593Smuzhiyun				     "renesas,rcar-gen2-scif", "renesas,scif";
857*4882a593Smuzhiyun			reg = <0 0xe6ea8000 0 0x40>;
858*4882a593Smuzhiyun			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
859*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 718>,
860*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
861*4882a593Smuzhiyun			clock-names = "fck", "brg_int", "scif_clk";
862*4882a593Smuzhiyun			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
863*4882a593Smuzhiyun			       <&dmac1 0x2f>, <&dmac1 0x30>;
864*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
865*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
866*4882a593Smuzhiyun			resets = <&cpg 718>;
867*4882a593Smuzhiyun			status = "disabled";
868*4882a593Smuzhiyun		};
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun		scif4: serial@e6ee0000 {
871*4882a593Smuzhiyun			compatible = "renesas,scif-r8a7745",
872*4882a593Smuzhiyun				     "renesas,rcar-gen2-scif", "renesas,scif";
873*4882a593Smuzhiyun			reg = <0 0xe6ee0000 0 0x40>;
874*4882a593Smuzhiyun			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
875*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 715>,
876*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
877*4882a593Smuzhiyun			clock-names = "fck", "brg_int", "scif_clk";
878*4882a593Smuzhiyun			dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
879*4882a593Smuzhiyun			       <&dmac1 0xfb>, <&dmac1 0xfc>;
880*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
881*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
882*4882a593Smuzhiyun			resets = <&cpg 715>;
883*4882a593Smuzhiyun			status = "disabled";
884*4882a593Smuzhiyun		};
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun		scif5: serial@e6ee8000 {
887*4882a593Smuzhiyun			compatible = "renesas,scif-r8a7745",
888*4882a593Smuzhiyun				     "renesas,rcar-gen2-scif", "renesas,scif";
889*4882a593Smuzhiyun			reg = <0 0xe6ee8000 0 0x40>;
890*4882a593Smuzhiyun			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
891*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 714>,
892*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
893*4882a593Smuzhiyun			clock-names = "fck", "brg_int", "scif_clk";
894*4882a593Smuzhiyun			dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
895*4882a593Smuzhiyun			       <&dmac1 0xfd>, <&dmac1 0xfe>;
896*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
897*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
898*4882a593Smuzhiyun			resets = <&cpg 714>;
899*4882a593Smuzhiyun			status = "disabled";
900*4882a593Smuzhiyun		};
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun		hscif0: serial@e62c0000 {
903*4882a593Smuzhiyun			compatible = "renesas,hscif-r8a7745",
904*4882a593Smuzhiyun				     "renesas,rcar-gen2-hscif", "renesas,hscif";
905*4882a593Smuzhiyun			reg = <0 0xe62c0000 0 0x60>;
906*4882a593Smuzhiyun			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
907*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 717>,
908*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
909*4882a593Smuzhiyun			clock-names = "fck", "brg_int", "scif_clk";
910*4882a593Smuzhiyun			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
911*4882a593Smuzhiyun			       <&dmac1 0x39>, <&dmac1 0x3a>;
912*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
913*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
914*4882a593Smuzhiyun			resets = <&cpg 717>;
915*4882a593Smuzhiyun			status = "disabled";
916*4882a593Smuzhiyun		};
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun		hscif1: serial@e62c8000 {
919*4882a593Smuzhiyun			compatible = "renesas,hscif-r8a7745",
920*4882a593Smuzhiyun				     "renesas,rcar-gen2-hscif", "renesas,hscif";
921*4882a593Smuzhiyun			reg = <0 0xe62c8000 0 0x60>;
922*4882a593Smuzhiyun			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
923*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 716>,
924*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
925*4882a593Smuzhiyun			clock-names = "fck", "brg_int", "scif_clk";
926*4882a593Smuzhiyun			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
927*4882a593Smuzhiyun			       <&dmac1 0x4d>, <&dmac1 0x4e>;
928*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
929*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
930*4882a593Smuzhiyun			resets = <&cpg 716>;
931*4882a593Smuzhiyun			status = "disabled";
932*4882a593Smuzhiyun		};
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun		hscif2: serial@e62d0000 {
935*4882a593Smuzhiyun			compatible = "renesas,hscif-r8a7745",
936*4882a593Smuzhiyun				     "renesas,rcar-gen2-hscif", "renesas,hscif";
937*4882a593Smuzhiyun			reg = <0 0xe62d0000 0 0x60>;
938*4882a593Smuzhiyun			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
939*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 713>,
940*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
941*4882a593Smuzhiyun			clock-names = "fck", "brg_int", "scif_clk";
942*4882a593Smuzhiyun			dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
943*4882a593Smuzhiyun			       <&dmac1 0x3b>, <&dmac1 0x3c>;
944*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
945*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
946*4882a593Smuzhiyun			resets = <&cpg 713>;
947*4882a593Smuzhiyun			status = "disabled";
948*4882a593Smuzhiyun		};
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun		msiof0: spi@e6e20000 {
951*4882a593Smuzhiyun			compatible = "renesas,msiof-r8a7745",
952*4882a593Smuzhiyun				     "renesas,rcar-gen2-msiof";
953*4882a593Smuzhiyun			reg = <0 0xe6e20000 0 0x0064>;
954*4882a593Smuzhiyun			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
955*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 000>;
956*4882a593Smuzhiyun			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
957*4882a593Smuzhiyun			       <&dmac1 0x51>, <&dmac1 0x52>;
958*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
959*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
960*4882a593Smuzhiyun			#address-cells = <1>;
961*4882a593Smuzhiyun			#size-cells = <0>;
962*4882a593Smuzhiyun			resets = <&cpg 000>;
963*4882a593Smuzhiyun			status = "disabled";
964*4882a593Smuzhiyun		};
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun		msiof1: spi@e6e10000 {
967*4882a593Smuzhiyun			compatible = "renesas,msiof-r8a7745",
968*4882a593Smuzhiyun				     "renesas,rcar-gen2-msiof";
969*4882a593Smuzhiyun			reg = <0 0xe6e10000 0 0x0064>;
970*4882a593Smuzhiyun			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
971*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 208>;
972*4882a593Smuzhiyun			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
973*4882a593Smuzhiyun			       <&dmac1 0x55>, <&dmac1 0x56>;
974*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
975*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
976*4882a593Smuzhiyun			#address-cells = <1>;
977*4882a593Smuzhiyun			#size-cells = <0>;
978*4882a593Smuzhiyun			resets = <&cpg 208>;
979*4882a593Smuzhiyun			status = "disabled";
980*4882a593Smuzhiyun		};
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun		msiof2: spi@e6e00000 {
983*4882a593Smuzhiyun			compatible = "renesas,msiof-r8a7745",
984*4882a593Smuzhiyun				     "renesas,rcar-gen2-msiof";
985*4882a593Smuzhiyun			reg = <0 0xe6e00000 0 0x0064>;
986*4882a593Smuzhiyun			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
987*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 205>;
988*4882a593Smuzhiyun			dmas = <&dmac0 0x41>, <&dmac0 0x42>,
989*4882a593Smuzhiyun			       <&dmac1 0x41>, <&dmac1 0x42>;
990*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
991*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
992*4882a593Smuzhiyun			#address-cells = <1>;
993*4882a593Smuzhiyun			#size-cells = <0>;
994*4882a593Smuzhiyun			resets = <&cpg 205>;
995*4882a593Smuzhiyun			status = "disabled";
996*4882a593Smuzhiyun		};
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun		pwm0: pwm@e6e30000 {
999*4882a593Smuzhiyun			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1000*4882a593Smuzhiyun			reg = <0 0xe6e30000 0 0x8>;
1001*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 523>;
1002*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1003*4882a593Smuzhiyun			resets = <&cpg 523>;
1004*4882a593Smuzhiyun			#pwm-cells = <2>;
1005*4882a593Smuzhiyun			status = "disabled";
1006*4882a593Smuzhiyun		};
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun		pwm1: pwm@e6e31000 {
1009*4882a593Smuzhiyun			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1010*4882a593Smuzhiyun			reg = <0 0xe6e31000 0 0x8>;
1011*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 523>;
1012*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1013*4882a593Smuzhiyun			resets = <&cpg 523>;
1014*4882a593Smuzhiyun			#pwm-cells = <2>;
1015*4882a593Smuzhiyun			status = "disabled";
1016*4882a593Smuzhiyun		};
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun		pwm2: pwm@e6e32000 {
1019*4882a593Smuzhiyun			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1020*4882a593Smuzhiyun			reg = <0 0xe6e32000 0 0x8>;
1021*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 523>;
1022*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1023*4882a593Smuzhiyun			resets = <&cpg 523>;
1024*4882a593Smuzhiyun			#pwm-cells = <2>;
1025*4882a593Smuzhiyun			status = "disabled";
1026*4882a593Smuzhiyun		};
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun		pwm3: pwm@e6e33000 {
1029*4882a593Smuzhiyun			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1030*4882a593Smuzhiyun			reg = <0 0xe6e33000 0 0x8>;
1031*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 523>;
1032*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1033*4882a593Smuzhiyun			resets = <&cpg 523>;
1034*4882a593Smuzhiyun			#pwm-cells = <2>;
1035*4882a593Smuzhiyun			status = "disabled";
1036*4882a593Smuzhiyun		};
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun		pwm4: pwm@e6e34000 {
1039*4882a593Smuzhiyun			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1040*4882a593Smuzhiyun			reg = <0 0xe6e34000 0 0x8>;
1041*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 523>;
1042*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1043*4882a593Smuzhiyun			resets = <&cpg 523>;
1044*4882a593Smuzhiyun			#pwm-cells = <2>;
1045*4882a593Smuzhiyun			status = "disabled";
1046*4882a593Smuzhiyun		};
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun		pwm5: pwm@e6e35000 {
1049*4882a593Smuzhiyun			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1050*4882a593Smuzhiyun			reg = <0 0xe6e35000 0 0x8>;
1051*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 523>;
1052*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1053*4882a593Smuzhiyun			resets = <&cpg 523>;
1054*4882a593Smuzhiyun			#pwm-cells = <2>;
1055*4882a593Smuzhiyun			status = "disabled";
1056*4882a593Smuzhiyun		};
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun		pwm6: pwm@e6e36000 {
1059*4882a593Smuzhiyun			compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar";
1060*4882a593Smuzhiyun			reg = <0 0xe6e36000 0 0x8>;
1061*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 523>;
1062*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1063*4882a593Smuzhiyun			resets = <&cpg 523>;
1064*4882a593Smuzhiyun			#pwm-cells = <2>;
1065*4882a593Smuzhiyun			status = "disabled";
1066*4882a593Smuzhiyun		};
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun		can0: can@e6e80000 {
1069*4882a593Smuzhiyun			compatible = "renesas,can-r8a7745",
1070*4882a593Smuzhiyun				     "renesas,rcar-gen2-can";
1071*4882a593Smuzhiyun			reg = <0 0xe6e80000 0 0x1000>;
1072*4882a593Smuzhiyun			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1073*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 916>,
1074*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_RCAN>,
1075*4882a593Smuzhiyun				 <&can_clk>;
1076*4882a593Smuzhiyun			clock-names = "clkp1", "clkp2", "can_clk";
1077*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1078*4882a593Smuzhiyun			resets = <&cpg 916>;
1079*4882a593Smuzhiyun			status = "disabled";
1080*4882a593Smuzhiyun		};
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun		can1: can@e6e88000 {
1083*4882a593Smuzhiyun			compatible = "renesas,can-r8a7745",
1084*4882a593Smuzhiyun				     "renesas,rcar-gen2-can";
1085*4882a593Smuzhiyun			reg = <0 0xe6e88000 0 0x1000>;
1086*4882a593Smuzhiyun			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1087*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 915>,
1088*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_RCAN>,
1089*4882a593Smuzhiyun				 <&can_clk>;
1090*4882a593Smuzhiyun			clock-names = "clkp1", "clkp2", "can_clk";
1091*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1092*4882a593Smuzhiyun			resets = <&cpg 915>;
1093*4882a593Smuzhiyun			status = "disabled";
1094*4882a593Smuzhiyun		};
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun		vin0: video@e6ef0000 {
1097*4882a593Smuzhiyun			compatible = "renesas,vin-r8a7745",
1098*4882a593Smuzhiyun				     "renesas,rcar-gen2-vin";
1099*4882a593Smuzhiyun			reg = <0 0xe6ef0000 0 0x1000>;
1100*4882a593Smuzhiyun			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1101*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 811>;
1102*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1103*4882a593Smuzhiyun			resets = <&cpg 811>;
1104*4882a593Smuzhiyun			status = "disabled";
1105*4882a593Smuzhiyun		};
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun		vin1: video@e6ef1000 {
1108*4882a593Smuzhiyun			compatible = "renesas,vin-r8a7745",
1109*4882a593Smuzhiyun				     "renesas,rcar-gen2-vin";
1110*4882a593Smuzhiyun			reg = <0 0xe6ef1000 0 0x1000>;
1111*4882a593Smuzhiyun			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1112*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 810>;
1113*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1114*4882a593Smuzhiyun			resets = <&cpg 810>;
1115*4882a593Smuzhiyun			status = "disabled";
1116*4882a593Smuzhiyun		};
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun		rcar_sound: sound@ec500000 {
1119*4882a593Smuzhiyun			/*
1120*4882a593Smuzhiyun			 * #sound-dai-cells is required
1121*4882a593Smuzhiyun			 *
1122*4882a593Smuzhiyun			 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1123*4882a593Smuzhiyun			 * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1124*4882a593Smuzhiyun			 */
1125*4882a593Smuzhiyun			compatible = "renesas,rcar_sound-r8a7745",
1126*4882a593Smuzhiyun				     "renesas,rcar_sound-gen2";
1127*4882a593Smuzhiyun			reg = <0 0xec500000 0 0x1000>, /* SCU */
1128*4882a593Smuzhiyun			      <0 0xec5a0000 0 0x100>,  /* ADG */
1129*4882a593Smuzhiyun			      <0 0xec540000 0 0x1000>, /* SSIU */
1130*4882a593Smuzhiyun			      <0 0xec541000 0 0x280>,  /* SSI */
1131*4882a593Smuzhiyun			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
1132*4882a593Smuzhiyun			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 1005>,
1135*4882a593Smuzhiyun				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1136*4882a593Smuzhiyun				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1137*4882a593Smuzhiyun				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1138*4882a593Smuzhiyun				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1139*4882a593Smuzhiyun				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1140*4882a593Smuzhiyun				 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
1141*4882a593Smuzhiyun				 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
1142*4882a593Smuzhiyun				 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
1143*4882a593Smuzhiyun				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1144*4882a593Smuzhiyun				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
1145*4882a593Smuzhiyun				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1146*4882a593Smuzhiyun				 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
1147*4882a593Smuzhiyun				 <&cpg CPG_CORE R8A7745_CLK_M2>;
1148*4882a593Smuzhiyun			clock-names = "ssi-all",
1149*4882a593Smuzhiyun				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1150*4882a593Smuzhiyun				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1151*4882a593Smuzhiyun				      "ssi.1", "ssi.0",
1152*4882a593Smuzhiyun				      "src.6", "src.5", "src.4", "src.3",
1153*4882a593Smuzhiyun				      "src.2", "src.1",
1154*4882a593Smuzhiyun				      "ctu.0", "ctu.1",
1155*4882a593Smuzhiyun				      "mix.0", "mix.1",
1156*4882a593Smuzhiyun				      "dvc.0", "dvc.1",
1157*4882a593Smuzhiyun				      "clk_a", "clk_b", "clk_c", "clk_i";
1158*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1159*4882a593Smuzhiyun			resets = <&cpg 1005>,
1160*4882a593Smuzhiyun				 <&cpg 1006>, <&cpg 1007>, <&cpg 1008>,
1161*4882a593Smuzhiyun				 <&cpg 1009>, <&cpg 1010>, <&cpg 1011>,
1162*4882a593Smuzhiyun				 <&cpg 1012>, <&cpg 1013>, <&cpg 1014>,
1163*4882a593Smuzhiyun				 <&cpg 1015>;
1164*4882a593Smuzhiyun			reset-names = "ssi-all",
1165*4882a593Smuzhiyun				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1166*4882a593Smuzhiyun				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1167*4882a593Smuzhiyun				      "ssi.1", "ssi.0";
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun			status = "disabled";
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun			rcar_sound,dvc {
1172*4882a593Smuzhiyun				dvc0: dvc-0 {
1173*4882a593Smuzhiyun					dmas = <&audma0 0xbc>;
1174*4882a593Smuzhiyun					dma-names = "tx";
1175*4882a593Smuzhiyun				};
1176*4882a593Smuzhiyun				dvc1: dvc-1 {
1177*4882a593Smuzhiyun					dmas = <&audma0 0xbe>;
1178*4882a593Smuzhiyun					dma-names = "tx";
1179*4882a593Smuzhiyun				};
1180*4882a593Smuzhiyun			};
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun			rcar_sound,mix {
1183*4882a593Smuzhiyun				mix0: mix-0 { };
1184*4882a593Smuzhiyun				mix1: mix-1 { };
1185*4882a593Smuzhiyun			};
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun			rcar_sound,ctu {
1188*4882a593Smuzhiyun				ctu00: ctu-0 { };
1189*4882a593Smuzhiyun				ctu01: ctu-1 { };
1190*4882a593Smuzhiyun				ctu02: ctu-2 { };
1191*4882a593Smuzhiyun				ctu03: ctu-3 { };
1192*4882a593Smuzhiyun				ctu10: ctu-4 { };
1193*4882a593Smuzhiyun				ctu11: ctu-5 { };
1194*4882a593Smuzhiyun				ctu12: ctu-6 { };
1195*4882a593Smuzhiyun				ctu13: ctu-7 { };
1196*4882a593Smuzhiyun			};
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun			rcar_sound,src {
1199*4882a593Smuzhiyun				src-0 {
1200*4882a593Smuzhiyun					status = "disabled";
1201*4882a593Smuzhiyun				};
1202*4882a593Smuzhiyun				src1: src-1 {
1203*4882a593Smuzhiyun					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1204*4882a593Smuzhiyun					dmas = <&audma0 0x87>, <&audma0 0x9c>;
1205*4882a593Smuzhiyun					dma-names = "rx", "tx";
1206*4882a593Smuzhiyun				};
1207*4882a593Smuzhiyun				src2: src-2 {
1208*4882a593Smuzhiyun					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1209*4882a593Smuzhiyun					dmas = <&audma0 0x89>, <&audma0 0x9e>;
1210*4882a593Smuzhiyun					dma-names = "rx", "tx";
1211*4882a593Smuzhiyun				};
1212*4882a593Smuzhiyun				src3: src-3 {
1213*4882a593Smuzhiyun					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1214*4882a593Smuzhiyun					dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1215*4882a593Smuzhiyun					dma-names = "rx", "tx";
1216*4882a593Smuzhiyun				};
1217*4882a593Smuzhiyun				src4: src-4 {
1218*4882a593Smuzhiyun					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1219*4882a593Smuzhiyun					dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1220*4882a593Smuzhiyun					dma-names = "rx", "tx";
1221*4882a593Smuzhiyun				};
1222*4882a593Smuzhiyun				src5: src-5 {
1223*4882a593Smuzhiyun					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1224*4882a593Smuzhiyun					dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1225*4882a593Smuzhiyun					dma-names = "rx", "tx";
1226*4882a593Smuzhiyun				};
1227*4882a593Smuzhiyun				src6: src-6 {
1228*4882a593Smuzhiyun					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1229*4882a593Smuzhiyun					dmas = <&audma0 0x91>, <&audma0 0xb4>;
1230*4882a593Smuzhiyun					dma-names = "rx", "tx";
1231*4882a593Smuzhiyun				};
1232*4882a593Smuzhiyun			};
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun			rcar_sound,ssi {
1235*4882a593Smuzhiyun				ssi0: ssi-0 {
1236*4882a593Smuzhiyun					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1237*4882a593Smuzhiyun					dmas = <&audma0 0x01>, <&audma0 0x02>,
1238*4882a593Smuzhiyun					       <&audma0 0x15>, <&audma0 0x16>;
1239*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1240*4882a593Smuzhiyun				};
1241*4882a593Smuzhiyun				ssi1: ssi-1 {
1242*4882a593Smuzhiyun					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1243*4882a593Smuzhiyun					dmas = <&audma0 0x03>, <&audma0 0x04>,
1244*4882a593Smuzhiyun					       <&audma0 0x49>, <&audma0 0x4a>;
1245*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1246*4882a593Smuzhiyun				};
1247*4882a593Smuzhiyun				ssi2: ssi-2 {
1248*4882a593Smuzhiyun					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1249*4882a593Smuzhiyun					dmas = <&audma0 0x05>, <&audma0 0x06>,
1250*4882a593Smuzhiyun					       <&audma0 0x63>, <&audma0 0x64>;
1251*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1252*4882a593Smuzhiyun				};
1253*4882a593Smuzhiyun				ssi3: ssi-3 {
1254*4882a593Smuzhiyun					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1255*4882a593Smuzhiyun					dmas = <&audma0 0x07>, <&audma0 0x08>,
1256*4882a593Smuzhiyun					       <&audma0 0x6f>, <&audma0 0x70>;
1257*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1258*4882a593Smuzhiyun				};
1259*4882a593Smuzhiyun				ssi4: ssi-4 {
1260*4882a593Smuzhiyun					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1261*4882a593Smuzhiyun					dmas = <&audma0 0x09>, <&audma0 0x0a>,
1262*4882a593Smuzhiyun					       <&audma0 0x71>, <&audma0 0x72>;
1263*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1264*4882a593Smuzhiyun				};
1265*4882a593Smuzhiyun				ssi5: ssi-5 {
1266*4882a593Smuzhiyun					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1267*4882a593Smuzhiyun					dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1268*4882a593Smuzhiyun					       <&audma0 0x73>, <&audma0 0x74>;
1269*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1270*4882a593Smuzhiyun				};
1271*4882a593Smuzhiyun				ssi6: ssi-6 {
1272*4882a593Smuzhiyun					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1273*4882a593Smuzhiyun					dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1274*4882a593Smuzhiyun					       <&audma0 0x75>, <&audma0 0x76>;
1275*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1276*4882a593Smuzhiyun				};
1277*4882a593Smuzhiyun				ssi7: ssi-7 {
1278*4882a593Smuzhiyun					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1279*4882a593Smuzhiyun					dmas = <&audma0 0x0f>, <&audma0 0x10>,
1280*4882a593Smuzhiyun					       <&audma0 0x79>, <&audma0 0x7a>;
1281*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1282*4882a593Smuzhiyun				};
1283*4882a593Smuzhiyun				ssi8: ssi-8 {
1284*4882a593Smuzhiyun					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1285*4882a593Smuzhiyun					dmas = <&audma0 0x11>, <&audma0 0x12>,
1286*4882a593Smuzhiyun					       <&audma0 0x7b>, <&audma0 0x7c>;
1287*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1288*4882a593Smuzhiyun				};
1289*4882a593Smuzhiyun				ssi9: ssi-9 {
1290*4882a593Smuzhiyun					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1291*4882a593Smuzhiyun					dmas = <&audma0 0x13>, <&audma0 0x14>,
1292*4882a593Smuzhiyun					       <&audma0 0x7d>, <&audma0 0x7e>;
1293*4882a593Smuzhiyun					dma-names = "rx", "tx", "rxu", "txu";
1294*4882a593Smuzhiyun				};
1295*4882a593Smuzhiyun			};
1296*4882a593Smuzhiyun		};
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun		audma0: dma-controller@ec700000 {
1299*4882a593Smuzhiyun			compatible = "renesas,dmac-r8a7745",
1300*4882a593Smuzhiyun				     "renesas,rcar-dmac";
1301*4882a593Smuzhiyun			reg = <0 0xec700000 0 0x10000>;
1302*4882a593Smuzhiyun			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
1303*4882a593Smuzhiyun				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1304*4882a593Smuzhiyun				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1305*4882a593Smuzhiyun				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1306*4882a593Smuzhiyun				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1307*4882a593Smuzhiyun				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1308*4882a593Smuzhiyun				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1309*4882a593Smuzhiyun				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1310*4882a593Smuzhiyun				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1311*4882a593Smuzhiyun				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1312*4882a593Smuzhiyun				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1313*4882a593Smuzhiyun				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1314*4882a593Smuzhiyun				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1315*4882a593Smuzhiyun				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1316*4882a593Smuzhiyun			interrupt-names = "error",
1317*4882a593Smuzhiyun					  "ch0", "ch1", "ch2", "ch3",
1318*4882a593Smuzhiyun					  "ch4", "ch5", "ch6", "ch7",
1319*4882a593Smuzhiyun					  "ch8", "ch9", "ch10", "ch11",
1320*4882a593Smuzhiyun					  "ch12";
1321*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 502>;
1322*4882a593Smuzhiyun			clock-names = "fck";
1323*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1324*4882a593Smuzhiyun			resets = <&cpg 502>;
1325*4882a593Smuzhiyun			#dma-cells = <1>;
1326*4882a593Smuzhiyun			dma-channels = <13>;
1327*4882a593Smuzhiyun		};
1328*4882a593Smuzhiyun
1329*4882a593Smuzhiyun		pci0: pci@ee090000 {
1330*4882a593Smuzhiyun			compatible = "renesas,pci-r8a7745",
1331*4882a593Smuzhiyun				     "renesas,pci-rcar-gen2";
1332*4882a593Smuzhiyun			device_type = "pci";
1333*4882a593Smuzhiyun			reg = <0 0xee090000 0 0xc00>,
1334*4882a593Smuzhiyun			      <0 0xee080000 0 0x1100>;
1335*4882a593Smuzhiyun			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1336*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 703>;
1337*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1338*4882a593Smuzhiyun			resets = <&cpg 703>;
1339*4882a593Smuzhiyun			status = "disabled";
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun			bus-range = <0 0>;
1342*4882a593Smuzhiyun			#address-cells = <3>;
1343*4882a593Smuzhiyun			#size-cells = <2>;
1344*4882a593Smuzhiyun			#interrupt-cells = <1>;
1345*4882a593Smuzhiyun			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1346*4882a593Smuzhiyun			interrupt-map-mask = <0xf800 0 0 0x7>;
1347*4882a593Smuzhiyun			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1348*4882a593Smuzhiyun					<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1349*4882a593Smuzhiyun					<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun			usb@1,0 {
1352*4882a593Smuzhiyun				reg = <0x800 0 0 0 0>;
1353*4882a593Smuzhiyun				phys = <&usb0 0>;
1354*4882a593Smuzhiyun				phy-names = "usb";
1355*4882a593Smuzhiyun			};
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun			usb@2,0 {
1358*4882a593Smuzhiyun				reg = <0x1000 0 0 0 0>;
1359*4882a593Smuzhiyun				phys = <&usb0 0>;
1360*4882a593Smuzhiyun				phy-names = "usb";
1361*4882a593Smuzhiyun			};
1362*4882a593Smuzhiyun		};
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun		pci1: pci@ee0d0000 {
1365*4882a593Smuzhiyun			compatible = "renesas,pci-r8a7745",
1366*4882a593Smuzhiyun				     "renesas,pci-rcar-gen2";
1367*4882a593Smuzhiyun			device_type = "pci";
1368*4882a593Smuzhiyun			reg = <0 0xee0d0000 0 0xc00>,
1369*4882a593Smuzhiyun			      <0 0xee0c0000 0 0x1100>;
1370*4882a593Smuzhiyun			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1371*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 703>;
1372*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1373*4882a593Smuzhiyun			resets = <&cpg 703>;
1374*4882a593Smuzhiyun			status = "disabled";
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun			bus-range = <1 1>;
1377*4882a593Smuzhiyun			#address-cells = <3>;
1378*4882a593Smuzhiyun			#size-cells = <2>;
1379*4882a593Smuzhiyun			#interrupt-cells = <1>;
1380*4882a593Smuzhiyun			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1381*4882a593Smuzhiyun			interrupt-map-mask = <0xf800 0 0 0x7>;
1382*4882a593Smuzhiyun			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1383*4882a593Smuzhiyun					<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1384*4882a593Smuzhiyun					<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun			usb@1,0 {
1387*4882a593Smuzhiyun				reg = <0x10800 0 0 0 0>;
1388*4882a593Smuzhiyun				phys = <&usb2 0>;
1389*4882a593Smuzhiyun				phy-names = "usb";
1390*4882a593Smuzhiyun			};
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun			usb@2,0 {
1393*4882a593Smuzhiyun				reg = <0x11000 0 0 0 0>;
1394*4882a593Smuzhiyun				phys = <&usb2 0>;
1395*4882a593Smuzhiyun				phy-names = "usb";
1396*4882a593Smuzhiyun			};
1397*4882a593Smuzhiyun		};
1398*4882a593Smuzhiyun
1399*4882a593Smuzhiyun		sdhi0: mmc@ee100000 {
1400*4882a593Smuzhiyun			compatible = "renesas,sdhi-r8a7745",
1401*4882a593Smuzhiyun				     "renesas,rcar-gen2-sdhi";
1402*4882a593Smuzhiyun			reg = <0 0xee100000 0 0x328>;
1403*4882a593Smuzhiyun			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1404*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 314>;
1405*4882a593Smuzhiyun			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1406*4882a593Smuzhiyun			       <&dmac1 0xcd>, <&dmac1 0xce>;
1407*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
1408*4882a593Smuzhiyun			max-frequency = <195000000>;
1409*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1410*4882a593Smuzhiyun			resets = <&cpg 314>;
1411*4882a593Smuzhiyun			status = "disabled";
1412*4882a593Smuzhiyun		};
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun		sdhi1: mmc@ee140000 {
1415*4882a593Smuzhiyun			compatible = "renesas,sdhi-r8a7745",
1416*4882a593Smuzhiyun				     "renesas,rcar-gen2-sdhi";
1417*4882a593Smuzhiyun			reg = <0 0xee140000 0 0x100>;
1418*4882a593Smuzhiyun			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1419*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 312>;
1420*4882a593Smuzhiyun			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1421*4882a593Smuzhiyun			       <&dmac1 0xc1>, <&dmac1 0xc2>;
1422*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
1423*4882a593Smuzhiyun			max-frequency = <97500000>;
1424*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1425*4882a593Smuzhiyun			resets = <&cpg 312>;
1426*4882a593Smuzhiyun			status = "disabled";
1427*4882a593Smuzhiyun		};
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun		sdhi2: mmc@ee160000 {
1430*4882a593Smuzhiyun			compatible = "renesas,sdhi-r8a7745",
1431*4882a593Smuzhiyun				     "renesas,rcar-gen2-sdhi";
1432*4882a593Smuzhiyun			reg = <0 0xee160000 0 0x100>;
1433*4882a593Smuzhiyun			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1434*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 311>;
1435*4882a593Smuzhiyun			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1436*4882a593Smuzhiyun			       <&dmac1 0xd3>, <&dmac1 0xd4>;
1437*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
1438*4882a593Smuzhiyun			max-frequency = <97500000>;
1439*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1440*4882a593Smuzhiyun			resets = <&cpg 311>;
1441*4882a593Smuzhiyun			status = "disabled";
1442*4882a593Smuzhiyun		};
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun		mmcif0: mmc@ee200000 {
1445*4882a593Smuzhiyun			compatible = "renesas,mmcif-r8a7745",
1446*4882a593Smuzhiyun				     "renesas,sh-mmcif";
1447*4882a593Smuzhiyun			reg = <0 0xee200000 0 0x80>;
1448*4882a593Smuzhiyun			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1449*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 315>;
1450*4882a593Smuzhiyun			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1451*4882a593Smuzhiyun			       <&dmac1 0xd1>, <&dmac1 0xd2>;
1452*4882a593Smuzhiyun			dma-names = "tx", "rx", "tx", "rx";
1453*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1454*4882a593Smuzhiyun			resets = <&cpg 315>;
1455*4882a593Smuzhiyun			reg-io-width = <4>;
1456*4882a593Smuzhiyun			max-frequency = <97500000>;
1457*4882a593Smuzhiyun			status = "disabled";
1458*4882a593Smuzhiyun		};
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun		ether: ethernet@ee700000 {
1461*4882a593Smuzhiyun			compatible = "renesas,ether-r8a7745",
1462*4882a593Smuzhiyun				     "renesas,rcar-gen2-ether";
1463*4882a593Smuzhiyun			reg = <0 0xee700000 0 0x400>;
1464*4882a593Smuzhiyun			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1465*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 813>;
1466*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1467*4882a593Smuzhiyun			resets = <&cpg 813>;
1468*4882a593Smuzhiyun			phy-mode = "rmii";
1469*4882a593Smuzhiyun			#address-cells = <1>;
1470*4882a593Smuzhiyun			#size-cells = <0>;
1471*4882a593Smuzhiyun			status = "disabled";
1472*4882a593Smuzhiyun		};
1473*4882a593Smuzhiyun
1474*4882a593Smuzhiyun		gic: interrupt-controller@f1001000 {
1475*4882a593Smuzhiyun			compatible = "arm,gic-400";
1476*4882a593Smuzhiyun			#interrupt-cells = <3>;
1477*4882a593Smuzhiyun			#address-cells = <0>;
1478*4882a593Smuzhiyun			interrupt-controller;
1479*4882a593Smuzhiyun			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
1480*4882a593Smuzhiyun			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
1481*4882a593Smuzhiyun			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1482*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 408>;
1483*4882a593Smuzhiyun			clock-names = "clk";
1484*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1485*4882a593Smuzhiyun			resets = <&cpg 408>;
1486*4882a593Smuzhiyun		};
1487*4882a593Smuzhiyun
1488*4882a593Smuzhiyun		vsp@fe928000 {
1489*4882a593Smuzhiyun			compatible = "renesas,vsp1";
1490*4882a593Smuzhiyun			reg = <0 0xfe928000 0 0x8000>;
1491*4882a593Smuzhiyun			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
1492*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 131>;
1493*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1494*4882a593Smuzhiyun			resets = <&cpg 131>;
1495*4882a593Smuzhiyun		};
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun		vsp@fe930000 {
1498*4882a593Smuzhiyun			compatible = "renesas,vsp1";
1499*4882a593Smuzhiyun			reg = <0 0xfe930000 0 0x8000>;
1500*4882a593Smuzhiyun			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1501*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 128>;
1502*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1503*4882a593Smuzhiyun			resets = <&cpg 128>;
1504*4882a593Smuzhiyun		};
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun		du: display@feb00000 {
1507*4882a593Smuzhiyun			compatible = "renesas,du-r8a7745";
1508*4882a593Smuzhiyun			reg = <0 0xfeb00000 0 0x40000>;
1509*4882a593Smuzhiyun			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1510*4882a593Smuzhiyun				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1511*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1512*4882a593Smuzhiyun			clock-names = "du.0", "du.1";
1513*4882a593Smuzhiyun			resets = <&cpg 724>;
1514*4882a593Smuzhiyun			reset-names = "du.0";
1515*4882a593Smuzhiyun			status = "disabled";
1516*4882a593Smuzhiyun
1517*4882a593Smuzhiyun			ports {
1518*4882a593Smuzhiyun				#address-cells = <1>;
1519*4882a593Smuzhiyun				#size-cells = <0>;
1520*4882a593Smuzhiyun
1521*4882a593Smuzhiyun				port@0 {
1522*4882a593Smuzhiyun					reg = <0>;
1523*4882a593Smuzhiyun					du_out_rgb0: endpoint {
1524*4882a593Smuzhiyun					};
1525*4882a593Smuzhiyun				};
1526*4882a593Smuzhiyun				port@1 {
1527*4882a593Smuzhiyun					reg = <1>;
1528*4882a593Smuzhiyun					du_out_rgb1: endpoint {
1529*4882a593Smuzhiyun					};
1530*4882a593Smuzhiyun				};
1531*4882a593Smuzhiyun			};
1532*4882a593Smuzhiyun		};
1533*4882a593Smuzhiyun
1534*4882a593Smuzhiyun		prr: chipid@ff000044 {
1535*4882a593Smuzhiyun			compatible = "renesas,prr";
1536*4882a593Smuzhiyun			reg = <0 0xff000044 0 4>;
1537*4882a593Smuzhiyun		};
1538*4882a593Smuzhiyun
1539*4882a593Smuzhiyun		cmt0: timer@ffca0000 {
1540*4882a593Smuzhiyun			compatible = "renesas,r8a7745-cmt0",
1541*4882a593Smuzhiyun				     "renesas,rcar-gen2-cmt0";
1542*4882a593Smuzhiyun			reg = <0 0xffca0000 0 0x1004>;
1543*4882a593Smuzhiyun			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1544*4882a593Smuzhiyun				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1545*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 124>;
1546*4882a593Smuzhiyun			clock-names = "fck";
1547*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1548*4882a593Smuzhiyun			resets = <&cpg 124>;
1549*4882a593Smuzhiyun			status = "disabled";
1550*4882a593Smuzhiyun		};
1551*4882a593Smuzhiyun
1552*4882a593Smuzhiyun		cmt1: timer@e6130000 {
1553*4882a593Smuzhiyun			compatible = "renesas,r8a7745-cmt1",
1554*4882a593Smuzhiyun				     "renesas,rcar-gen2-cmt1";
1555*4882a593Smuzhiyun			reg = <0 0xe6130000 0 0x1004>;
1556*4882a593Smuzhiyun			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1557*4882a593Smuzhiyun				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1558*4882a593Smuzhiyun				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1559*4882a593Smuzhiyun				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1560*4882a593Smuzhiyun				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1561*4882a593Smuzhiyun				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1562*4882a593Smuzhiyun				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1563*4882a593Smuzhiyun				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1564*4882a593Smuzhiyun			clocks = <&cpg CPG_MOD 329>;
1565*4882a593Smuzhiyun			clock-names = "fck";
1566*4882a593Smuzhiyun			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
1567*4882a593Smuzhiyun			resets = <&cpg 329>;
1568*4882a593Smuzhiyun			status = "disabled";
1569*4882a593Smuzhiyun		};
1570*4882a593Smuzhiyun	};
1571*4882a593Smuzhiyun
1572*4882a593Smuzhiyun	timer {
1573*4882a593Smuzhiyun		compatible = "arm,armv7-timer";
1574*4882a593Smuzhiyun		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1575*4882a593Smuzhiyun				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1576*4882a593Smuzhiyun				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1577*4882a593Smuzhiyun				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1578*4882a593Smuzhiyun	};
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun	/* External USB clock - can be overridden by the board */
1581*4882a593Smuzhiyun	usb_extal_clk: usb_extal {
1582*4882a593Smuzhiyun		compatible = "fixed-clock";
1583*4882a593Smuzhiyun		#clock-cells = <0>;
1584*4882a593Smuzhiyun		clock-frequency = <48000000>;
1585*4882a593Smuzhiyun	};
1586*4882a593Smuzhiyun};
1587