Lines Matching +full:0 +full:xe6060000
15 PINMUX_RESERVED = 0,
439 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
473 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
474 0, 0,
475 0, 0,
476 0, 0,
477 0, 0,
478 0, 0,
479 0, 0,
507 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
541 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
575 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
609 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
643 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
644 0, 0,
645 0, 0,
667 0, 0,
677 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
678 0, 0,
679 0, 0,
680 0, 0,
681 0, 0,
682 0, 0,
683 0, 0,
712 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
716 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
718 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
738 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
740 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
744 0, 0, 0,
748 0, 0, 0,
751 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
754 0, 0, 0,
757 0, 0, 0, }
759 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
762 0, 0, 0, 0,
766 0, 0, 0,
770 0, 0, 0,
772 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
774 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
776 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
782 0, 0, 0,
786 0, 0, 0,
790 0, 0, 0,
794 0, 0, 0,
803 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
807 0, 0,
818 0, 0, 0, 0,
820 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
832 0, 0, 0,
834 0, 0, 0, 0,
836 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
838 0, 0, 0, 0,
846 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
848 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
854 0, 0, 0,
856 0, 0,
862 0, 0,
866 0, 0,
870 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
872 0, 0, 0, 0,
878 0, 0, 0,
880 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
882 0, 0,
886 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
888 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
892 0, 0,
896 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
906 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
908 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
910 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
916 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
922 0, 0, 0, 0,
928 0, 0, 0,
930 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
932 0, 0, 0, 0,
934 0, 0, 0, 0,
936 0, 0, }
938 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
944 0, 0, 0,
946 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
948 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
950 0, 0,
960 0, 0, 0,
962 0, 0, 0, 0,
964 0, 0, 0, 0,
968 0, 0, 0,
970 0, 0,
976 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
978 0, 0, 0, 0,
980 0, 0, 0, 0,
982 0, 0, 0, 0, }
984 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
985 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
986 0, 0,
987 0, 0,
988 0, 0,
989 0, 0,
990 0, 0,
991 0, 0,
1019 { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
1020 { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
1021 { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
1022 { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
1023 { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
1024 { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
1025 0, 0,
1026 0, 0,
1027 0, 0,
1028 0, 0,
1029 0, 0,
1030 0, 0,
1062 { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
1063 { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
1064 0, 0, 0, 0,
1065 0, 0, GP_1_25_DATA, GP_1_24_DATA,
1073 { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
1074 { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
1075 { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
1076 { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
1077 { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
1078 { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
1079 0, 0, 0, 0,
1080 0, 0, GP_7_25_DATA, GP_7_24_DATA,
1094 .unlock_reg = 0xe6060000, /* PMMR */