| 5a91c439 | 14-May-2021 |
Pali Rohár <pali@kernel.org> |
fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate is always 25 MHz. This is incorrect, because the xtal cl
fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate is always 25 MHz. This is incorrect, because the xtal clock can also run at 40 MHz (this is board specific).
The frequency of the xtal clock is determined by a value on a strapping pin during SOC reset. The code to determine this frequency is already in A3K's comphy driver.
Move the get_ref_clk() function from the comphy driver to a separate file and use it for UART parent clock rate determination.
Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
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| 2e1dba44 | 02-Aug-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada: fix TRNG return SMC handling
Use single 64b register for the return value instead of two 32b. Report an error if caller requested larger than than 64b random number in a single
plat/marvell/armada: fix TRNG return SMC handling
Use single 64b register for the return value instead of two 32b. Report an error if caller requested larger than than 64b random number in a single SMC call.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Ib8756cd3c0808b78c359f90c6f6913f7d16ac360 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/33280 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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| b5a06637 | 28-Feb-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada: postpone MSS CPU startup to BL31 stage
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes s
plat/marvell/armada: postpone MSS CPU startup to BL31 stage
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations.
Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
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| 81c2a044 | 03-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In intr
drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In introduced misc_dfx driver some registers are white-listed so non-secure software can still access them.
This will allow non-secure word drivers access some white-listed registers related to e.g.: Sample at reset, efuses, SoC type and revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25055 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| 0cedca63 | 02-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: thermal: use dedicated function for thermal SiPs
Since more drivers which uses dfx register set need to be handled with use of SiP services, use dedicated and more meaningful name
drivers: marvell: thermal: use dedicated function for thermal SiPs
Since more drivers which uses dfx register set need to be handled with use of SiP services, use dedicated and more meaningful name for thermal SiP services.
Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25054 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| ad416958 | 18-Dec-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), acce
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), accessing thermal registers which are part of dfx register set, will not be possible from lower exception levels. Due to above expose thermal driver as a SiP service. This will allow Linux and U-Boot thermal driver to initialise and perform various operations on thermal sensor.
The thermal sensor driver is based on Linux drivers/thermal/armada_thermal.c.
Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/20581 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
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