1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <drivers/marvell/cache_llc.h> 11 #include <drivers/marvell/mochi/ap_setup.h> 12 #include <drivers/rambus/trng_ip_76.h> 13 #include <lib/smccc.h> 14 15 #include <marvell_plat_priv.h> 16 #include <plat_marvell.h> 17 18 #include "comphy/phy-comphy-cp110.h" 19 #include "secure_dfx_access/dfx.h" 20 #include "ddr_phy_access.h" 21 #include <stdbool.h> 22 23 /* #define DEBUG_COMPHY */ 24 #ifdef DEBUG_COMPHY 25 #define debug(format...) NOTICE(format) 26 #else 27 #define debug(format, arg...) 28 #endif 29 30 /* Comphy related FID's */ 31 #define MV_SIP_COMPHY_POWER_ON 0x82000001 32 #define MV_SIP_COMPHY_POWER_OFF 0x82000002 33 #define MV_SIP_COMPHY_PLL_LOCK 0x82000003 34 #define MV_SIP_COMPHY_XFI_TRAIN 0x82000004 35 #define MV_SIP_COMPHY_DIG_RESET 0x82000005 36 37 /* Miscellaneous FID's' */ 38 #define MV_SIP_DRAM_SIZE 0x82000010 39 #define MV_SIP_LLC_ENABLE 0x82000011 40 #define MV_SIP_PMU_IRQ_ENABLE 0x82000012 41 #define MV_SIP_PMU_IRQ_DISABLE 0x82000013 42 #define MV_SIP_DFX 0x82000014 43 #define MV_SIP_DDR_PHY_WRITE 0x82000015 44 #define MV_SIP_DDR_PHY_READ 0x82000016 45 46 /* TRNG */ 47 #define MV_SIP_RNG_64 0xC200FF11 48 49 #define MAX_LANE_NR 6 50 #define MVEBU_COMPHY_OFFSET 0x441000 51 #define MVEBU_CP_BASE_MASK (~0xffffff) 52 53 /* Common PHY register */ 54 #define COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS 0x120a2c 55 56 /* This macro is used to identify COMPHY related calls from SMC function ID */ 57 #define is_comphy_fid(fid) \ 58 ((fid) >= MV_SIP_COMPHY_POWER_ON && (fid) <= MV_SIP_COMPHY_DIG_RESET) 59 60 _Bool is_cp_range_valid(u_register_t *addr) 61 { 62 int cp_nr; 63 64 *addr &= MVEBU_CP_BASE_MASK; 65 for (cp_nr = 0; cp_nr < CP_NUM; cp_nr++) { 66 if (*addr == MVEBU_CP_REGS_BASE(cp_nr)) 67 return true; 68 } 69 70 return false; 71 } 72 73 uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, 74 u_register_t x1, 75 u_register_t x2, 76 u_register_t x3, 77 u_register_t x4, 78 void *cookie, 79 void *handle, 80 u_register_t flags) 81 { 82 u_register_t ret, read, x5 = x1; 83 uint32_t w2[2] = {0, 0}; 84 int i; 85 86 debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 87 __func__, smc_fid, x1, x2, x3); 88 89 if (is_comphy_fid(smc_fid)) { 90 /* validate address passed via x1 */ 91 if (!is_cp_range_valid(&x1)) { 92 ERROR("%s: Wrong smc (0x%x) address: %lx\n", 93 __func__, smc_fid, x1); 94 SMC_RET1(handle, SMC_UNK); 95 } 96 97 x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS; 98 x1 += MVEBU_COMPHY_OFFSET; 99 100 if (x2 >= MAX_LANE_NR) { 101 ERROR("%s: Wrong smc (0x%x) lane nr: %lx\n", 102 __func__, smc_fid, x2); 103 SMC_RET1(handle, SMC_UNK); 104 } 105 } 106 107 switch (smc_fid) { 108 109 /* Comphy related FID's */ 110 case MV_SIP_COMPHY_POWER_ON: 111 /* x1: comphy_base, x2: comphy_index, x3: comphy_mode */ 112 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); 113 SMC_RET1(handle, ret); 114 case MV_SIP_COMPHY_POWER_OFF: 115 /* x1: comphy_base, x2: comphy_index */ 116 ret = mvebu_cp110_comphy_power_off(x1, x2, x3); 117 SMC_RET1(handle, ret); 118 case MV_SIP_COMPHY_PLL_LOCK: 119 /* x1: comphy_base, x2: comphy_index */ 120 ret = mvebu_cp110_comphy_is_pll_locked(x1, x2); 121 SMC_RET1(handle, ret); 122 case MV_SIP_COMPHY_XFI_TRAIN: 123 /* x1: comphy_base, x2: comphy_index */ 124 ret = mvebu_cp110_comphy_xfi_rx_training(x1, x2); 125 SMC_RET1(handle, ret); 126 case MV_SIP_COMPHY_DIG_RESET: 127 /* x1: comphy_base, x2: comphy_index, x3: mode, x4: command */ 128 ret = mvebu_cp110_comphy_digital_reset(x1, x2, x3, x4); 129 SMC_RET1(handle, ret); 130 131 /* Miscellaneous FID's' */ 132 case MV_SIP_DRAM_SIZE: 133 ret = mvebu_get_dram_size(MVEBU_REGS_BASE); 134 SMC_RET1(handle, ret); 135 case MV_SIP_LLC_ENABLE: 136 for (i = 0; i < ap_get_count(); i++) 137 llc_runtime_enable(i); 138 139 SMC_RET1(handle, 0); 140 #ifdef MVEBU_PMU_IRQ_WA 141 case MV_SIP_PMU_IRQ_ENABLE: 142 mvebu_pmu_interrupt_enable(); 143 SMC_RET1(handle, 0); 144 case MV_SIP_PMU_IRQ_DISABLE: 145 mvebu_pmu_interrupt_disable(); 146 SMC_RET1(handle, 0); 147 #endif 148 case MV_SIP_DFX: 149 if (x1 >= MV_SIP_DFX_THERMAL_INIT && 150 x1 <= MV_SIP_DFX_THERMAL_SEL_CHANNEL) { 151 ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3); 152 SMC_RET2(handle, ret, read); 153 } 154 if (x1 >= MV_SIP_DFX_SREAD && x1 <= MV_SIP_DFX_SWRITE) { 155 ret = mvebu_dfx_misc_handle(x1, &read, x2, x3); 156 SMC_RET2(handle, ret, read); 157 } 158 159 SMC_RET1(handle, SMC_UNK); 160 case MV_SIP_DDR_PHY_WRITE: 161 ret = mvebu_ddr_phy_write(x1, x2); 162 SMC_RET1(handle, ret); 163 case MV_SIP_DDR_PHY_READ: 164 read = 0; 165 ret = mvebu_ddr_phy_read(x1, (uint16_t *)&read); 166 SMC_RET2(handle, ret, read); 167 case MV_SIP_RNG_64: 168 ret = eip76_rng_get_random((uint8_t *)&w2, 4 * (x1 % 2 + 1)); 169 SMC_RET3(handle, ret, w2[0], w2[1]); 170 default: 171 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 172 SMC_RET1(handle, SMC_UNK); 173 } 174 } 175 176 /* Define a runtime service descriptor for fast SMC calls */ 177 DECLARE_RT_SVC( 178 marvell_sip_svc, 179 OEN_SIP_START, 180 OEN_SIP_END, 181 SMC_TYPE_FAST, 182 NULL, 183 mrvl_sip_smc_handler 184 ); 185