1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <drivers/marvell/cache_llc.h> 11 #include <drivers/marvell/mochi/ap_setup.h> 12 #include <lib/smccc.h> 13 14 #include <marvell_plat_priv.h> 15 #include <plat_marvell.h> 16 17 #include "comphy/phy-comphy-cp110.h" 18 #include "secure_dfx_access/dfx.h" 19 #include "ddr_phy_access.h" 20 #include <stdbool.h> 21 22 /* #define DEBUG_COMPHY */ 23 #ifdef DEBUG_COMPHY 24 #define debug(format...) NOTICE(format) 25 #else 26 #define debug(format, arg...) 27 #endif 28 29 /* Comphy related FID's */ 30 #define MV_SIP_COMPHY_POWER_ON 0x82000001 31 #define MV_SIP_COMPHY_POWER_OFF 0x82000002 32 #define MV_SIP_COMPHY_PLL_LOCK 0x82000003 33 #define MV_SIP_COMPHY_XFI_TRAIN 0x82000004 34 #define MV_SIP_COMPHY_DIG_RESET 0x82000005 35 36 /* Miscellaneous FID's' */ 37 #define MV_SIP_DRAM_SIZE 0x82000010 38 #define MV_SIP_LLC_ENABLE 0x82000011 39 #define MV_SIP_PMU_IRQ_ENABLE 0x82000012 40 #define MV_SIP_PMU_IRQ_DISABLE 0x82000013 41 #define MV_SIP_DFX 0x82000014 42 #define MV_SIP_DDR_PHY_WRITE 0x82000015 43 #define MV_SIP_DDR_PHY_READ 0x82000016 44 45 #define MAX_LANE_NR 6 46 #define MVEBU_COMPHY_OFFSET 0x441000 47 #define MVEBU_CP_BASE_MASK (~0xffffff) 48 49 /* Common PHY register */ 50 #define COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS 0x120a2c 51 52 /* This macro is used to identify COMPHY related calls from SMC function ID */ 53 #define is_comphy_fid(fid) \ 54 ((fid) >= MV_SIP_COMPHY_POWER_ON && (fid) <= MV_SIP_COMPHY_DIG_RESET) 55 56 _Bool is_cp_range_valid(u_register_t *addr) 57 { 58 int cp_nr; 59 60 *addr &= MVEBU_CP_BASE_MASK; 61 for (cp_nr = 0; cp_nr < CP_NUM; cp_nr++) { 62 if (*addr == MVEBU_CP_REGS_BASE(cp_nr)) 63 return true; 64 } 65 66 return false; 67 } 68 69 uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, 70 u_register_t x1, 71 u_register_t x2, 72 u_register_t x3, 73 u_register_t x4, 74 void *cookie, 75 void *handle, 76 u_register_t flags) 77 { 78 u_register_t ret, read, x5 = x1; 79 int i; 80 81 debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 82 __func__, smc_fid, x1, x2, x3); 83 84 if (is_comphy_fid(smc_fid)) { 85 /* validate address passed via x1 */ 86 if (!is_cp_range_valid(&x1)) { 87 ERROR("%s: Wrong smc (0x%x) address: %lx\n", 88 __func__, smc_fid, x1); 89 SMC_RET1(handle, SMC_UNK); 90 } 91 92 x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS; 93 x1 += MVEBU_COMPHY_OFFSET; 94 95 if (x2 >= MAX_LANE_NR) { 96 ERROR("%s: Wrong smc (0x%x) lane nr: %lx\n", 97 __func__, smc_fid, x2); 98 SMC_RET1(handle, SMC_UNK); 99 } 100 } 101 102 switch (smc_fid) { 103 104 /* Comphy related FID's */ 105 case MV_SIP_COMPHY_POWER_ON: 106 /* x1: comphy_base, x2: comphy_index, x3: comphy_mode */ 107 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); 108 SMC_RET1(handle, ret); 109 case MV_SIP_COMPHY_POWER_OFF: 110 /* x1: comphy_base, x2: comphy_index */ 111 ret = mvebu_cp110_comphy_power_off(x1, x2, x3); 112 SMC_RET1(handle, ret); 113 case MV_SIP_COMPHY_PLL_LOCK: 114 /* x1: comphy_base, x2: comphy_index */ 115 ret = mvebu_cp110_comphy_is_pll_locked(x1, x2); 116 SMC_RET1(handle, ret); 117 case MV_SIP_COMPHY_XFI_TRAIN: 118 /* x1: comphy_base, x2: comphy_index */ 119 ret = mvebu_cp110_comphy_xfi_rx_training(x1, x2); 120 SMC_RET1(handle, ret); 121 case MV_SIP_COMPHY_DIG_RESET: 122 /* x1: comphy_base, x2: comphy_index, x3: mode, x4: command */ 123 ret = mvebu_cp110_comphy_digital_reset(x1, x2, x3, x4); 124 SMC_RET1(handle, ret); 125 126 /* Miscellaneous FID's' */ 127 case MV_SIP_DRAM_SIZE: 128 ret = mvebu_get_dram_size(MVEBU_REGS_BASE); 129 SMC_RET1(handle, ret); 130 case MV_SIP_LLC_ENABLE: 131 for (i = 0; i < ap_get_count(); i++) 132 llc_runtime_enable(i); 133 134 SMC_RET1(handle, 0); 135 #ifdef MVEBU_PMU_IRQ_WA 136 case MV_SIP_PMU_IRQ_ENABLE: 137 mvebu_pmu_interrupt_enable(); 138 SMC_RET1(handle, 0); 139 case MV_SIP_PMU_IRQ_DISABLE: 140 mvebu_pmu_interrupt_disable(); 141 SMC_RET1(handle, 0); 142 #endif 143 case MV_SIP_DFX: 144 if (x1 >= MV_SIP_DFX_THERMAL_INIT && 145 x1 <= MV_SIP_DFX_THERMAL_SEL_CHANNEL) { 146 ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3); 147 SMC_RET2(handle, ret, read); 148 } 149 if (x1 >= MV_SIP_DFX_SREAD && x1 <= MV_SIP_DFX_SWRITE) { 150 ret = mvebu_dfx_misc_handle(x1, &read, x2, x3); 151 SMC_RET2(handle, ret, read); 152 } 153 154 SMC_RET1(handle, SMC_UNK); 155 case MV_SIP_DDR_PHY_WRITE: 156 ret = mvebu_ddr_phy_write(x1, x2); 157 SMC_RET1(handle, ret); 158 case MV_SIP_DDR_PHY_READ: 159 read = 0; 160 ret = mvebu_ddr_phy_read(x1, (uint16_t *)&read); 161 SMC_RET2(handle, ret, read); 162 default: 163 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 164 SMC_RET1(handle, SMC_UNK); 165 } 166 } 167 168 /* Define a runtime service descriptor for fast SMC calls */ 169 DECLARE_RT_SVC( 170 marvell_sip_svc, 171 OEN_SIP_START, 172 OEN_SIP_END, 173 SMC_TYPE_FAST, 174 NULL, 175 mrvl_sip_smc_handler 176 ); 177